stm32f4xx: Significant rework of STM32F4 startup code.
Now it's pure C-based and unified. Need to bring the other STM32 families up to the same level of smarts.
This commit is contained in:
parent
65ac5c8bae
commit
50cdb0043a
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@ -9,9 +9,9 @@
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#define MCU_EXTSRAM_SIZE (0)
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#define MCU_EXTSRAM_BASE (0x68000000)
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#define MCU_FLASH_BASE (0x08000000)
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#define MCU_FLASH_SIZE (2048*1024)
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#define MCU_FLASH_SIZE (1024*1024)
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#define MCU_FLASH_PAGE_SIZE 2048
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#define MCU_FLASH_IMAGE_SIZE (2046*1024)
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#define MCU_STACK_SIZE 0x200
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#define MCU_FLASH_IMAGE_SIZE (1022*1024)
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#define MCU_STACK_SIZE 512
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#endif
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@ -89,11 +89,15 @@ task.h is included from an application file. */
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/* Assumes 8bit bytes! */
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#define heapBITS_PER_BYTE ( ( size_t ) 8 )
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#ifdef INTERNAL_HEAP /* XXXX */
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/* A few bytes might be lost to byte aligning the heap start address. */
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#define heapADJUSTED_HEAP_SIZE ( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT )
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/* Allocate the memory for the heap. */
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static unsigned char ucHeap[ configTOTAL_HEAP_SIZE ];
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#else
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unsigned char *ucHeap;
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#endif
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/* Define the linked list structure. This is used to link free blocks in order
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of their memory address. */
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@ -125,15 +129,23 @@ static void prvHeapInit( void );
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block must by correctly byte aligned. */
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static const unsigned short heapSTRUCT_SIZE = ( ( sizeof ( xBlockLink ) + ( portBYTE_ALIGNMENT - 1 ) ) & ~portBYTE_ALIGNMENT_MASK );
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#ifdef INTERNAL_HEAP /* XXX */
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/* Ensure the pxEnd pointer will end up on the correct byte alignment. */
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static const size_t xTotalHeapSize = ( ( size_t ) heapADJUSTED_HEAP_SIZE ) & ( ( size_t ) ~portBYTE_ALIGNMENT_MASK );
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#else
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size_t xTotalHeapSize;
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#endif
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/* Create a couple of list links to mark the start and end of the list. */
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static xBlockLink xStart, *pxEnd = NULL;
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/* Keeps track of the number of free bytes remaining, but says nothing about
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fragmentation. */
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#ifdef INTERNAL_HEAP /* XXX */
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static size_t xFreeBytesRemaining = ( ( size_t ) heapADJUSTED_HEAP_SIZE ) & ( ( size_t ) ~portBYTE_ALIGNMENT_MASK );
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#else
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size_t xFreeBytesRemaining;
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#endif
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/* Gets set to the top bit of an size_t type. When this bit in the xBlockSize
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member of an xBlockLink structure is set then the block belongs to the
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@ -3,6 +3,9 @@ ENTRY(Reset_Handler)
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MEMORY {
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SRAM (RWX) : ORIGIN = MCU_SRAM_BASE , LENGTH = MCU_SRAM_SIZE
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EXTSRAM (RWX) : ORIGIN = MCU_EXTSRAM_BASE , LENGTH = MCU_EXTSRAM_SIZE
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#ifdef MCU_CCRAM_BASE
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CCMRAM (RWX) : ORIGIN = MCU_CCRAM_BASE, LENGTH = MCU_CCRAM_SIZE
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#endif
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FLASH (RX) : ORIGIN = MCU_FLASH_BASE , LENGTH = MCU_FLASH_SIZE
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EEMUL (RWX) : ORIGIN = MCU_FLASH_BASE + MCU_FLASH_SIZE - MCU_FLASH_PAGE_SIZE, LENGTH = MCU_FLASH_PAGE_SIZE
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}
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@ -10,6 +13,7 @@ MEMORY {
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_estack = ORIGIN(SRAM)+LENGTH(SRAM); /* end of the stack */
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_seemul = ORIGIN(EEMUL); /* start of the eeprom emulation area */
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_min_stack = MCU_STACK_SIZE; /* minimum stack space to reserve for the user app */
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_eheap = _estack - _min_stack; /* Heap end is beginning of stack */
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/* check valid alignment for the vector table */
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ASSERT(ORIGIN(FLASH) == ALIGN(ORIGIN(FLASH), 0x80), "Start of memory region flash not aligned for startup vector table");
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@ -18,7 +22,7 @@ SECTIONS {
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/* vector table and program code goes into FLASH */
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.text : {
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. = ALIGN(0x80);
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_isr_vectors_offs = . - 0x08000000;
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_isr_vectors_offs = . - MCU_FLASH_BASE;
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KEEP(*(.isr_vector))
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. = ALIGN(4);
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CREATE_OBJECT_SYMBOLS
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@ -106,7 +110,9 @@ SECTIONS {
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_ebss = . ; /* exported for the startup function */
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_end = .;
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__end = .;
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_sheap = . ; /* exported for the startup function */
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} >SRAM AT>FLASH
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#if 0
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/* ensure there is enough room for the user stack */
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._usrstack (NOLOAD): {
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. = ALIGN(4);
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@ -115,7 +121,7 @@ SECTIONS {
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. = ALIGN(4);
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_eusrstack = . ;
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} >SRAM
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#endif
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/* Stabs debugging sections. */
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.stab 0 : { *(.stab) }
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.stabstr 0 : { *(.stabstr) }
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@ -11,8 +11,8 @@ MCU_CPPFLAGS += -D"assert_param(expr)=((void)0)"
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MCU_CFLAGS += -mcpu=cortex-m4 -mthumb -Wa,-mthumb
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# CMSIS
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STARTUP_OBJS = $(LIBDIR)/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.o $(LIBDIR)/startup_$(MCU_SUBTYPE).o
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#STARTUP_OBJS = $(LIBDIR)/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.o $(LIBDIR)/startup_$(MCU_SUBTYPE).o
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STARTUP_OBJS = src/startup_$(MCU).o
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# Standard Peripheral Library
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STM32F4xx_OBJSR = misc.o stm32f4xx_dma.o stm32f4xx_rcc.o stm32f4xx_adc.o \
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@ -31,6 +31,6 @@ STM32F4xx_OBJS += $(addprefix $(LIBDIR)/STM32F4xx_StdPeriph_Driver/src/,$(STM32F
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MCU_LIBS_OBJS += $(STM32F4xx_OBJS)
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# Build Rules
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$(LIBDIR)/startup_$(MCU_SUBTYPE).o: $(LIBDIR)/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc_ride7/startup_$(MCU_SUBTYPE).s
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@$(E) " AS " $@
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$(Q)$(AS) -c -o $@ $<
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#$(LIBDIR)/startup_$(MCU_SUBTYPE).o: $(LIBDIR)/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc_ride7/startup_$(MCU_SUBTYPE).s
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# @$(E) " AS " $@
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# $(Q)$(AS) -c -o $@ $<
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445
src/startup_stm32f4xx.c
Normal file
445
src/startup_stm32f4xx.c
Normal file
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@ -0,0 +1,445 @@
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#include <stdint.h>
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#include <sys/types.h>
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#include "stm32f4xx.h"
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#include "misc.h"
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typedef void( *const intfunc )( void );
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#define WEAK_HANDLER(__x) void __x (void) __attribute ((weak, alias("Default_Handler")));
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/* All of these are exposed by the linker script */
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extern unsigned long _etext;
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extern unsigned long _sidata;
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extern unsigned long _sdata;
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extern unsigned long _edata;
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extern unsigned long _sbss;
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extern unsigned long _ebss;
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extern unsigned long _estack;
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extern unsigned long _sheap;
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extern unsigned long _eheap;
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extern uint32_t _isr_vectors_offs;
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/* Main */
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extern int main(void);
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#ifdef INTERNAL_HEAP
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/* Track heap */
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size_t heapremain;
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size_t heapsize;
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void *heap_ptr;
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#else
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extern unsigned char *ucHeap;
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extern size_t xTotalHeapSize;
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extern size_t xFreeBytesRemaining;
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#endif
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static void __Init_Data(void) {
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unsigned long *src, *dst;
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/* copy the data segment into ram */
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src = &_sidata;
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dst = &_sdata;
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if (src != dst)
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while(dst < &_edata)
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*(dst++) = *(src++);
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/* zero the bss segment */
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dst = &_sbss;
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while(dst < &_ebss)
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*(dst++) = 0;
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#ifdef INTERNAL_HEAP
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/* Initialize Heap */
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heapremain = heapsize = &_eheap - &_sheap;
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heap_ptr = (void*) &_sheap;
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#else
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ucHeap = (unsigned char *) &_sheap;
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xTotalHeapSize = xFreeBytesRemaining = &_eheap - &_sheap;
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#endif
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}
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/* Endless loop for our default handler */
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void Default_Handler(void) {
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while (1) {}
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}
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//WEAK_HANDLER(Reset_Handler);
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WEAK_HANDLER(NMI_Handler);
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WEAK_HANDLER(HardFault_Handler);
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WEAK_HANDLER(MemManage_Handler);
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WEAK_HANDLER(BusFault_Handler);
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WEAK_HANDLER(UsageFault_Handler);
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WEAK_HANDLER(SVC_Handler);
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WEAK_HANDLER(DebugMon_Handler);
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WEAK_HANDLER(PendSV_Handler);
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WEAK_HANDLER(SysTick_Handler);
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WEAK_HANDLER(WWDG_IRQHandler);
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WEAK_HANDLER(PVD_IRQHandler);
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WEAK_HANDLER(TAMP_STAMP_IRQHandler);
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WEAK_HANDLER(RTC_WKUP_IRQHandler);
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WEAK_HANDLER(FLASH_IRQHandler);
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WEAK_HANDLER(RCC_IRQHandler);
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WEAK_HANDLER(EXTI0_IRQHandler);
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WEAK_HANDLER(EXTI1_IRQHandler);
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WEAK_HANDLER(EXTI2_IRQHandler);
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WEAK_HANDLER(EXTI3_IRQHandler);
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WEAK_HANDLER(EXTI4_IRQHandler);
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WEAK_HANDLER(DMA1_Stream0_IRQHandler);
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WEAK_HANDLER(DMA1_Stream1_IRQHandler);
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WEAK_HANDLER(DMA1_Stream2_IRQHandler);
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WEAK_HANDLER(DMA1_Stream3_IRQHandler);
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WEAK_HANDLER(DMA1_Stream4_IRQHandler);
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WEAK_HANDLER(DMA1_Stream5_IRQHandler);
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WEAK_HANDLER(DMA1_Stream6_IRQHandler);
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WEAK_HANDLER(ADC1_IRQHandler);
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WEAK_HANDLER(CAN1_TX_IRQHandler);
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WEAK_HANDLER(CAN1_RX0_IRQHandler);
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WEAK_HANDLER(CAN1_RX1_IRQHandler);
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WEAK_HANDLER(CAN1_SCE_IRQHandler);
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WEAK_HANDLER(EXTI9_5_IRQHandler);
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WEAK_HANDLER(TIM1_BRK_TIM9_IRQHandler);
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WEAK_HANDLER(TIM1_UP_TIM10_IRQHandler);
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WEAK_HANDLER(TIM1_TRG_COM_TIM11_IRQHandler);
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WEAK_HANDLER(TIM1_CC_IRQHandler);
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WEAK_HANDLER(TIM2_IRQHandler);
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WEAK_HANDLER(TIM3_IRQHandler);
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WEAK_HANDLER(TIM4_IRQHandler);
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WEAK_HANDLER(I2C1_EV_IRQHandler);
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WEAK_HANDLER(I2C1_ER_IRQHandler);
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WEAK_HANDLER(I2C2_EV_IRQHandler);
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WEAK_HANDLER(I2C2_ER_IRQHandler);
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WEAK_HANDLER(SPI1_IRQHandler);
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WEAK_HANDLER(SPI2_IRQHandler);
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WEAK_HANDLER(USART1_IRQHandler);
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WEAK_HANDLER(USART2_IRQHandler);
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WEAK_HANDLER(USART3_IRQHandler);
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WEAK_HANDLER(EXTI15_10_IRQHandler);
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WEAK_HANDLER(RTC_Alarm_IRQHandler);
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WEAK_HANDLER(OTG_FS_WKUP_IRQHandler);
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WEAK_HANDLER(TIM8_BRK_TIM12_IRQHandler);
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WEAK_HANDLER(TIM8_UP_TIM13_IRQHandler);
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WEAK_HANDLER(TIM8_TRG_COM_TIM14_IRQHandler);
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WEAK_HANDLER(TIM8_CC_IRQHandler);
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WEAK_HANDLER(DMA1_Stream7_IRQHandler);
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WEAK_HANDLER(FSMC_IRQHandler);
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WEAK_HANDLER(SDIO_IRQHandler);
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WEAK_HANDLER(TIM5_IRQHandler);
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WEAK_HANDLER(SPI3_IRQHandler);
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WEAK_HANDLER(UART4_IRQHandler);
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WEAK_HANDLER(UART5_IRQHandler);
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WEAK_HANDLER(TIM6_DAC_IRQHandler);
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WEAK_HANDLER(TIM7_IRQHandler);
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WEAK_HANDLER(DMA2_Stream0_IRQHandler);
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WEAK_HANDLER(DMA2_Stream1_IRQHandler);
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WEAK_HANDLER(DMA2_Stream2_IRQHandler);
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WEAK_HANDLER(DMA2_Stream3_IRQHandler);
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WEAK_HANDLER(DMA2_Stream4_IRQHandler);
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WEAK_HANDLER(ETH_IRQHandler);
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WEAK_HANDLER(ETH_WKUP_IRQHandler);
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WEAK_HANDLER(CAN2_TX_IRQHandler);
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WEAK_HANDLER(CAN2_RX0_IRQHandler);
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WEAK_HANDLER(CAN2_RX1_IRQHandler);
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WEAK_HANDLER(CAN2_SCE_IRQHandler);
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WEAK_HANDLER(OTG_FS_IRQHandler);
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WEAK_HANDLER(DMA2_Stream5_IRQHandler);
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WEAK_HANDLER(DMA2_Stream6_IRQHandler);
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WEAK_HANDLER(DMA2_Stream7_IRQHandler);
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WEAK_HANDLER(USART6_IRQHandler);
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WEAK_HANDLER(I2C3_EV_IRQHandler);
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WEAK_HANDLER(I2C3_ER_IRQHandler);
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WEAK_HANDLER(OTG_HS_EP1_OUT_IRQHandler);
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WEAK_HANDLER(OTG_HS_EP1_IN_IRQHandler);
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WEAK_HANDLER(OTG_HS_WKUP_IRQHandler);
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WEAK_HANDLER(OTG_HS_IRQHandler);
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WEAK_HANDLER(DCMI_IRQHandler);
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WEAK_HANDLER(CRYP_IRQHandler);
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WEAK_HANDLER(HASH_RNG_IRQHandler);
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WEAK_HANDLER(FPU_IRQHandler);
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WEAK_HANDLER(USART7_IRQHandler);
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WEAK_HANDLER(USART8_IRQHandler);
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WEAK_HANDLER(SPI4_IRQHandler);
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WEAK_HANDLER(SPI5_IRQHandler);
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WEAK_HANDLER(SPI6_IRQHandler);
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void Reset_Handler(void) {
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/* Initialize data and bss */
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__Init_Data();
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/* Set up base CPU stuffs. */
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SystemInit();
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/* Continue with boot */
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main();
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while(1) {}
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}
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__attribute__ ((section(".isr_vectors")))
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void (* const g_pfnVectors[])(void) = {
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(intfunc)((unsigned long)&_estack), /* The stack pointer after relocation */
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Reset_Handler, /* Reset Handler */
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NMI_Handler, /* NMI Handler */
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HardFault_Handler, /* Hard Fault Handler */
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MemManage_Handler, /* MPU Fault Handler */
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BusFault_Handler, /* Bus Fault Handler */
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UsageFault_Handler, /* Usage Fault Handler */
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0, /* Reserved */
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0, /* Reserved */
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0, /* Reserved */
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0, /* Reserved */
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SVC_Handler, /* SVCall Handler */
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DebugMon_Handler, /* Debug Monitor Handler */
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0, /* Reserved */
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PendSV_Handler, /* PendSV Handler */
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SysTick_Handler, /* SysTick Handler */
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/* External Interrupts */
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WWDG_IRQHandler, /* Window Watchdog */
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PVD_IRQHandler, /* PVD through EXTI Line detect */
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TAMP_STAMP_IRQHandler, /* Tamper and TimeSTamps through EXTI line */
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RTC_WKUP_IRQHandler, /* RTC */
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FLASH_IRQHandler, /* Flash */
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RCC_IRQHandler, /* RCC */
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EXTI0_IRQHandler, /* EXTI Line 0 */
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EXTI1_IRQHandler, /* EXTI Line 1 */
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EXTI2_IRQHandler, /* EXTI Line 2 */
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EXTI3_IRQHandler, /* EXTI Line 3 */
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EXTI4_IRQHandler, /* EXTI Line 4 */
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DMA1_Stream0_IRQHandler, /* DMA1 Stream 0 */
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DMA1_Stream1_IRQHandler, /* DMA1 Stream 1 */
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DMA1_Stream2_IRQHandler, /* DMA1 Stream 2 */
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DMA1_Stream3_IRQHandler, /* DMA1 Stream 3 */
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DMA1_Stream4_IRQHandler, /* DMA1 Stream 4 */
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DMA1_Stream5_IRQHandler, /* DMA1 Stream 5 */
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DMA1_Stream6_IRQHandler, /* DMA1 Stream 6 */
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ADC1_IRQHandler, /* ADC1, ADC2 & ADC3 */
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CAN1_TX_IRQHandler, /* CAN1 TX */
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CAN1_RX0_IRQHandler, /* CAN1 RX0 */
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CAN1_RX1_IRQHandler, /* CAN1 RX1 */
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CAN1_SCE_IRQHandler, /* CAN1 SCE */
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EXTI9_5_IRQHandler, /* EXTI Line 9..5 */
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TIM1_BRK_TIM9_IRQHandler, /* TIM1 Break and TIM9 */
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TIM1_UP_TIM10_IRQHandler, /* TIM1 Update and TIM10 */
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TIM1_TRG_COM_TIM11_IRQHandler, /* TIM1 Trigger and Commutation and TIM11 */
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TIM1_CC_IRQHandler, /* TIM1 Capture Compare */
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TIM2_IRQHandler, /* TIM2 */
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TIM3_IRQHandler, /* TIM3 */
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TIM4_IRQHandler, /* TIM4 */
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I2C1_EV_IRQHandler, /* I2C1 Event */
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I2C1_ER_IRQHandler, /* I2C1 Error */
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I2C2_EV_IRQHandler, /* I2C2 Event */
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I2C2_ER_IRQHandler, /* I2C2 Error */
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SPI1_IRQHandler, /* SPI1 */
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SPI2_IRQHandler, /* SPI2 */
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USART1_IRQHandler, /* USART1 */
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USART2_IRQHandler, /* USART2 */
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USART3_IRQHandler, /* USART3 */
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EXTI15_10_IRQHandler, /* EXTI Line 15..10 */
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RTC_Alarm_IRQHandler, /* RTC Alarm through EXTI Line */
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OTG_FS_WKUP_IRQHandler, /* USB OTG Wakeup through EXTI Line */
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TIM8_BRK_TIM12_IRQHandler,
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TIM8_UP_TIM13_IRQHandler,
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TIM8_TRG_COM_TIM14_IRQHandler,
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TIM8_CC_IRQHandler,
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DMA1_Stream7_IRQHandler,
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FSMC_IRQHandler,
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SDIO_IRQHandler,
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TIM5_IRQHandler,
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SPI3_IRQHandler, /* SPI3 */
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UART4_IRQHandler,
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UART5_IRQHandler,
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TIM6_DAC_IRQHandler,
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TIM7_IRQHandler, /* TIM7 */
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DMA2_Stream0_IRQHandler,
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DMA2_Stream1_IRQHandler,
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DMA2_Stream2_IRQHandler,
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DMA2_Stream3_IRQHandler,
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DMA2_Stream4_IRQHandler,
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ETH_IRQHandler,
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ETH_WKUP_IRQHandler,
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CAN2_TX_IRQHandler, /* CAN2 TX */
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CAN2_RX0_IRQHandler, /* CAN2 RX0 */
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CAN2_RX1_IRQHandler, /* CAN2 RX1 */
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CAN2_SCE_IRQHandler, /* CAN2 SCE */
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OTG_FS_IRQHandler,
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DMA2_Stream5_IRQHandler,
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DMA2_Stream6_IRQHandler,
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DMA2_Stream7_IRQHandler,
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USART6_IRQHandler,
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I2C3_EV_IRQHandler, /* I2C3 Event */
|
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I2C3_ER_IRQHandler, /* I2C3 Error */
|
||||
OTG_HS_EP1_OUT_IRQHandler,
|
||||
OTG_HS_EP1_IN_IRQHandler,
|
||||
OTG_HS_WKUP_IRQHandler,
|
||||
OTG_HS_IRQHandler,
|
||||
DCMI_IRQHandler,
|
||||
CRYP_IRQHandler,
|
||||
HASH_RNG_IRQHandler,
|
||||
FPU_IRQHandler,
|
||||
#if (MCU_SUBTYPE == stm32f427x)
|
||||
USART7_IRQHandler,
|
||||
USART8_IRQHandler,
|
||||
SPI4_IRQHandler, /* SPI4 */
|
||||
SPI5_IRQHandler, /* SPI5 */
|
||||
SPI6_IRQHandler, /* SPI6 */
|
||||
#endif
|
||||
};
|
||||
|
||||
/* ================================= */
|
||||
/* Lifted from system_stm32f4xx.c */
|
||||
|
||||
uint32_t SystemCoreClock = 168000000;
|
||||
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
#define VECT_TAB_OFFSET ((uint32_t)&_isr_vectors_offs)
|
||||
|
||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
|
||||
#define PLL_M 25
|
||||
#define PLL_N 336
|
||||
|
||||
/* SYSCLK = PLL_VCO / PLL_P */
|
||||
#define PLL_P 2
|
||||
|
||||
/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
|
||||
#define PLL_Q 7
|
||||
|
||||
static void SetSysClock(void) {
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSE) used as System clock source */
|
||||
/******************************************************************************/
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
/* Enable HSE */
|
||||
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do {
|
||||
HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CR & RCC_CR_HSERDY) != RESET) {
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
} else {
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01) {
|
||||
/* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */
|
||||
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
|
||||
PWR->CR |= PWR_CR_VOS;
|
||||
|
||||
/* HCLK = SYSCLK / 1*/
|
||||
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
|
||||
|
||||
/* PCLK2 = HCLK / 2*/
|
||||
RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
|
||||
|
||||
/* PCLK1 = HCLK / 4*/
|
||||
RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
|
||||
|
||||
/* Configure the main PLL */
|
||||
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
|
||||
(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
|
||||
|
||||
/* Enable the main PLL */
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
|
||||
/* Wait till the main PLL is ready */
|
||||
while((RCC->CR & RCC_CR_PLLRDY) == 0) { }
|
||||
|
||||
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
|
||||
FLASH->ACR = FLASH_ACR_PRFTEN |FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
|
||||
|
||||
/* Select the main PLL as system clock source */
|
||||
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
||||
RCC->CFGR |= RCC_CFGR_SW_PLL;
|
||||
|
||||
/* Wait till the main PLL is used as system clock source */
|
||||
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL) { }
|
||||
} else {
|
||||
/* If HSE fails to start-up, the application will have wrong clock
|
||||
configuration. User can add here some code to deal with this error */
|
||||
}
|
||||
}
|
||||
|
||||
void SystemInit(void) {
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||
/* Set HSION bit */
|
||||
RCC->CR |= (uint32_t)0x00000001;
|
||||
|
||||
/* Reset CFGR register */
|
||||
RCC->CFGR = 0x00000000;
|
||||
|
||||
/* Reset HSEON, CSSON and PLLON bits */
|
||||
RCC->CR &= (uint32_t)0xFEF6FFFF;
|
||||
|
||||
/* Reset PLLCFGR register */
|
||||
RCC->PLLCFGR = 0x24003010;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= (uint32_t)0xFFFBFFFF;
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIR = 0x00000000;
|
||||
|
||||
#ifdef DATA_IN_ExtSRAM
|
||||
SystemInit_ExtMemCtl();
|
||||
#endif /* DATA_IN_ExtSRAM */
|
||||
|
||||
/* Configure the System clock source, PLL Multiplier and Divider factors,
|
||||
AHB/APBx prescalers and Flash settings ----------------------------------*/
|
||||
SetSysClock();
|
||||
|
||||
/* Configure the Vector Table location add offset address ------------------*/
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
||||
#else
|
||||
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
|
||||
#endif
|
||||
}
|
||||
void SystemCoreClockUpdate(void) {
|
||||
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
tmp = RCC->CFGR & RCC_CFGR_SWS;
|
||||
|
||||
switch (tmp) {
|
||||
case 0x00: /* HSI used as system clock source */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
case 0x04: /* HSE used as system clock source */
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
case 0x08: /* PLL used as system clock source */
|
||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
|
||||
SYSCLK = PLL_VCO / PLL_P
|
||||
*/
|
||||
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
|
||||
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
||||
|
||||
if (pllsource != 0) {
|
||||
/* HSE used as PLL clock source */
|
||||
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
|
||||
} else {
|
||||
/* HSI used as PLL clock source */
|
||||
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
|
||||
}
|
||||
|
||||
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
|
||||
SystemCoreClock = pllvco/pllp;
|
||||
break;
|
||||
default:
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
}
|
||||
/* Compute HCLK frequency --------------------------------------------------*/
|
||||
/* Get HCLK prescaler */
|
||||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
|
||||
/* HCLK frequency */
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
Loading…
Reference in a new issue