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Nuke support for stm32w family (EOL'd in 2017 by ST)

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Solomon Peachy 2019-12-15 00:25:02 -05:00
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7
Makefile.opts.sample
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@ -29,13 +29,6 @@ MCU_SUBTYPE=stm32f446xx
#MCU_SUBTYPE=stm32l1xx_mdp
#MCU_SUBTYPE=stm32l1xx_hd
#MCU=stm32w108xx
#MCU_SUBTYPE=stm32w108c8
#MCU_SUBTYPE=stm32w108cc
#MCU_SUBTYPE=stm32w108cz
#MCU_SUBTYPE=stm32w108db
#MCU_SUBTYPE=stm32w108hz
#MCU=stm32f30x
#MCU=stm32f37x

1967
libs/CMSIS/Device/ST/STM32W108xx/Include/stm32w108xx.h
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File diff suppressed because it is too large Load diff

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libs/CMSIS/Device/ST/STM32W108xx/Include/system_stm32w108xx.h
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@ -1,104 +0,0 @@
/**
******************************************************************************
* @file system_stm32w108xx.h
* @author MCD Application Team
* @version V1.0.1
* @date 30-November-2012
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32w108xx_system
* @{
*/
/**
* @brief Define to prevent recursive inclusion
*/
#ifndef __SYSTEM_STM32W108XX_H
#define __SYSTEM_STM32W108XX_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup STM32W108xx_System_Includes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32W108xx_System_Exported_types
* @{
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* @}
*/
/** @addtogroup STM32W108xx_System_Exported_Constants
* @{
*/
/**
* @}
*/
/** @addtogroup STM32W108xx_System_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32W108xx_System_Exported_Functions
* @{
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__SYSTEM_STM32W108XX_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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libs/CMSIS/Device/ST/STM32W108xx/Release_Notes.html
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<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
Notes for<o:p></o:p> STM32W108xx CMSIS<br>
</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright 2012 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../../../../_htmresc/logo.bmp" style="border: 0px solid ; width: 86px; height: 65px;"></span></p>
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<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>
<ol style="margin-top: 0cm;" start="1" type="1">
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32W108xx CMSIS update history</a><o:p></o:p></span></li>
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>
</ol>
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32W108xx CMSIS update history<o:p></o:p></span></h2><span style="color: black;"><o:p></o:p></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 186px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.1 /30-November-2012</span></h3>
<span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;"><span style="font-weight: bold;"></span></span></span>
<span style="font-size: 10pt; font-family: Verdana;"></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 23px; width: 868px;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Development Toolchains<o:p></o:p></span></u></b></p>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">IAR Embedded Workbench for ARM (EWARM) toolchain V6.40<br>
</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;" lang="EN-US">Keil (MDK-ARM)&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">toolchain V4.54</span><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;" lang="EN-US"> </span><span style="font-size: 10pt; font-family: Verdana;"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;" lang="EN-US">TASKING VX-toolset for ARM Cortex-M3</span><b style=""><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;" lang="EN-US">&nbsp;</span></b><span style="font-size: 10pt; font-family: Verdana;">toolchain V4.2r1</span></li></ul><span style="font-size: 10pt; font-family: Verdana;"></span>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Raisonance IDE RIDE7
(RIDE)&nbsp;toolchain V7.40</span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Atollic TrueSTUDIO STM32
(TrueSTUDIO)&nbsp;toolchain V3.2.0</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 186px; margin-right: 500pt;"><span style="font-family: Arial; color: white; font-size: 10pt;">V1.0.0 /
09-October-2012</span></h3>
<p style="margin: 4.5pt 0cm 4.5pt 18pt;" class="MsoNormal"><b><u><span style="font-family: Verdana; color: black; font-size: 10pt;">Main
Changes<o:p></o:p></span></u></b></p><span style="font-family: Verdana; font-size: 10pt;">&nbsp; &nbsp; &nbsp;First official release
for </span><span style="font-family: Verdana; font-size: 10pt;"><span style="font-style: italic; font-weight: bold;">STM32W108xx</span></span><span style="font-family: Verdana; font-size: 10pt;"><span style="font-style: italic; font-weight: bold;"> devices </span></span><span style="font-family: Verdana; font-size: 10pt;">running on MBxxx
boards </span><br> <span style="font-family: Verdana; color: black; font-size: 10pt;"><o:p></o:p></span><span style="font-family: Verdana; font-size: 10pt;"></span><span style="font-family: Verdana; font-size: 10pt;"><span style="text-decoration: underline;"><span style="font-weight: bold;"></span></span></span><span style="font-family: Verdana; font-size: 10pt;"></span>
<p style="margin: 4.5pt 0cm 4.5pt 23px; width: 868px;" class="MsoNormal"><b><u><span style="font-family: Verdana; color: black; font-size: 10pt;">Development
Toolchains<o:p></o:p></span></u></b></p>
<span style="font-family: Verdana; font-size: 10pt;">&nbsp; &nbsp; &nbsp;IAR Embedded
Workbench for ARM (EWARM) toolchain V6.40</span><span style="font-size: 10pt; font-family: Verdana;"></span><ul style="margin-top: 0cm;" type="square"></ul>
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
<p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">package</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"> except in compliance with the License. You may obtain a copy of the License at:<br><br></span></p><div style="text-align: center;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a target="_blank" href="http://www.st.com/software_license_agreement_liberty_v2">http://www.st.com/software_license_agreement_liberty_v2</a></span><br><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"></span></div><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"><br>Unless
required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS, <br>WITHOUT
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See
the License for the specific language governing permissions and
limitations under the License.</span><p class="MsoNormal" style="margin: 4.5pt 0cm;"><b><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></b><span style="font-size: 10pt; font-family: Verdana; color: black;"><o:p></o:p></span></p>
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<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STMicroelectronics<span style="color: black;"> Microcontrollers visit </span><a target="_blank" href="http://www.st.com/internet/mcu/family/141.jsp"><u><span style="color: blue;">www.st.com</span></u></a></span><span style="color: black;"><o:p></o:p></span></p>
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266
libs/CMSIS/Device/ST/STM32W108xx/Source/Templates/TrueSTUDIO/startup_stm32w108xx.s
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@ -1,266 +0,0 @@
/**
******************************************************************************
* @file : startup_stm32w108xx.s
* Author : MCD Application Team
* Version : V0.0.1RC1
* Date : 18-April-2012
* @brief : stm32w108xx Devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the cortex-m3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF108F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M0. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word TIM1_IRQHandler
.word TIM2_IRQHandler
.word MNG_IRQHandler
.word BASEBAND_IRQHandler
.word SLPTIM_IRQHandler
.word SC1_IRQHandler
.word SC2_IRQHandler
.word SECURITY_IRQHandler
.word MAC_TIM_IRQHandler
.word MAC_TR_IRQHandler
.word MAC_RE_IRQHandler
.word ADC_IRQHandler
.word EXTIA_IRQHandler
.word EXTIB_IRQHandler
.word EXTIC_IRQHandler
.word EXTID_IRQHandler
.word DEBUG_IRQHandler
.word BootRAM /* @0x108. This is for boot in RAM mode for
stm32w108xx devices. */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak TIM1_IRQHandler
.thumb_set TIM1_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak MNG_IRQHandler
.thumb_set MNG_IRQHandler,Default_Handler
.weak BASEBAND_IRQHandler
.thumb_set BASEBAND_IRQHandler,Default_Handler
.weak SLPTIM_IRQHandler
.thumb_set SLPTIM_IRQHandler,Default_Handler
.weak SC1_IRQHandler
.thumb_set SC1_IRQHandler,Default_Handler
.weak SC2_IRQHandler
.thumb_set SC2_IRQHandler,Default_Handler
.weak SECURITY_IRQHandler
.thumb_set SECURITY_IRQHandler,Default_Handler
.weak MAC_TIM_IRQHandler
.thumb_set MAC_TIM_IRQHandler,Default_Handler
.weak MAC_TR_IRQHandler
.thumb_set MAC_TR_IRQHandler,Default_Handler
.weak MAC_RE_IRQHandler
.thumb_set MAC_RE_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak EXTIA_IRQHandler
.thumb_set EXTIA_IRQHandler,Default_Handler
.weak EXTIB_IRQHandler
.thumb_set EXTIB_IRQHandler,Default_Handler
.weak EXTIC_IRQHandler
.thumb_set EXTIC_IRQHandler,Default_Handler
.weak EXTID_IRQHandler
.thumb_set EXTID_IRQHandler,Default_Handler
.weak DEBUG_IRQHandler
.thumb_set DEBUG_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

231
libs/CMSIS/Device/ST/STM32W108xx/Source/Templates/arm/startup_stm32w108xx.s
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@ -1,231 +0,0 @@
;/**************************************************************************//**
; * @file startup_stm32w108.s
; * @brief CMSIS Core Device Startup File for
; * STM32W108 Device Series
; * @version V1.0.1
; * @date 30 November 2012
; *
; * @note
; * Copyright (C) 2012 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00001000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD TIM1_IRQHandler ; 16+ 0 Timer 1 Interrupt
DCD TIM2_IRQHandler ; 16+ 1 Timer 2 Interrupt
DCD MNG_IRQHandler ; 16+ 2 Management Peripheral Interrupt
DCD BASEBAND_IRQHandler ; 16+ 3 Base Band Interrupt
DCD SLPTIM_IRQHandler ; 16+ 4 Sleep Timer Interrupt
DCD SC1_IRQHandler ; 16+ 5 Serial Controller 1 Interrupt
DCD SC2_IRQHandler ; 16+ 6 Serial Controller 2 Interrupt
DCD SECURITY_IRQHandler ; 16+ 7 Security Interrupt
DCD MAC_TIM_IRQHandler ; 16+ 8 MAC Timer Interrupt
DCD MAC_TR_IRQHandler ; 16+ 9 MAC Transmit Interrupt
DCD MAC_RE_IRQHandler ; 16+10 MAC Receive Interrupt
DCD ADC_IRQHandler ; 16+11 ADC Interrupt
DCD EXTIA_IRQHandler ; 16+12 EXTIA Interrupt
DCD EXTIB_IRQHandler ; 16+13 EXTIB Interrupt
DCD EXTIC_IRQHandler ; 16+14 EXTIC Interrupt
DCD EXTID_IRQHandler ; 16+15 EXTID Interrupt
DCD DEBUG_IRQHandler ; 16+16 Debug Interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT TIM1_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT MNG_IRQHandler [WEAK]
EXPORT BASEBAND_IRQHandler [WEAK]
EXPORT SLPTIM_IRQHandler [WEAK]
EXPORT SC1_IRQHandler [WEAK]
EXPORT SC2_IRQHandler [WEAK]
EXPORT SECURITY_IRQHandler [WEAK]
EXPORT MAC_TIM_IRQHandler [WEAK]
EXPORT MAC_TR_IRQHandler [WEAK]
EXPORT MAC_RE_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT EXTIA_IRQHandler [WEAK]
EXPORT EXTIB_IRQHandler [WEAK]
EXPORT EXTIC_IRQHandler [WEAK]
EXPORT EXTID_IRQHandler [WEAK]
EXPORT DEBUG_IRQHandler [WEAK]
TIM1_IRQHandler
TIM2_IRQHandler
MNG_IRQHandler
BASEBAND_IRQHandler
SLPTIM_IRQHandler
SC1_IRQHandler
SC2_IRQHandler
SECURITY_IRQHandler
MAC_TIM_IRQHandler
MAC_TR_IRQHandler
MAC_RE_IRQHandler
ADC_IRQHandler
EXTIA_IRQHandler
EXTIB_IRQHandler
EXTIC_IRQHandler
EXTID_IRQHandler
DEBUG_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

252
libs/CMSIS/Device/ST/STM32W108xx/Source/Templates/gcc_ride7/startup_stm32w108xx.s
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@ -1,252 +0,0 @@
/**
******************************************************************************
* @file : startup_stm32w108xx.s
* Author : MCD Application Team
* Version : V0.0.1RC1
* Date : 18-April-2012
* @brief : stm32w108xx Devices vector table for Ride toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the cortex-m3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF108F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word TIM1_IRQHandler
.word TIM2_IRQHandler
.word MNG_IRQHandler
.word BASEBAND_IRQHandler
.word SLPTIM_IRQHandler
.word SC1_IRQHandler
.word SC2_IRQHandler
.word SECURITY_IRQHandler
.word MAC_TIM_IRQHandler
.word MAC_TR_IRQHandler
.word MAC_RE_IRQHandler
.word ADC_IRQHandler
.word EXTIA_IRQHandler
.word EXTIB_IRQHandler
.word EXTIC_IRQHandler
.word EXTID_IRQHandler
.word DEBUG_IRQHandler
.word BootRAM /* @0x108. This is for boot in RAM mode for
stm32w108xx devices. */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak TIM1_IRQHandler
.thumb_set TIM1_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak MNG_IRQHandler
.thumb_set MNG_IRQHandler,Default_Handler
.weak BASEBAND_IRQHandler
.thumb_set BASEBAND_IRQHandler,Default_Handler
.weak SLPTIM_IRQHandler
.thumb_set SLPTIM_IRQHandler,Default_Handler
.weak SC1_IRQHandler
.thumb_set SC1_IRQHandler,Default_Handler
.weak SC2_IRQHandler
.thumb_set SC2_IRQHandler,Default_Handler
.weak SECURITY_IRQHandler
.thumb_set SECURITY_IRQHandler,Default_Handler
.weak MAC_TIM_IRQHandler
.thumb_set MAC_TIM_IRQHandler,Default_Handler
.weak MAC_TR_IRQHandler
.thumb_set MAC_TR_IRQHandler,Default_Handler
.weak MAC_RE_IRQHandler
.thumb_set MAC_RE_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak EXTIA_IRQHandler
.thumb_set EXTIA_IRQHandler,Default_Handler
.weak EXTIB_IRQHandler
.thumb_set EXTIB_IRQHandler,Default_Handler
.weak EXTIC_IRQHandler
.thumb_set EXTIC_IRQHandler,Default_Handler
.weak EXTID_IRQHandler
.thumb_set EXTID_IRQHandler,Default_Handler
.weak DEBUG_IRQHandler
.thumb_set DEBUG_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

261
libs/CMSIS/Device/ST/STM32W108xx/Source/Templates/iar/startup_stm32w108xx.s
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@ -1,261 +0,0 @@
;/******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
;* File Name : startup_stm32w108xx.s
;* Author : MCD Application Team
;* Version : V1.0.1
;* Date : 30-November-2012
;* Description : STM32W108xx RF High Performance Devices vector table for *
;* EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************/
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD TIM1_IRQHandler ; Timer 1 Interrupt
DCD TIM2_IRQHandler ; Timer 2 Interrupt
DCD MNG_IRQHandler ; Management Peripheral Interrupt
DCD BASEBAND_IRQHandler ; Base Band Interrupt
DCD SLPTIM_IRQHandler ; Sleep Timer Interrupt
DCD SC1_IR