diff --git a/Makefile.opts.sample b/Makefile.opts.sample index e88b89f..64ed67b 100644 --- a/Makefile.opts.sample +++ b/Makefile.opts.sample @@ -29,13 +29,6 @@ MCU_SUBTYPE=stm32f446xx #MCU_SUBTYPE=stm32l1xx_mdp #MCU_SUBTYPE=stm32l1xx_hd -#MCU=stm32w108xx -#MCU_SUBTYPE=stm32w108c8 -#MCU_SUBTYPE=stm32w108cc -#MCU_SUBTYPE=stm32w108cz -#MCU_SUBTYPE=stm32w108db -#MCU_SUBTYPE=stm32w108hz - #MCU=stm32f30x #MCU=stm32f37x diff --git a/libs/CMSIS/Device/ST/STM32W108xx/Include/stm32w108xx.h b/libs/CMSIS/Device/ST/STM32W108xx/Include/stm32w108xx.h deleted file mode 100644 index 311fa5a..0000000 --- a/libs/CMSIS/Device/ST/STM32W108xx/Include/stm32w108xx.h +++ /dev/null @@ -1,1967 +0,0 @@ -/** - ****************************************************************************** - * @file stm32w108xx.h - * @author MCD Application Team - * @version V1.0.1 - * @date 30-November-2012 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32W108xx devices. - * - * The file is the unique include file that the application programmer - * is using in the C source code, usually in main.c. This file contains: - * - Configuration section that allows to select: - * - The device used in the target application - * - To use or not the peripheral’s drivers in application code(i.e. - * code will be based on direct access to peripheral’s registers - * rather than drivers API), this option is controlled by - * "#define USE_STDPERIPH_DRIVER" - * - To change few application-specific parameters such as the HSE - * crystal frequency - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32w108xx - * @{ - */ - -#ifndef __STM32W108XX_H -#define __STM32W108XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup Library_configuration_section - * @{ - */ - -/** Uncomment the line below according to the target STM32 device used in your - * application - */ - -#if !defined (STM32W108C8) && !defined (STM32W108CB) && !defined (STM32W108CC) && !defined (STM32W108CZ) && !defined (STM32W108HB) - /* #define STM32W108C8 */ /*!< STM32W108C8: 64k FLASH */ - /* #define STM32W108CB */ /*!< STM32W108CB: 128k FLASH */ - /* #define STM32W108CC */ /*!< STM32W108CC: 256k FLASH */ - /* #define STM32W108CZ */ /*!< STM32W108CZ: 192k FLASH */ - /* #define STM32W108HB */ /*!< STM32W108HB: 128k FLASH */ -#endif - -/** Tip: To avoid modifying this file each time you need to switch between these - * devices, you can define the device in your toolchain compiler preprocessor. - */ - -#if !defined (STM32W108C8) && !defined (STM32W108CB) && !defined (STM32W108CC) && !defined (STM32W108CZ) && !defined (STM32W108HB) - #error "Please select first the target STM32W108XX device used in your application (in stm32w108xx.h file)" -#endif - -#if !defined (USE_STDPERIPH_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - * In this case, these drivers will not be included and the application code will - * be based on direct access to peripherals registers - */ - - /* #define USE_STDPERIPH_DRIVER */ -#endif /* USE_STDPERIPH_DRIVER */ - -/** - * @brief In the following line adjust the value of External High Speed oscillator (HSE) - * used in your application - * - * Tip: To avoid modifying this file each time you need to use different HSE, you - * can define the HSE value in your toolchain compiler preprocessor. - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)24000000) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -/** - * @brief In the following line adjust the External High Speed oscillator (HSE) Startup - * Timeout value - */ -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief The internal high speed clock (HSI) should be calibrated before using it. - * The defined one is the theoretical value. - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)12000000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief The internal low speed clock (LSI) should be calibrated before using it. - * The defined one is the theoretical value. - */ -#if !defined (LSI_VALUE) -#define LSI_VALUE ((uint32_t)10000) /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -#endif - -/** - * @brief The following line define the External low Speed oscillator (LSE). - * - */ -#if !defined (LSE_VALUE) -#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ -#endif - -/** - * @brief STM32W108XX Standard Peripherals Library version number V0.0.1RC1 - */ -#define __STM32W108XX_STDPERIPH_VERSION_MAIN (0x00) /*!< [31:24] main version */ -#define __STM32W108XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ -#define __STM32W108XX_STDPERIPH_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ -#define __STM32W108XX_STDPERIPH_VERSION_RC (0x01) /*!< [7:0] release candidate */ -#define __STM32W108XX_STDPERIPH_VERSION ((__STM32W108XX_STDPERIPH_VERSION_MAIN << 24)\ - |(__STM32W108XX_STDPERIPH_VERSION_SUB1 << 16)\ - |(__STM32W108XX_STDPERIPH_VERSION_SUB2 << 8)\ - |(__STM32W108XX_STDPERIPH_VERSION_RC)) -/** - * @} - */ - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#define __CM3_REV 0x0101 /*!< Core revision r1p1 */ -#define __MPU_PRESENT 1 /*!< STM32W108XX provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32W108XX uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 0 /*!< FPU is not present */ - -/** - * @brief STM32W108XX Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ****************************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ -/****** STM32W108xx specific Interrupt Numbers ****************************************************************/ - TIM1_IRQn = 0, /*!< Timer 1 Interrupt */ - TIM2_IRQn = 1, /*!< Timer 1 Interrupt */ - MNG_IRQn = 2, /*!< Management Peripheral Interrupt */ - BASEBAND_IRQn = 3, /*!< Base Band Interrupt */ - SLPTIM_IRQn = 4, /*!< Sleep Timer Interrupt */ - SC1_IRQn = 5, /*!< Serial Controller 1 Interrupt */ - SC2_IRQn = 6, /*!< Serial Controller 2 Interrupt */ - SECURITY_IRQn = 7, /*!< Security Interrupt */ - MAC_TIM_IRQn = 8, /*!< MAC Timer Interrupt */ - MAC_TR_IRQn = 9, /*!< MAC Transmit Interrupt */ - MAC_RE_IRQn = 10, /*!< MAC Receive Interrupt */ - ADC_IRQn = 11, /*!< ADC Interrupt */ - EXTIA_IRQn = 12, /*!< EXTI port A interrupt */ - EXTIB_IRQn = 13, /*!< EXTI port B interrupt */ - EXTIC_IRQn = 14, /*!< EXTI port C interrupt */ - EXTID_IRQn = 15, /*!< EXTI port D interrupt */ - DEBUG_IRQn = 16 /*!< Debug Interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ -#include "system_stm32w108xx.h" -#include - -/** @addtogroup Exported_types - * @{ - */ - - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; - -/** - * @} - */ - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Clock Controller Registers - */ -typedef struct -{ - __IO uint32_t SLEEPCR; /*!< Sleep timer control register, Address offset: 0x0008 */ - __IO uint32_t LSI10KCR; /*!< LSI Clock (10KHz) control register, Address offset: 0x000C */ - __IO uint32_t LSI1KCR; /*!< LSI Clock (1KHz) control register, Address offset: 0x0010 */ - uint32_t RESERVED0[4092]; /*!< Reserved */ - __IO uint32_t HSECR1; /*!< HSE Clock (24MHz) control register 1, Address offset: 0x4004 */ - __IO uint32_t HSICR; /*!< HSI Clock (12MHz) trim register, Address offset: 0x4008 */ - __IO uint32_t HSECOMPR; /*!< HSE comparator Output, Address offset: 0x400C */ - __IO uint32_t PERIODCR; /*!< Clock period control register, Address offset: 0x4010 */ - __IO uint32_t PERIODSR; /*!< Clock period status register, Address offset: 0x4014 */ - __IO uint32_t DITHERCR; /*!< Clock dither control register, Address offset: 0x4018 */ - __IO uint32_t HSECR2; /*!< HSE Clock (24MHz) control register 2, Address offset: 0x401C */ - __IO uint32_t CPUCR; /*!< Clock source select register, Address offset: 0x4020 */ -} CLK_TypeDef; - -/** - * @brief Power Management Registers (PWR) - */ -typedef struct -{ - __IO uint32_t DSLEEPCR1; /*!< Deep Sleep Control register 1 Address offset 0x0004 */ - uint32_t RESERVED0[3]; /*!< Reserved */ - __IO uint32_t DSLEEPCR2; /*!< Deep Sleep Control register 2 Address offset 0x0014 */ - __IO uint32_t VREGCR; /*!< Voltage regulator Control register 1 Address offset 0x0018 */ - uint32_t RESERVED1; /*!< Reserved */ - __IO uint32_t WAKECR1; /*!< Wake Control register 1 Address offset 0x0020 */ - __IO uint32_t WAKECR2; /*!< Wake Control register 2 Address offset 0x0024 */ - __IO uint32_t WAKESR; /*!< Wake Status register Address offset 0x0028 */ - uint32_t RESERVED2[2]; /*!< Reserved */ - __IO uint32_t CPWRUPREQSR; /*!< CPWRUPREQ status register Address offset 0x0034 */ - __IO uint32_t CSYSPWRUPREQSR; /*!< CSYSPWRUPREQ status register Address offset 0x0038 */ - __IO uint32_t CSYSPWRUPACKSR; /*!< CSYSPWRUPACK status register Address offset 0x003C */ - __IO uint32_t CSYSPWRUPACKCR; /*!< CSYSPWRUPACK control register Address offset 0x0040 */ - uint32_t RESERVED3[12017]; /*!< Reserved */ - __IO uint32_t WAKEPAR; /*!< Wake GPIO Port A register Address offset 0xBC08 */ - __IO uint32_t WAKEPBR; /*!< Wake GPIO Port B register Address offset 0xBC0C */ - __IO uint32_t WAKEPCR; /*!< Wake GPIO Port C register Address offset 0xBC10 */ - uint32_t RESERVED4[2]; /*!< Reserved */ - __IO uint32_t WAKEFILTR; /*!< Wake filter register Address offset 0xBC1C */ -} PWR_TypeDef; - -/** - * @brief Reset Registers - */ -typedef struct -{ - __IO uint32_t SR; /*!< Reset Status Register Address offset: 0x002C */ -} RST_TypeDef; - -/** - * @brief FLASH Registers - */ -typedef struct -{ - __IO uint32_t CLKER; /*!< FLASH controller clock enable register Address offset: 0x402C */ - __IO uint32_t CLKSR; /*!< FLASH controller clock status register Address offset: 0x4030 */ - uint32_t RESERVED0[4083]; /*!< Reserved */ - __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x8000 */ - __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x8004 */ - __IO uint32_t OPTKEYR; /*!< FLASH OPT key register, Address offset: 0x8008 */ - __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x800C */ - __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x8010 */ - __IO uint32_t AR; /*!< FLASH address register, Address offset: 0x8014 */ - uint32_t RESERVED1; /*!< Reserved */ - __IO uint32_t OBR; /*!< FLASH option bytes register, Address offset: 0x801C */ - __IO uint32_t WRPR; /*!< FLASH option bytes register, Address offset: 0x8020 */ -} FLASH_TypeDef; - -/** - * @brief Memory Registers - */ -typedef struct -{ - __IO uint32_t RAMPROTR1; /*!< Memory protection register1, Address offset: 0x5000 */ - __IO uint32_t RAMPROTR2; /*!< Memory protection register2, Address offset: 0x5004 */ - __IO uint32_t RAMPROTR3; /*!< Memory protection register3, Address offset: 0x5008 */ - __IO uint32_t RAMPROTR4; /*!< Memory protection register4, Address offset: 0x500C */ - __IO uint32_t RAMPROTR5; /*!< Memory protection register5, Address offset: 0x5010 */ - __IO uint32_t RAMPROTR6; /*!< Memory protection register6, Address offset: 0x5014 */ - __IO uint32_t RAMPROTR7; /*!< Memory protection register7, Address offset: 0x5018 */ - __IO uint32_t RAMPROTR8; /*!< Memory protection register8, Address offset: 0x501C */ - __IO uint32_t DMAPROTR1; /*!< DMA protection register1, Address offset: 0x5020 */ - __IO uint32_t DMAPROTR2; /*!< DMA protection register2, Address offset: 0x5024 */ - __IO uint32_t RAMCR; /*!< Memory configuration register, Address offset: 0x5028 */ -} MEM_TypeDef; - -/** - * @brief Option Bytes Registers - */ -typedef struct -{ - __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address 0x00 */ - __IO uint16_t Rsvd0; /*!< Reserved */ - __IO uint16_t Rsvd1; /*!< Reserved */ - __IO uint16_t Rsvd2; /*!< Reserved */ - __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */ - __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */ - __IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */ - __IO uint16_t WRP3; /*!< FLASH option byte write protection 0, Address offset: 0x0E */ -} OB_TypeDef; - -/** - * @brief GPIO Registers - */ -typedef struct -{ - __IO uint32_t CRL; /*!< GPIO port configuration low register, Address offset: 0x00 */ - __IO uint32_t CRH; /*!< GPIO port configuration high register, Address offset: 0x04 */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x08 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x0C */ - __IO uint32_t BSR; /*!< GPIO port bit set registerBSR, Address offset: 0x10 */ - __IO uint32_t BRR; /*!< GPIO port bit reset registerBRR, Address offset: 0x14 */ -} GPIO_TypeDef; - -/** - * @brief GPIO Debug Registers - */ -typedef struct -{ - __IO uint32_t PCTRACECR; /*!< Clock PC trace register, Address offset 0x4028 */ - uint32_t RESERVED[7925]; - __IO uint32_t DBGCR; /*!< GPIO debug configuration register, Address offset 0xBC00 */ - __IO uint32_t DBGSR; /*!< GPIO debug status register, Address offset 0xBC04 */ -} GPIO_DBG_TypeDef; - -/** - * @brief Management interrupt Registers - */ -typedef struct -{ - __IO uint32_t ISR; /*!< Management Interrupt status Register, Address offset 0xA018 */ - uint32_t RESERVED0[15]; /*!< Reserved */ - __IO uint32_t IER; /*!< Management Interrupt Enable Register, Address offset 0xA058 */ -} MGMT_IT_TypeDef; - -/** - * @brief EXTI Registers - */ - -typedef struct -{ - __IO uint32_t PR; /*!< EXTI pending register, Address offset 0xA814 */ - uint32_t RESERVED0[18]; /*!< Reserved */ - __IO uint32_t TSR[4]; /*!< EXTI trigger source register, Address offset 0xA860 */ - uint32_t RESERVED1[1257]; /*!< Reserved */ - __IO uint32_t CR[2]; /*!< EXTI configuration register, Address offset 0xBC14 */ -} EXTI_TypeDef; - -/** - * @brief WDG Registers - */ - -typedef struct -{ - __IO uint32_t CR; /*!< WDG configuration register, Address offset 0x6000 */ - __IO uint32_t KR; /*!< WDG key register, Address offset 0x6004 */ - __IO uint32_t KICKSR; /*!< WDG kick-start register, Address offset 0x6008 */ -} WDG_TypeDef; - -/** - * @brief Sleep Timer Registers - */ -typedef struct -{ - __IO uint32_t CR; /*!< SLPTMR configuration register, Address offset 0x600C */ - __IO uint32_t CNTH; /*!< SLPTMR counter high register, Address offset 0x6010 */ - __IO uint32_t CNTL; /*!< SLPTMR counter high register, Address offset 0x6014 */ - __IO uint32_t CMPAH; /*!< SLPTMR compare A high register, Address offset 0x6018 */ - __IO uint32_t CMPAL; /*!< SLPTMR compare A low register, Address offset 0x601C */ - __IO uint32_t CMPBH; /*!< SLPTMR compare B high register, Address offset 0x6020 */ - __IO uint32_t CMPBL; /*!< SLPTMR compare B low register, Address offset 0x6024 */ - uint32_t RESERVED0[4091]; /*!< Reserved */ - __IO uint32_t ISR; /*!< SLPTMR interrupt status register, Address offset 0xA014 */ - uint32_t RESERVED1[2]; /*!< Reserved */ - __IO uint32_t IFR; /*!< SLPTMR force interrupts register, Address offset 0xA020 */ - uint32_t RESERVED2[12]; /*!< Reserved */ - __IO uint32_t IER; /*!< SLPTMR interrupt enable register, Address offset 0xA054 */ -} SLPTMR_TypeDef; - -/** - * @brief MAC Timer Registers - */ -typedef struct -{ - __IO uint32_t CNTR; /*!< MACTMR counter register, Address offset 0x2038 */ - uint32_t RESERVED[20]; /*!< Reserved */ - __IO uint32_t CR; /*!< MACTMR configuration register, Address offset 0x208C */ -} MACTMR_TypeDef; - -/** - * @brief Analog to Digital Converter (ADC) Registers - */ -typedef struct -{ - __IO uint32_t ISR; /*!< ADC Interrupt Status Register, Address offset: 0xA810 */ - uint32_t RESERVED0[15]; /*!< Reserved */ - __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0xA850 */ - uint32_t RESERVED1[2540]; /*!< Reserved.*/ - __IO uint32_t CR; /*!< ADC Configuration Register, Address offset: 0xD004 */ - __IO uint32_t OFFSETR; /*!< ADC Offset Register, Address offset: 0xD008 */ - __IO uint32_t GAINR; /*!< ADC Gain Register, Address offset: 0xD00C */ - __IO uint32_t DMACR; /*!< ADC DMA Configuration Register, Address offset: 0xD010 */ - __IO uint32_t DMASR; /*!< ADC DMA Status Register, Address offset: 0xD014 */ - __IO uint32_t DMAMSAR; /*!< ADC DMA Memory Start Address Register, Address offset: 0xD018 */ - __IO uint32_t DMANDTR; /*!< ADC DMA Number of Data Register, Address offset: 0xD01C */ - __IO uint32_t DMAMNAR; /*!< ADC DMA Memory Next Address Register, Address offset: 0xD020 */ - __IO uint32_t DMACNDTR; /*!< ADC DMA Channel Number of Data Register, Address offset: 0xD024 */ -} ADC_TypeDef; - -/** - * @brief Timer Registers - */ -typedef struct -{ - __IO uint32_t CR1; /*!< TIM control register 1, Address offset 0x00 */ - __IO uint32_t CR2; /*!< TIM control register 2, Address offset 0x04 */ - __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset 0x08 */ - uint32_t RESERVED0[2]; /*!< Reserved */ - __IO uint32_t EGR; /*!< TIM event generation register Address offset 0x14 */ - __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset 0x18 */ - __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset 0x1C */ - __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset 0x20 */ - __IO uint32_t CNT; /*!< TIM counter register, Address offset 0x24 */ - __IO uint32_t PSC; /*!< TIM prescaler register, Address offset 0x28 */ - __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset 0x2C */ - uint32_t RESERVED1; /*!< Reserved */ - __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset 0x34 */ - __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset 0x38 */ - __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset 0x3C */ - __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset 0x40 */ - uint32_t RESERVED2[3]; /*!< Reserved */ - __IO uint32_t OR; /*!< TIM option register, Address offset 0x50 */ -} TIM_TypeDef; - -/** - * @brief Serial Controller Registers (Universal Asynchronous Receiver/Transmitter) - */ -typedef struct -{ - __IO uint32_t DR; /*!< Serial control Data register Address offset 0x00 */ - uint32_t RESERVED0[2]; /*!< Reserved */ - __IO uint32_t UARTSR; /*!< UART control register Address offset 0x08 */ - uint32_t RESERVED1[2]; /*!< Reserved */ - __IO uint32_t CR; /*!< Serial control control register Address offset 0x14 */ - uint32_t RESERVED2[1]; /*!< Reserved */ - __IO uint32_t UARTCR; /*!< UART control register Address offset 0x1C */ - uint32_t RESERVED3[2]; /*!< Reserved */ - __IO uint32_t UARTBRR1; /*!< UART Baud rate register 1 Address offset 0x28 */ - __IO uint32_t UARTBRR2; /*!< UART Baud rate register 2 Address offset 0x2C */ -} SC_UART_TypeDef; - -/** - * @brief Serial Controller Registers (Serial peripheral interface) - */ -typedef struct -{ - __IO uint32_t DR; /*!< Serial control Data register Address offset 0x00 */ - __IO uint32_t SPISR; /*!< SPI status register Address offset 0x04 */ - uint32_t RESERVED0[4]; /*!< Reserved */ - __IO uint32_t CR; /*!< Serial control control register Address offset 0x18 */ - __IO uint32_t SPICR; /*!< SPI status register Address offset 0x1C */ - uint32_t RESERVED1[1]; /*!< Reserved */ - __IO uint32_t CRR1; /*!< Serial control clock rate register 1 Address offset 0x24 */ - __IO uint32_t CRR2; /*!< Serial control clock rate register 2 Address offset 0x28 */ -} SC_SPI_TypeDef; - -/** - * @brief Serial Controller Registers (Inter-Integrated circuit) - */ -typedef struct -{ - __IO uint32_t DR; /*!< Serial control Data register Address offset 0x00 */ - uint32_t RESERVED0[1]; /*!< Reserved */ - __IO uint32_t I2CSR; /*!< I2C status register Address offset 0x08 */ - uint32_t RESERVED1[1]; /*!< Reserved */ - __IO uint32_t I2CCR1; /*!< I2C control register 1 Address offset 0x10 */ - __IO uint32_t I2CCR2; /*!< I2C control register 2 Address offset 0x14 */ - __IO uint32_t CR; /*!< Serial control control register Address offset 0x18 */ - uint32_t RESERVED2[2]; /*!< Reserved */ - __IO uint32_t CRR1; /*!< Serial control clock rate register 1 Address offset 0x24 */ - __IO uint32_t CRR2; /*!< Serial control clock rate register 2 Address offset 0x28 */ -} SC_I2C_TypeDef; - -/** - * @brief Timer Interrupt Registers - */ -typedef struct -{ - __IO uint32_t ISR; /*!< TIM interrupt and status register Address offset 0x00 */ - uint32_t RESERVED0[5]; /*!< Reserved */ - __IO uint32_t IMR; /*!< TIM interrupt missed register Address offset 0x18 */ - uint32_t RESERVED1[9]; /*!< Reserved */ - __IO uint32_t IER; /*!< TIM interrupt enable register Address offset 0x40 */ -} TIM_IT_TypeDef; - -/** - * @brief Serial Controller interrupt Registers - */ -typedef struct -{ - __IO uint32_t ISR; /*!< Interrupt Status register Address offset 0x08 */ - uint32_t RESERVED0[15]; /*!< Reserved */ - __IO uint32_t IER; /*!< Interrupt Enable register Address offset 0x48 */ - uint32_t RESERVED1[2]; /*!< Reserved */ - __IO uint32_t ICR; /*!< Interrupt Control register Address offset 0x54 */ -} SC_IT_TypeDef; - -/** - * @brief Serial Controller DMA Registers - */ -typedef struct -{ - __IO uint32_t DMARXCNTAR; /*!< DMA Rx counter A register Address offset 0x20 */ - __IO uint32_t DMARXCNTBR; /*!< DMA Rx counter B register Address offset 0x24 */ - __IO uint32_t DMATXCNTR; /*!< DMA Tx counter register Address offset 0x28 */ - __IO uint32_t DMASR; /*!< DMA status register Address offset 0x2C */ - __IO uint32_t DMACR; /*!< DMA control register Address offset 0x30 */ - __IO uint32_t DMARXERRAR; /*!< DMA Rx error A register Address offset 0x34 */ - __IO uint32_t DMARXERRBR; /*!< DMA Rx error B register Address offset 0x38 */ - uint32_t RESERVED0[13]; /*!< Reserved */ - __IO uint32_t DMARXCNTSAVEDR; /*!< DMA Rx Counter saved register Address offset 0x70 */ -} SC_DMA_TypeDef; - -/** - * @brief Serial Controller DMA Channel Registers - */ -typedef struct -{ - __IO uint32_t DMABEGADDAR; /*!< DMA begin address A register Address offset 0x00 */ - __IO uint32_t DMAENDADDAR; /*!< DMA end address A register Address offset 0x04 */ - __IO uint32_t DMABEGADDBR; /*!< DMA begin address B register Address offset 0x08 */ - __IO uint32_t DMAENDADDBR; /*!< DMA end address B register Address offset 0x0C */ -} SC_DMA_Channel_TypeDef; - -/** @addtogroup Peripheral_memory_map - * @{ - */ -#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ -#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ - -#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ - -/*!< Peripheral memory map */ -#define PWR_BASE (PERIPH_BASE + 0x0004) -#define CLK_BASE (PERIPH_BASE + 0x0008) -#define RST_BASE (PERIPH_BASE + 0x002C) -#define MACTMR_BASE (PERIPH_BASE + 0x2038) -#define GPIO_DBG_BASE (PERIPH_BASE + 0x4028) -#define FLASH_R_BASE (PERIPH_BASE + 0x402C) -#define MEM_R_BASE (PERIPH_BASE + 0x5000) -#define WDG_BASE (PERIPH_BASE + 0x6000) -#define SLPTMR_BASE (PERIPH_BASE + 0x600C) -#define ADC_BASE (PERIPH_BASE + 0xA810) -#define EXTI_BASE (PERIPH_BASE + 0xA814) -#define GPIOA_BASE (PERIPH_BASE + 0xB000) -#define GPIOB_BASE (PERIPH_BASE + 0xB400) -#define GPIOC_BASE (PERIPH_BASE + 0xB800) -#define SC1_UART_BASE (PERIPH_BASE + 0xC83C) -#define SC1_SPI_BASE (PERIPH_BASE + 0xC83C) -#define SC1_I2C_BASE (PERIPH_BASE + 0xC83C) -#define SC2_UART_BASE (PERIPH_BASE + 0xC03C) -#define SC2_SPI_BASE (PERIPH_BASE + 0xC03C) -#define SC2_I2C_BASE (PERIPH_BASE + 0xC03C) -#define TIM1_BASE (PERIPH_BASE + 0xE000) -#define TIM2_BASE (PERIPH_BASE + 0xF000) -#define OB_BASE ((uint32_t)0x08040800) /*!< Flash Option Bytes base address */ - -#define MGMT_IT_BASE (PERIPH_BASE + 0xA018) -#define TIM1_IT_BASE (PERIPH_BASE + 0xA800) -#define TIM2_IT_BASE (PERIPH_BASE + 0xA804) -#define SC1_IT_BASE (PERIPH_BASE + 0xA808) -#define SC2_IT_BASE (PERIPH_BASE + 0xA80C) - -#define SC2_DMA_ChannelRx_BASE (PERIPH_BASE + 0xC000) -#define SC2_DMA_ChannelTx_BASE (PERIPH_BASE + 0xC010) -#define SC2_DMA_BASE (PERIPH_BASE + 0xC020) - -#define SC1_DMA_ChannelRx_BASE (PERIPH_BASE + 0xC800) -#define SC1_DMA_ChannelTx_BASE (PERIPH_BASE + 0xC810) -#define SC1_DMA_BASE (PERIPH_BASE + 0xC820) - -/** @addtogroup Peripheral_declaration - * @{ - */ - -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define CLK ((CLK_TypeDef *) CLK_BASE) -#define RST ((RST_TypeDef *) RST_BASE) -#define MACTMR ((MACTMR_TypeDef *) MACTMR_BASE) -#define GPIO_DBG ((GPIO_DBG_TypeDef *) GPIO_DBG_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define MEM ((MEM_TypeDef *) MEM_R_BASE) -#define WDG ((WDG_TypeDef *) WDG_BASE) -#define SLPTMR ((SLPTMR_TypeDef *) SLPTMR_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define SC1_UART ((SC_UART_TypeDef *) SC1_UART_BASE) -#define SC1_SPI ((SC_SPI_TypeDef *) SC1_SPI_BASE) -#define SC1_I2C ((SC_I2C_TypeDef *) SC1_I2C_BASE) -#define SC2_UART ((SC_UART_TypeDef *) SC2_UART_BASE) -#define SC2_SPI ((SC_SPI_TypeDef *) SC2_SPI_BASE) -#define SC2_I2C ((SC_I2C_TypeDef *) SC2_I2C_BASE) -#define ADC ((ADC_TypeDef *) ADC_BASE) -#define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define OB ((OB_TypeDef *) OB_BASE) - -#define MGMT_IT ((MGMT_IT_TypeDef *) MGMT_IT_BASE) -#define TIM1_IT ((TIM_IT_TypeDef *) TIM1_IT_BASE) -#define TIM2_IT ((TIM_IT_TypeDef *) TIM2_IT_BASE) -#define SC1_IT ((SC_IT_TypeDef *) SC1_IT_BASE) -#define SC2_IT ((SC_IT_TypeDef *) SC2_IT_BASE) - -#define SC2_DMA_ChannelRx ((SC_DMA_Channel_TypeDef *) SC2_DMA_ChannelRx_BASE) -#define SC2_DMA_ChannelTx ((SC_DMA_Channel_TypeDef *) SC2_DMA_ChannelTx_BASE) -#define SC2_DMA ((SC_DMA_TypeDef *) SC2_DMA_BASE) - -#define SC1_DMA_ChannelRx ((SC_DMA_Channel_TypeDef *) SC1_DMA_ChannelRx_BASE) -#define SC1_DMA_ChannelTx ((SC_DMA_Channel_TypeDef *) SC1_DMA_ChannelTx_BASE) -#define SC1_DMA ((SC_DMA_TypeDef *) SC1_DMA_BASE) - -/** - * @} - */ - -/** @defgroup PPP_Exported_Constants - * @{ - */ - -/** @defgroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* */ -/* Clock Control (CLK) */ -/* */ -/******************************************************************************/ -/******************** Bit definition for CLK_SLEEPCR register ***************/ -#define CLK_SLEEPCR_LSEEN ((uint32_t)0x00000001) /*!< Enables 32kHz external XTAL */ -#define CLK_SLEEPCR_LSI10KEN ((uint32_t)0x00000002) /*!< Enables 10kHz internal RC during deep */ - -/******************** Bit definition for CLK_LSI10KCR register **************/ -#define CLK_LSI10KCR_TUNE ((uint32_t)0x0000000F) /*!< Tune value for clkrc */ - -/******************** Bit definition for CLK_LSI1KCR register ***************/ -#define CLK_LSI1KCR_CALFRAC ((uint32_t)0x000007FF) /*!< Divider value fractional portion */ -#define CLK_LSI1KCR_CALINT ((uint32_t)0x0000F800) /*!< Divider value integer portion */ - -/******************** Bit definition for CLK_HSECR1 register ****************/ -#define CLK_HSECR1_BIASTRIM ((uint32_t)0x0000000F) /*!< Bias trim setting for 24MHz oscillator */ - -/******************** Bit definition for CLK_HSICR register *****************/ -#define CLK_HSICR_TUNE ((uint32_t)0x0000001F) /*!< Frequency trim setting for HF RC oscillator */ - -/******************** Bit definition for CLK_HSECOMPR register **************/ -#define CLK_HSECOMPR_HLEVEL ((uint32_t)0x00000002) /*!< Frequency trim setting for HF RC oscillator */ -#define CLK_HSECOMPR_LLEVEL ((uint32_t)0x00000001) /*!< Frequency trim setting for HF RC oscillator */ - -/******************** Bit definition for CLK_PERIODCR register **************/ -#define CLK_PERIODCR_MODE ((uint32_t)0x00000003) /*!< Sets clock to be measured by CLK_PERIOD */ - -/******************** Bit definition for CLK_PERIODSR register **************/ -#define CLK_PERIODSR_PERIOD ((uint32_t)0x0000FFFF) /*!< Clock period measurement */ - -/******************** Bit definition for CLK_DITHERCR register **************/ -#define CLK_DITHERCR_DIS ((uint32_t)0x00000001) /*!< Dither disable */ - -/******************** Bit definition for CLK_HSECR2 register ****************/ -#define CLK_HSECR2_SW1 ((uint32_t)0x00000001) /*!< 0/1: OSCHF/XTAL is selected */ -#define CLK_HSECR2_EN ((uint32_t)0x00000002) /*!< 1: 24 MHz crystal oscillator is main clock */ - -/******************** Bit definition for CLK_CPUCR register *****************/ -#define CLK_CPUCR_SW2 ((uint32_t)0x00000001) /*!< 0/1: 12MHz/24MHz is selected */ - -/******************************************************************************/ -/* */ -/* Reset Event source (RST) */ -/* */ -/******************************************************************************/ -/******************** Bit definition for RST_SR register ********************/ -#define RST_SR_PWRHV ((uint32_t)0x00000001) /*!< Normal power applied */ -#define RST_SR_PWRLV ((uint32_t)0x00000002) /*!< The application of a Core power supply */ -#define RST_SR_PIN ((uint32_t)0x00000004) /*!< External reset pin signal */ -#define RST_SR_WDG ((uint32_t)0x00000008) /*!< Watchdog expiration */ -#define RST_SR_SWRST ((uint32_t)0x00000010) /*!< Software reset */ -#define RST_SR_WKUP ((uint32_t)0x00000020) /*!< Wake-up from Deep Sleep */ -#define RST_SR_OBFAIL ((uint32_t)0x00000040) /*!< Option byte load failure */ -#define RST_SR_LKUP ((uint32_t)0x00000080) /*!< Core lockup */ - -/******************************************************************************/ -/* */ -/* PWR */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for PWR_DSLEEPCR1 register **************/ -#define PWR_DSLEEPCR1_LVFREEZE ((uint32_t)0x00000002) /*!< Freeze state LV output states */ - -/******************* Bit definition for PWR_DSLEEPCR2 register **************/ -#define PWR_DSLEEPCR2_MODE ((uint32_t)0x00000001) /*!< Selects deep sleep mode 0 when the debugger is attached */ - -/******************* Bit definition for PWR_VREGCR register *****************/ -#define PWR_VREGCR_VREFEN ((uint32_t)0x00008000) /*!< VREF on/off */ - -#define PWR_VREGCR_1V8EN ((uint32_t)0x00000800) /*!< 1V8 direct controle of regulator on/off */ -#define PWR_VREGCR_1V8TRIM ((uint32_t)0x00000380) /*!< 1V2 regulator trim value */ - -#define PWR_VREGCR_1V2EN ((uint32_t)0x00000010) /*!< 1V2 direct controle of regulator on/off */ -#define PWR_VREGCR_1V2TRIM ((uint32_t)0x00000007) /*!< 1V2 regulator trim value */ - -/******************* Bit definition for PWR_WAKECR1 register ****************/ -#define PWR_WAKECR1_CSYSPWRRUPREQ ((uint32_t)0x00000200) /*!< Wake up method on CSYSPWRUPREQ event */ -#define PWR_WAKECR1_CPWRRUPREQ ((uint32_t)0x00000100) /*!< Wake up method on CPWRRUPREQ event */ -#define PWR_WAKECR1_CORE ((uint32_t)0x00000080) /*!< Wake up method on COREWAKE bit */ -#define PWR_WAKECR1_WRAP ((uint32_t)0x00000040) /*!< Wake up method on sleep timer compare wrap/overflow event */ -#define PWR_WAKECR1_COMPB ((uint32_t)0x00000020) /*!< Wake up method on sleep timer compare B event */ -#define PWR_WAKECR1_COMPA ((uint32_t)0x00000010) /*!< Wake up method on sleep timer compare A event */ -#define PWR_WAKECR1_IRQD ((uint32_t)0x00000008) /*!< Wake up method on falling/rising edge of pin PC0*/ -#define PWR_WAKECR1_SC2 ((uint32_t)0x00000004) /*!< Wake up method on falling/rising edge of pin PA2 for SC2 */ -#define PWR_WAKECR1_SC1 ((uint32_t)0x00000002) /*!< Wake up method on falling/rising edge of pin PB2 for SC1*/ -#define PWR_WAKECR1_MONEN ((uint32_t)0x00000001) /*!< Enable the GPIO monitoring to wake from deep sleep */ - -/******************* Bit definition for PWR_WAKECR2 register ****************/ -#define PWR_WAKECR2_COREWAKE ((uint32_t)0x00000020) /*!< Power up controlled by debug port activity */ - -/******************* Bit definition for PWR_WAKESR register ******************/ -#define PWR_WAKESR_CSYSPWRRUPREQ ((uint32_t)0x00000200) /*!< Wake up done using the DAP access to SYS registers */ -#define PWR_WAKESR_CPWRRUPREQ ((uint32_t)0x00000100) /*!< Wake up done using the DAP access to DBG registers */ -#define PWR_WAKESR_CORE ((uint32_t)0x00000080) /*!< Wake up done using debug port activity */ -#define PWR_WAKESR_WRAP ((uint32_t)0x00000040) /*!< Wake up done using sleep timer wrap */ -#define PWR_WAKESR_COMPB ((uint32_t)0x00000020) /*!< Wake up done using sleep timer compare B */ -#define PWR_WAKESR_COMPA ((uint32_t)0x00000010) /*!< Wake up done using sleep timer compare A */ -#define PWR_WAKESR_IRQD ((uint32_t)0x00000008) /*!< Wake up done using external interrupt IRQD */ -#define PWR_WAKESR_SC2 ((uint32_t)0x00000004) /*!< Wake up done using serial controller 2 (PA2) */ -#define PWR_WAKESR_SC1 ((uint32_t)0x00000002) /*!< Wake up done using serial controller 1 (PB2) */ -#define PWR_WAKESR_MON ((uint32_t)0x00000001) /*!< Wake up done using GPIO monitoring */ - -/******************* Bit definition for PWR_CPWRUPREQSR register ************/ -#define PWR_CPWRUPREQSR_REQ ((uint32_t)0x00000001) /*!< Current value of CPWRUPREQ */ - -/******************* Bit definition for PWR_CSYSPWRUPREQSR register *********/ -#define PWR_CSYSPWRUPREQSR_REQ ((uint32_t)0x00000001) /*!< Current value of CSYSPWRUPREQ */ - -/******************* Bit definition for PWR_CSYSPWRUPACKSR register *********/ -#define PWR_CSYSPWRUPACKSR_ACK ((uint32_t)0x00000001) /*!< Current value of CSYSPWRUPACK */ - -/******************* Bit definition for PWR_CSYSPWRUPACKCR register *********/ -#define PWR_CSYSPWRUPACKCR_INHIBIT ((uint32_t)0x00000001) /*!< Inhibit CSYSPWRUPACK */ - -/******************* Bit definition for PWR_WAKEPxR register ****************/ -#define PWR_WAKEPxR_Px0 ((uint32_t)0x00000001) -#define PWR_WAKEPxR_Px1 ((uint32_t)0x00000002) -#define PWR_WAKEPxR_Px2 ((uint32_t)0x00000004) -#define PWR_WAKEPxR_Px3 ((uint32_t)0x00000008) -#define PWR_WAKEPxR_Px4 ((uint32_t)0x00000010) -#define PWR_WAKEPxR_Px5 ((uint32_t)0x00000020) -#define PWR_WAKEPxR_Px6 ((uint32_t)0x00000040) -#define PWR_WAKEPxR_Px7 ((uint32_t)0x00000080) - -/******************* Bit definition for PWR_WAKEFILTR register **************/ -#define PWR_WAKEFILTR_GPIO ((uint32_t)0x00000001) /*!< Enable filter on GPIO wakeup sources enabled by the PWR_WAKEPxR registers */ -#define PWR_WAKEFILTR_SC1 ((uint32_t)0x00000002) /*!< Enable filter on GPIO wakeup source SC1 (PB2) */ -#define PWR_WAKEFILTR_SC2 ((uint32_t)0x00000004) /*!< Enable filter on GPIO wakeup source SC2 (PA2) */ -#define PWR_WAKEFILTR_IRQD ((uint32_t)0x00000008) /*!< Enable filter on GPIO wakeup source EXTI D */ - -/******************************************************************************/ -/* */ -/* Management interrupt (MGMT) */ -/* */ -/******************************************************************************/ -/******************** Bit definition for MGMT_ISR register ******************/ -#define MGMT_ISR_HSECOMPLLIF ((uint32_t)0x00000001) /*!< HSE COMP Low Level flag */ -#define MGMT_ISR_HSECOMPHLIF ((uint32_t)0x00000002) /*!< HSE COMP High Level flag */ - -/******************** Bit definition for MGMT_IER register ******************/ -#define MGMT_IER_HSECOMPLLIE ((uint32_t)0x00000001) /*!< HSE COMP Low Level Interrupt source */ -#define MGMT_IER_HSECOMPHLIE ((uint32_t)0x00000002) /*!< HSE COMP High Level Interrupt source */ - - -/******************************************************************************/ -/* */ -/* General Purpose IOs (GPIO) */ -/* */ -/******************************************************************************/ -/******************* Bit definition for GPIO_CRL register *******************/ -#define GPIO_CRL_CNFMODE0 ((uint32_t)0x0000000F) /*!< CNFMODE0[3:0] bits (GPIO Configuration and Mode Control) */ -#define GPIO_CRL_CNFMODE0_0 ((uint32_t)0x00000001) -#define GPIO_CRL_CNFMODE0_1 ((uint32_t)0x00000002) -#define GPIO_CRL_CNFMODE0_2 ((uint32_t)0x00000004) -#define GPIO_CRL_CNFMODE0_3 ((uint32_t)0x00000008) -#define GPIO_CRL_CNFMODE1 ((uint32_t)0x000000F0) /*!< CNFMODE1[3:0] bits (GPIO Configuration and Mode Control) */ -#define GPIO_CRL_CNFMODE1_0 ((uint32_t)0x00000010) -#define GPIO_CRL_CNFMODE1_1 ((uint32_t)0x00000020) -#define GPIO_CRL_CNFMODE1_2 ((uint32_t)0x00000040) -#define GPIO_CRL_CNFMODE1_3 ((uint32_t)0x00000080) -#define GPIO_CRL_CNFMODE2 ((uint32_t)0x00000F00) /*!< CNFMODE2[3:0] bits (GPIO Configuration and Mode Control) */ -#define GPIO_CRL_CNFMODE2_0 ((uint32_t)0x00000100) -#define GPIO_CRL_CNFMODE2_1 ((uint32_t)0x00000200) -#define GPIO_CRL_CNFMODE2_2 ((uint32_t)0x00000400) -#define GPIO_CRL_CNFMODE2_3 ((uint32_t)0x00000800) -#define GPIO_CRL_CNFMODE3 ((uint32_t)0x0000F000) /*!< CNFMODE3[3:0] bits (GPIO Configuration and Mode Control) */ -#define GPIO_CRL_CNFMODE3_0 ((uint32_t)0x00001000) -#define GPIO_CRL_CNFMODE3_1 ((uint32_t)0x00002000) -#define GPIO_CRL_CNFMODE3_2 ((uint32_t)0x00004000) -#define GPIO_CRL_CNFMODE3_3 ((uint32_t)0x00008000) - -/******************* Bit definition for GPIO_CRH register *******************/ -#define GPIO_CRH_CNFMODE4 ((uint32_t)0x0000000F) /*!< CNFMODE4[3:0] bits (GPIO Configuration and Mode Control) */ -#define GPIO_CRH_CNFMODE4_0 ((uint32_t)0x00000001) -#define GPIO_CRH_CNFMODE4_1 ((uint32_t)0x00000002) -#define GPIO_CRH_CNFMODE4_2 ((uint32_t)0x00000004) -#define GPIO_CRH_CNFMODE4_3 ((uint32_t)0x00000008) -#define GPIO_CRH_CNFMODE5 ((uint32_t)0x000000F0) /*!< CNFMODE5[3:0] bits (GPIO Configuration and Mode Control) */ -#define GPIO_CRH_CNFMODE5_0 ((uint32_t)0x00000010) -#define GPIO_CRH_CNFMODE5_1 ((uint32_t)0x00000020) -#define GPIO_CRH_CNFMODE5_2 ((uint32_t)0x00000040) -#define GPIO_CRH_CNFMODE5_3 ((uint32_t)0x00000080) -#define GPIO_CRH_CNFMODE6 ((uint32_t)0x00000F00) /*!< CNFMODE6[3:0] bits (GPIO Configuration and Mode Control) */ -#define GPIO_CRH_CNFMODE6_0 ((uint32_t)0x00000100) -#define GPIO_CRH_CNFMODE6_1 ((uint32_t)0x00000200) -#define GPIO_CRH_CNFMODE6_2 ((uint32_t)0x00000400) -#define GPIO_CRH_CNFMODE6_3 ((uint32_t)0x00000800) -#define GPIO_CRH_CNFMODE7 ((uint32_t)0x0000F000) /*!< CNFMODE7[3:0] bits (GPIO Configuration and Mode Control) */ -#define GPIO_CRH_CNFMODE7_0 ((uint32_t)0x00001000) -#define GPIO_CRH_CNFMODE7_1 ((uint32_t)0x00002000) -#define GPIO_CRH_CNFMODE7_2 ((uint32_t)0x00004000) -#define GPIO_CRH_CNFMODE7_3 ((uint32_t)0x00008000) - -/******************* Bit definition for GPIO_IDR register ****************/ -#define GPIO_IDR_IDR0 ((uint32_t)0x00000001) -#define GPIO_IDR_IDR1 ((uint32_t)0x00000002) -#define GPIO_IDR_IDR2 ((uint32_t)0x00000004) -#define GPIO_IDR_IDR3 ((uint32_t)0x00000008) -#define GPIO_IDR_IDR4 ((uint32_t)0x00000010) -#define GPIO_IDR_IDR5 ((uint32_t)0x00000020) -#define GPIO_IDR_IDR6 ((uint32_t)0x00000040) -#define GPIO_IDR_IDR7 ((uint32_t)0x00000080) - -/******************* Bit definition for GPIO_ODR register ****************/ -#define GPIO_ODR_ODR0 ((uint32_t)0x00000001) -#define GPIO_ODR_ODR1 ((uint32_t)0x00000002) -#define GPIO_ODR_ODR2 ((uint32_t)0x00000004) -#define GPIO_ODR_ODR3 ((uint32_t)0x00000008) -#define GPIO_ODR_ODR4 ((uint32_t)0x00000010) -#define GPIO_ODR_ODR5 ((uint32_t)0x00000020) -#define GPIO_ODR_ODR6 ((uint32_t)0x00000040) -#define GPIO_ODR_ODR7 ((uint32_t)0x00000080) - -/******************* Bit definition for GPIO_BRR register ****************/ -#define GPIO_BRR_BR0 ((uint32_t)0x00000001) -#define GPIO_BRR_BR1 ((uint32_t)0x00000002) -#define GPIO_BRR_BR2 ((uint32_t)0x00000004) -#define GPIO_BRR_BR3 ((uint32_t)0x00000008) -#define GPIO_BRR_BR4 ((uint32_t)0x00000010) -#define GPIO_BRR_BR5 ((uint32_t)0x00000020) -#define GPIO_BRR_BR6 ((uint32_t)0x00000040) -#define GPIO_BRR_BR7 ((uint32_t)0x00000080) - -/******************* Bit definition for GPIO_BSR register ****************/ -#define GPIO_BSR_BS0 ((uint32_t)0x00000001) -#define GPIO_BSR_BS1 ((uint32_t)0x00000002) -#define GPIO_BSR_BS2 ((uint32_t)0x00000004) -#define GPIO_BSR_BS3 ((uint32_t)0x00000008) -#define GPIO_BSR_BS4 ((uint32_t)0x00000010) -#define GPIO_BSR_BS5 ((uint32_t)0x00000020) -#define GPIO_BSR_BS6 ((uint32_t)0x00000040) -#define GPIO_BSR_BS7 ((uint32_t)0x00000080) - -/******************** Bit definition for GPIO_PCTRACECR register *************/ -#define GPIO_PCTRACECR_SEL ((uint32_t)0x00000001) /*!< selects PC_TRACE source on bb_debug GPIO pins */ - -/******************* Bit definition for GPIO_DBGCR register ****************/ -#define GPIO_DBGCR_PADDRIVE ((uint32_t)0x00000008) /*!< Global Pad drive strength */ -#define GPIO_DBGCR_EXTREGEN ((uint32_t)0x00000010) /*!< Disable REG_EN override of PA7's normal GPIO configuration */ -#define GPIO_DBGCR_DBGDIS ((uint32_t)0x00000020) /*!< Disable debug interface override of normal GPIO configuration */ -/******************* Bit definition for GPIO_DBGSR register ****************/ -#define GPIO_DBGSR_SWEN ((uint32_t)0x00000001) /*!< Status of Serial Wire interface */ -#define GPIO_DBGSR_FORCEDBG ((uint32_t)0x00000002) /*!< Status of debugger interface */ -#define GPIO_DBGSR_BOOTMODE ((uint32_t)0x00000008) /*!< Status of the nBOOTMODE signal sampled at the end of reset */ -/******************************************************************************/ -/* */ -/* EXTI */ -/* */ -/******************************************************************************/ -/******************* Bit definition for EXTI_CR register ********************/ -#define EXTI_CR_GPIO_SEL ((uint32_t)0x0000001F) /*!< GPIO_SEL[4:0]bits (GPIO EXTIx Selection) */ -#define EXTI_CR_GPIO_SEL_0 ((uint32_t)0x00000001) /*!< bit0 */ -#define EXTI_CR_GPIO_SEL_1 ((uint32_t)0x00000002) /*!< bit1 */ -#define EXTI_CR_GPIO_SEL_2 ((uint32_t)0x00000004) /*!< bit2 */ -#define EXTI_CR_GPIO_SEL_3 ((uint32_t)0x00000008) /*!< bit3 */ -#define EXTI_CR_GPIO_SEL_4 ((uint32_t)0x00000010) /*!< bit4 */ - -/******************* Bit definition for EXTI_TSR register ****************/ -#define EXTI_TSR_INTMOD ((uint32_t)0x000000E0) /*!< INTMOD[7:5]bits (EXTIx triggering mode) */ -#define EXTI_TSR_INTMOD_0 ((uint32_t)0x00000020) /*!< bit5 */ -#define EXTI_TSR_INTMOD_1 ((uint32_t)0x00000040) /*!< bit6 */ -#define EXTI_TSR_INTMOD_2 ((uint32_t)0x00000080) /*!< bit7 */ - -#define EXTI_TSR_FILTEN ((uint32_t)0x00000100) /*!< Set this bit to enable digital filtering on EXTIx */ - -/******************* Bit definition for EXTI_PR register ****************/ -#define EXTI_PR_IRQAP ((uint32_t)0x00000001) /*!< EXTIA interrupt pending */ -#define EXTI_PR_IRQBP ((uint32_t)0x00000002) /*!< EXTIB interrupt pending */ -#define EXTI_PR_IRQCP ((uint32_t)0x00000004) /*!< EXTIC interrupt pending */ -#define EXTI_PR_IRQDP ((uint32_t)0x00000008) /*!< EXTID interrupt pending */ - -/******************************************************************************/ -/* */ -/* WDG */ -/* */ -/******************************************************************************/ -/******************* Bit definition for WDG_CR register *********************/ -#define WDG_CR_WDGEN ((uint32_t)0x00000001) /*!< WDG enable */ -#define WDG_CR_WDGDIS ((uint32_t)0x00000002) /*!< WDG disable */ - -/******************* Bit definition for WDG_KR register *********************/ -#define WDG_KR_KEY ((uint32_t)0x0000FFFF) /*!< WDG key value */ - -/******************* Bit definition for WDG_KICKSR register *****************/ -#define WDG_KICKSR_KS ((uint32_t)0x0000FFFF) /*!< WDG kick start value */ - -/******************************************************************************/ -/* */ -/* Sleep Timer */ -/* */ -/******************************************************************************/ -/******************* Bit definition for SLPTMR_CR register ******************/ -#define SLPTMR_CR_CLKSEL ((uint32_t)0x00000001) /*!< clock select */ -#define SLPTMR_CR_PSC ((uint32_t)0x000000F0) /*!< Sleep timer prescaler setting */ -#define SLPTMR_CR_DBGP ((uint32_t)0x00000400) /*!< Debug Pause */ -#define SLPTMR_CR_EN ((uint32_t)0x00000800) /*!< Enable/Disable Sleep Timer */ -#define SLPTMR_CR_REVERSE ((uint32_t)0x00001000) /*!< count forward or backword */ - -/******************* Bit definition for SLPTMR_CNTH register *****************/ -#define SLPTMR_CNTH_CNTH ((uint32_t)0x0000FFFF) /*!< Sleep timer count high register */ - -/******************* Bit definition for SLPTMR_CNTL register *****************/ -#define SLPTMR_CNTL_CNTL ((uint32_t)0x0000FFFF) /*!< Sleep timer count low register */ - -/******************* Bit definition for SLPTMR_CMPAH register ****************/ -#define SLPTMR_CMPAH_CMPAH ((uint32_t)0x0000FFFF) /*!< Sleep timer compare A high register */ - -/******************* Bit definition for SLPTMR_CMPAL register ****************/ -#define SLPTMR_CMPAL_CMPAL ((uint32_t)0x0000FFFF) /*!< Sleep timer compare A low register */ - -/******************* Bit definition for SLPTMR_CMPBH register ****************/ -#define SLPTMR_CMPBH_CMPBH ((uint32_t)0x0000FFFF) /*!< Sleep timer compare B high register */ - -/******************* Bit definition for SLPTMR_CMPBL register ****************/ -#define SLPTMR_CMPBL_CMPBL ((uint32_t)0x0000FFFF) /*!< Sleep timer compare B low register */ - -/******************* Bit definition for SLPTMR_ISR register ******************/ -#define SLPTMR_ISR_WRAP ((uint32_t)0x00000001) /*!< Sleep timer overflow */ -#define SLPTMR_ISR_CMPA ((uint32_t)0x00000002) /*!< Sleep timer compare A */ -#define SLPTMR_ISR_CMPB ((uint32_t)0x00000004) /*!< Sleep timer compare B */ - -/******************* Bit definition for SLPTMR_IFR register ******************/ -#define SLPTMR_IFR_WRAP ((uint32_t)0x00000001) /*!< Sleep timer overflow */ -#define SLPTMR_IFR_CMPA ((uint32_t)0x00000002) /*!< Sleep timer compare A */ -#define SLPTMR_IFR_CMPB ((uint32_t)0x00000004) /*!< Sleep timer compare B */ - -/******************* Bit definition for SLPTMR_IER register ****************/ -#define SLPTMR_IER_WRAP ((uint32_t)0x00000001) /*!< Sleep timer overflow */ -#define SLPTMR_IER_CMPA ((uint32_t)0x00000002) /*!< Sleep timer compare A */ -#define SLPTMR_IER_CMPB ((uint32_t)0x00000004) /*!< Sleep timer compare B */ - -/******************************************************************************/ -/* */ -/* MAC Timer */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for SLPTMR_CNTR register *****************/ -#define MACTMR_CNTR_CNT ((uint32_t)0x000FFFFF) /*!< MAC timer count register */ - -/******************** Bit definition for MACTMR_CR register ******************/ -#define MACTMR_CR_EN ((uint32_t)0x00000001) /*!< MAC timer enable */ -#define MACTMR_CR_RST ((uint32_t)0x00000002) /*!< MAC timer reset */ - -/******************************************************************************/ -/* */ -/* Analog to Digital Converter (ADC) */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for ADC_CR register ********************/ - -#define ADC_CR_ADON ((uint32_t)0x00000001) /*!< ADC enable */ -#define ADC_CR_CLK ((uint32_t)0x00000004) /*!< Clock selection */ - -/*!< MUXN configuration */ -#define ADC_CR_CHSELN ((uint32_t)0x00000078) /*!< Input selection for the N channel */ -#define ADC_CR_CHSELN_0 ((uint32_t)0x00000008) /*!< Bit0 */ -#define ADC_CR_CHSELN_1 ((uint32_t)0x00000010) /*!< Bit1 */ -#define ADC_CR_CHSELN_2 ((uint32_t)0x00000020) /*!< Bit2 */ -#define ADC_CR_CHSELN_3 ((uint32_t)0x00000040) /*!< Bit3 */ - -/*!< MUXP configuration */ -#define ADC_CR_CHSELP ((uint32_t)0x00000780) /*!< Input selection for the P channel */ -#define ADC_CR_CHSELP_0 ((uint32_t)0x00000080) /*!< Bit0 */ -#define ADC_CR_CHSELP_1 ((uint32_t)0x00000100) /*!< Bit1 */ -#define ADC_CR_CHSELP_2 ((uint32_t)0x00000200) /*!< Bit2 */ -#define ADC_CR_CHSELP_3 ((uint32_t)0x00000400) /*!< Bit3 */ - -/*!< HVSELN configuration */ -#define ADC_CR_HVSELN ((uint32_t)0x00000800) /*!< Select voltage range for the N input channel */ - -/*!< HVSELP configuration */ -#define ADC_CR_HVSELP ((uint32_t)0x00001000) /*!< Select voltage range for the P input channel */ - -/*!< PERIOD configuration */ -#define ADC_CR_SMP ((uint32_t)0x0000E000) /*!< ADC sample time in clocks */ -#define ADC_CR_SMP_0 ((uint32_t)0x00002000) /*!< Bit0 */ -#define ADC_CR_SMP_1 ((uint32_t)0x00004000) /*!< Bit1 */ -#define ADC_CR_SMP_2 ((uint32_t)0x00008000) /*!< Bit2 */ - -/******************** Bit definition for ADC_OFFSETR register ***************/ - -#define ADC_OFFSETR_OFFSET ((uint32_t)0x0000FFFF) /*!< 16-bit signed offset added to the basic ADC conversion - result before gain correction is applied.*/ - -/******************** Bit definition for ADC_GAINR register *****************/ - -#define ADC_GAINR_GAIN ((uint32_t)0x0000FFFF) /*!< Gain factor that is multiplied by the offset-corrected - ADC result to produce the output value */ -/******************** Bit definition for ADC_DMACR register *****************/ - -#define ADC_DMACR_LOAD ((uint32_t)0x00000001) /*!< Starts the ADC DMA */ -#define ADC_DMACR_AUTOWRAP ((uint32_t)0x00000002) /*!< Selects DMA mode */ -#define ADC_DMACR_RST ((uint32_t)0x00000010) /*!< Reset the ADC DMA */ - -/******************** Bit definition for ADC_DMASR register *****************/ - -#define ADC_DMASR_ACT ((uint32_t)0x00000001) /*!< DMA active */ -#define ADC_DMASR_OVF ((uint32_t)0x00000002) /*!< DMA overflow */ - -/******************** Bit definition for ADC_DMAMSAR register ***************/ - -#define ADC_DMAMSAR_MSA ((uint32_t)0x00003FFF) /*!< ADC buffer start address */ - -/******************** Bit definition for ADC_DMANDTR register ***************/ - -#define ADC_DMANDTR_NDT ((uint32_t)0x00001FFF) /*!< ADC buffer size */ - -/******************** Bit definition for ADC_DMAMNAR register ***************/ - -#define ADC_DMAMNAR_MNA ((uint32_t)0x00003FFE) /*!< Current DMA address */ - -/******************** Bit definition for ADC_DMACNDTR register **************/ - -#define ADC_DMACNDTR_CNDT ((uint32_t)0x00001FFF) /*!< The number of 16-bit conversion results that have been - written to the buffer */ -/******************** Bit definition for ADC_ISR register *******************/ - -#define ADC_ISR_ADCFLAG ((uint32_t)0x0000001F) /*!< ADC interrupt flag register */ -#define ADC_ISR_ADCFLAG_0 ((uint32_t)0x00000001) /*!< Bit0: reserved and should always be set to 1 */ -#define ADC_ISR_DMABHF ((uint32_t)0x00000002) /*!< DMA buffer half full interrupt pending */ -#define ADC_ISR_DMABF ((uint32_t)0x00000004) /*!< DMA buffer full interrupt pending */ -#define ADC_ISR_SAT ((uint32_t)0x00000008) /*!< Gain correction saturation interrupt pending */ -#define ADC_ISR_DMAOVF ((uint32_t)0x00000010) /*!< DMA buffer overflow interrupt pending */ - -/******************** Bit definition for ADC_IER register *******************/ - -#define ADC_IER_ADCCFG ((uint32_t)0x0000001F) /*!< ADC interrupt configuration register */ -#define ADC_IER_ADCCFG_0 ((uint32_t)0x00000001) /*!< Bit0: reserved and should always be set to 0 */ -#define ADC_IER_DMABHFIE ((uint32_t)0x00000002) /*!< DMA buffer half full interrupt enable */ -#define ADC_IER_DMABFIE ((uint32_t)0x00000004) /*!< DMA buffer full interrupt enable */ -#define ADC_IER_SATIE ((uint32_t)0x00000008) /*!< Gain correction saturation interrupt enable */ -#define ADC_IER_DMAOVFIE ((uint32_t)0x00000010) /*!< DMA buffer overflow interrupt enable */ - -/******************************************************************************/ -/* */ -/* FLASH and Option Bytes Registers */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for FLASH_ACR register ******************/ -#define FLASH_ACR_LATENCY ((uint32_t)0x00000007) /*!< LATENCY[2:0] bits (Latency) */ -#define FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - -#define FLASH_ACR_HLFCYA ((uint32_t)0x00000008) /*!< Flash Half Cycle Access Enable */ -#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */ -#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */ - -/****************** Bit definition for FLASH_KEYR register ******************/ -#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */ - -/***************** Bit definition for FLASH_OPTKEYR register ****************/ -#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */ - -/****************** Bit definition for FLASH_SR register ********************/ -#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */ -#define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */ -#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */ -#define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */ - -/******************* Bit definition for FLASH_CR register *******************/ -#define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */ -#define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */ -#define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */ -#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */ -#define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */ -#define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */ -#define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */ -#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */ -#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */ -#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */ - -/******************* Bit definition for FLASH_AR register *******************/ -#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */ - -/****************** Bit definition for FLASH_OBR register *******************/ -#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */ -#define FLASH_OBR_RDPRT ((uint32_t)0x00000002) /*!< Read protection */ - -/****************** Bit definition for FLASH_WRPR register ******************/ -#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */ - -/****************** Bit definition for FLASH_CLKER register *****************/ -#define FLASH_CLKER_EN ((uint32_t)0x00000001) /*!< Request enabling of FPEC_CLK */ - -/****************** Bit definition for FLASH_CLKSR register ******************/ -#define FLASH_CLKSR_ACK ((uint32_t)0x00000001) /*!< Indicates FPEC_CLK is running and FCLK is 12MHz */ -#define FLASH_CLKSR_BSY ((uint32_t)0x00000002) /*!< Indicates FPEC is Busy */ - -/*----------------------------------------------------------------------------*/ - -/****************** Bit definition for FLASH_RDP register *******************/ -#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */ -#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */ - -/****************** Bit definition for FLASH_Rsvd0 register ******************/ -#define FLASH_Rsvd0_Rsvd0 ((uint32_t)0x00FF0000) /*!< Reserved option byte */ -#define FLASH_Rsvd0_nRsvd0 ((uint32_t)0xFF000000) /*!< Reserved complemented option byte */ - -/****************** Bit definition for FLASH_Rsvd1 register *****************/ -#define FLASH_Rsvd1_Rsvd1 ((uint32_t)0x000000FF) /*!< Reserved option byte */ -#define FLASH_Rsvd1_nRsvd1 ((uint32_t)0x0000FF00) /*!< Reserved complemented option byte */ - -/****************** Bit definition for FLASH_Rsvd2 register *****************/ -#define FLASH_Rsvd2_Rsvd2 ((uint32_t)0x00FF0000) /*!< Reserved option byte */ -#define FLASH_Rsvd2_nRsvd2 ((uint32_t)0xFF000000) /*!< Reserved complemented option byte */ - -/****************** Bit definition for FLASH_WRP0 register ******************/ -#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ -#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRP1 register ******************/ -#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ -#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRP2 register ******************/ -#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ -#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ - -/****************** Bit definition for FLASH_WRP3 register ******************/ -#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ -#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ -/******************************************************************************/ -/* */ -/* Serial Controllers Interface */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for SC_ISR register ********************/ - -#define SC_ISR_PE ((uint32_t)0x00004000) /*!< UART Parity error pending interrupt */ -#define SC_ISR_FE ((uint32_t)0x00002000) /*!< UART Frame error pending interrupt */ -#define SC_ISR_TXULODB ((uint32_t)0x00001000) /*!< DMA transmit buffer B unloaded pending interrupt */ -#define SC_ISR_TXULODA ((uint32_t)0x00000800) /*!< DMA transmit buffer A unloaded pending interrupt */ -#define SC_ISR_RXULODB ((uint32_t)0x00000400) /*!< DMA receive buffer B unloaded pending interrupt */ -#define SC_ISR_RXULODA ((uint32_t)0x00000200) /*!< DMA receive buffer A unloaded pending interrupt */ -#define SC_ISR_NACK ((uint32_t)0x00000100) /*!< I2C not acknowledge received pending interrupt */ -#define SC_ISR_CMDFIN ((uint32_t)0x00000080) /*!< I2C command complete detection pending interrupt */ -#define SC_ISR_BTF ((uint32_t)0x00000040) /*!< I2C byte transmit finished pending interrupt */ -#define SC_ISR_BRF ((uint32_t)0x00000020) /*!< I2C byte receive finished pending interrupt */ -#define SC_ISR_UND ((uint32_t)0x00000010) /*!< Underrun pending interrupt */ -#define SC_ISR_OVR ((uint32_t)0x00000008) /*!< Overrun pending interrupt */ -#define SC_ISR_IDLE ((uint32_t)0x00000004) /*!< IDLE line detection pending interrupt */ -#define SC_ISR_TXE ((uint32_t)0x00000002) /*!< Transmit data register empty pending interrupt */ -#define SC_ISR_RXNE ((uint32_t)0x00000001) /*!< Data register not empty pending interrupt */ - -/******************** Bit definition for SC_IER register ********************/ - -#define SC_IER_PEIE ((uint32_t)0x00004000) /*!< UART Parity error interrupt enable */ -#define SC_IER_FEIE ((uint32_t)0x00002000) /*!< UART Frame error interrupt enable */ -#define SC_IER_TXULODBIE ((uint32_t)0x00001000) /*!< DMA transmit buffer B unloaded interrupt enable */ -#define SC_IER_TXULODAIE ((uint32_t)0x00000800) /*!< DMA transmit buffer A unloaded interrupt enable */ -#define SC_IER_RXULODBIE ((uint32_t)0x00000400) /*!< DMA receive buffer B unloaded interrupt enable */ -#define SC_IER_RXULODAIE ((uint32_t)0x00000200) /*!< DMA receive buffer A unloaded interrupt enable */ -#define SC_IER_NACKIE ((uint32_t)0x00000100) /*!< I2C not acknowledge received interrupt enable */ -#define SC_IER_CMDFINIE ((uint32_t)0x00000080) /*!< I2C command complete detection interrupt enable */ -#define SC_IER_BTFIE ((uint32_t)0x00000040) /*!< I2C byte transmit finished interrupt enable */ -#define SC_IER_BRFIE ((uint32_t)0x00000020) /*!< I2C byte receive finished interrupt enable */ -#define SC_IER_UNDIE ((uint32_t)0x00000010) /*!< Underrun interrupt enable */ -#define SC_IER_OVRIE ((uint32_t)0x00000008) /*!< Overrun interrupt enable */ -#define SC_IER_IDLEIE ((uint32_t)0x00000004) /*!< IDLE line detection interrupt enable */ -#define SC_IER_TXEIE ((uint32_t)0x00000002) /*!< Transmit data register empty interrupt enable */ -#define SC_IER_RXNEIE ((uint32_t)0x00000001) /*!< Data register not empty interrupt enable */ - -/******************** Bit definition for SC_ICR register ********************/ -#define SC_ICR_IDLELEVEL ((uint32_t)0x00000004) /*!< Trigger event configuration to generate the IDLE interrupt */ -#define SC_ICR_TXELEVEL ((uint32_t)0x00000002) /*!< Trigger event configuration to generate the TXE interrupt */ -#define SC_ICR_RXNELEVEL ((uint32_t)0x00000001) /*!< Trigger event configuration to generate the RXNE interrupt */ - -/******************** Bit definition for SC_DMARXBEGADDAR register **********/ -#define SC_DMARXBEGADDAR_ADD ((uint32_t)0x00003FFF) /*!< DMA channelA Rx begin address */ - -/******************** Bit definition for SC_DMARXENDADDAR register **********/ -#define SC_DMARXENDADDAR_ADD ((uint32_t)0x00003FFF) /*!< DMA channelA Rx end address */ - -/******************** Bit definition for SC_DMARXBEGADDBR register **********/ -#define SC_DMARXBEGADDBR_ADD ((uint32_t)0x00003FFF) /*!< DMA channelB Rx begin address */ - -/******************** Bit definition for SC_DMARXENDADDBR register **********/ -#define SC_DMARXENDADDBR_ADD ((uint32_t)0x00003FFF) /*!< DMA channelB Rx end address */ - -/******************** Bit definition for SC_DMATXBEGADDAR register **********/ -#define SC_DMATXBEGADDAR_ADD ((uint32_t)0x00003FFF) /*!< DMA channelA Tx begin address */ - -/******************** Bit definition for SC_DMARXENDADDBR register **********/ -#define SC_DMATXENDADDAR_ADD ((uint32_t)0x00003FFF) /*!< DMA channelA Tx end address */ - -/******************** Bit definition for SC_DMATXBEGADDBR register **********/ -#define SC_DMATXBEGADDBR_ADD ((uint32_t)0x00003FFF) /*!< DMA channelB Tx begin address */ - -/******************** Bit definition for SC_DMARXENDADDBR register **********/ -#define SC_DMATXENDADDBR_ADD ((uint32_t)0x00003FFF) /*!< DMA channelB Tx end address */ - -/******************** Bit definition for SC_DMARXCNTAR register *************/ -#define SC_DMARXCNTAR_CNT ((uint32_t)0x00003FFF) /*!< Receive DMA counter A */ - -/******************** Bit definition for SC_DMARXCNTBR register *************/ -#define SC_DMARXCNTBR_CNT ((uint32_t)0x00003FFF) /*!< Receive DMA counter B */ - -/******************** Bit definition for SC_DMATXCNTR register **************/ -#define SC_DMATXCNTR_CNT ((uint32_t)0x00003FFF) /*!< Transmit DMA counter */ - -/******************** Bit definition for SC_DMASR register ******************/ -#define SC_DMASR_NSSS ((uint32_t)0x00001C00) /*!< NSSS[2:0] Status of the receiver count saved in the SCx_DMARXCNTSAVEDR when nSSEL deasserts */ -#define SC_DMASR_NSSS_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define SC_DMASR_NSSS_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define SC_DMASR_NSSS_2 ((uint32_t)0x00001000) /*!< Bit 2 */ - -#define SC_DMASR_FEB ((uint32_t)0x00000200) /*!< DMA channel B Frame error flag */ -#define SC_DMASR_FEA ((uint32_t)0x00000100) /*!< DMA channel A Frame error flag */ -#define SC_DMASR_PEB ((uint32_t)0x00000080) /*!< DMA channel B Parity error flag */ -#define SC_DMASR_PEA ((uint32_t)0x00000040) /*!< DMA channel A Parity error flag */ -#define SC_DMASR_OVRB ((uint32_t)0x00000020) /*!< DMA channel B overrun error flag */ -#define SC_DMASR_OVRA ((uint32_t)0x00000010) /*!< DMA channel A overrun error flag */ -#define SC_DMASR_TXBACK ((uint32_t)0x00000008) /*!< DMA Transmit channel B ACK flag */ -#define SC_DMASR_TXAACK ((uint32_t)0x00000004) /*!< DMA Transmit channel A ACK flag */ -#define SC_DMASR_RXBACK ((uint32_t)0x00000002) /*!< DMA Receive channel B ACK flag */ -#define SC_DMASR_RXAACK ((uint32_t)0x00000001) /*!< DMA Receive channel B ACK flag */ - -/******************** Bit definition for SC_DMACR register ******************/ -#define SC_DMACR_TXRST ((uint32_t)0x00000020) /*!< DMA transmit Channels reset */ -#define SC_DMACR_RXRST ((uint32_t)0x00000010) /*!< DMA receive Channels reset */ -#define SC_DMACR_TXLODB ((uint32_t)0x00000008) /*!< DMA transmit Channel B load */ -#define SC_DMACR_TXLODA ((uint32_t)0x00000004) /*!< DMA transmit Channel A load */ -#define SC_DMACR_RXLODB ((uint32_t)0x00000002) /*!< DMA receive Channel B load */ -#define SC_DMACR_RXLODA ((uint32_t)0x00000001) /*!< DMA receive Channel A load */ - -/******************** Bit definition for SC_DMARXERRAR register *************/ -#define SC_DMARXERRAR_ADD ((uint32_t)0x00003FFF) /*! DMA receive channel A error offset address */ - -/******************** Bit definition for SC_DMARXERRBR register *************/ -#define SC_DMARXERRBR_ADD ((uint32_t)0x00003FFF) /*! DMA receive channel B error offset address */ - -/******************** Bit definition for SC_DR register *********************/ -#define SC_DR_DR ((uint32_t)0x000000FF) /*!< Data value */ - -/******************** Bit definition for SC_SPISR register ******************/ -#define SC_SPISR_IDLE ((uint32_t)0x00000008) /*!< SPI Idle line detected flag */ -#define SC_SPISR_TXE ((uint32_t)0x00000004) /*!< SPI Transmit data register empty flag */ -#define SC_SPISR_RXNE ((uint32_t)0x00000002) /*!< SPI Data register not empty flag */ -#define SC_SPISR_OVR ((uint32_t)0x00000001) /*!< SPI Overrun flag */ - -/******************** Bit definition for SC_I2CSR register ******************/ -#define SC_I2CSR_CMDFIN ((uint32_t)0x00000008) /*!< I2C Command finished flag */ -#define SC_I2CSR_BRF ((uint32_t)0x00000004) /*!< I2C Byte received finished flag */ -#define SC_I2CSR_BTF ((uint32_t)0x00000002) /*!< I2C Byte transfer finished flag */ -#define SC_I2CSR_NACK ((uint32_t)0x00000001) /*!< I2C Not acknowledge flag */ - -/******************** Bit definition for SC_UARTSR register *****************/ -#define SC_UARTSR_IDLE ((uint32_t)0x00000040) /*!< UART Idle line detected flag */ -#define SC_UARTSR_PE ((uint32_t)0x00000020) /*!< UART Parity error flag */ -#define SC_UARTSR_FE ((uint32_t)0x00000010) /*!< UART Frame error flag */ -#define SC_UARTSR_OVR ((uint32_t)0x00000008) /*!< UART Overrun flag */ -#define SC_UARTSR_TXE ((uint32_t)0x00000004) /*!< UART Transmit data register empty flag */ -#define SC_UARTSR_RXNE ((uint32_t)0x00000002) /*!< UART Data register not empty flag */ -#define SC_UARTSR_CTS ((uint32_t)0x00000001) /*!< UART Clear to send flag */ - -/******************** Bit definition for SC_I2CCR1 register *****************/ -#define SC_I2CCR1_STOP ((uint32_t)0x00000008) /*!< I2C stop command generation */ -#define SC_I2CCR1_START ((uint32_t)0x00000004) /*!< I2C start command generation */ -#define SC_I2CCR1_BTE ((uint32_t)0x00000002) /*!< I2C byte transmit enable */ -#define SC_I2CCR1_BRE ((uint32_t)0x00000001) /*!< I2C byte receive enable */ - -/******************** Bit definition for SC_I2CCR2 register *****************/ -#define SC_I2CCR2_ACK ((uint32_t)0x00000001) /*!< I2C Not Acknowledge generation */ - -/******************** Bit definition for SC_CR register *********************/ -#define SC_CR_MODE ((uint32_t)0x00000003) /*!< MODE[1:0] Serial controller mode selection */ -#define SC_CR_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define SC_CR_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -/******************** Bit definition for SC_SPICR register ******************/ -#define SC_SPICR_RXMODE ((uint32_t)0x00000020) /*!< SPI Receiver-driven mode */ -#define SC_SPICR_MSTR ((uint32_t)0x00000010) /*!< SPI Master mode selection */ -#define SC_SPICR_RPTEN ((uint32_t)0x00000008) /*!< SPI transmit Repeat enable */ -#define SC_SPICR_LSBFIRST ((uint32_t)0x00000004) /*!< SPI frame format */ -#define SC_SPICR_CPHA ((uint32_t)0x00000002) /*!< SPI clock phase */ -#define SC_SPICR_CPOL ((uint32_t)0x00000001) /*!< SPI clock polarity */ - -/******************** Bit definition for SC_UARTCR register *****************/ -#define SC_UARTCR_AHFCE ((uint32_t)0x00000040) /*!< UART automatic hardware flow control enable */ -#define SC_UARTCR_HFCE ((uint32_t)0x00000020) /*!< UART hardware flow control enable */ -#define SC_UARTCR_PS ((uint32_t)0x00000010) /*!< UART parity selection */ -#define SC_UARTCR_PCE ((uint32_t)0x00000008) /*!< UART parity control enable */ -#define SC_UARTCR_STOP ((uint32_t)0x00000004) /*!< UART number of STOP bits */ -#define SC_UARTCR_M ((uint32_t)0x00000002) /*!< UART word length */ -#define SC_UARTCR_nRTS ((uint32_t)0x00000001) /*!< UART request to send */ - -/******************** Bit definition for SC_CRR1 register *******************/ -#define SC_CRR1_LIN ((uint32_t)0x0000000F) /*!< LIN[3:0] The linear component of the clock rate */ -#define SC_CRR1_LIN_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define SC_CRR1_LIN_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define SC_CRR1_LIN_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define SC_CRR1_LIN_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -/******************** Bit definition for SC_CRR2 register *******************/ -#define SC_CRR2_EXP ((uint32_t)0x0000000F) /*!< EXP[3:0] The exponential component of the clock rate */ -#define SC_CRR2_EXP_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define SC_CRR2_EXP_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define SC_CRR2_EXP_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define SC_CRR2_EXP_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - -/******************** Bit definition for SC_UARTBRR1 register ***************/ -#define SC_UARTBRR1_N ((uint32_t)0x0000FFFF) /*!< N[15:0] The integer part of baud rate period */ - -/******************** Bit definition for SC_UARTBRR2 register ***************/ -#define SC_UARTBRR1_F ((uint32_t)0x00000001) /*!< The fractional part of baud rate period */ - -/******************** Bit definition for SC_DMARXCNTSAVEDR register *********/ -#define SC_DMARXCNTSAVEDR_CNT ((uint32_t)0x00003FFF) /*!< DMA received counter in SPI slave mode when nSSEL deasserts */ - -/******************************************************************************/ -/* */ -/* TIM */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for TIM_CR1 register ********************/ -#define TIM_CR1_CEN ((uint32_t)0x00000001) /*!< Counter enable */ -#define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!< Update disable */ -#define TIM_CR1_URS ((uint32_t)0x00000004) /*!< Update request source */ -#define TIM_CR1_OPM ((uint32_t)0x00000008) /*!< One pulse mode */ -#define TIM_CR1_DIR ((uint32_t)0x00000010) /*!< Direction */ - -#define TIM_CR1_CMS ((uint32_t)0x00000060) /*!< CMS[1:0] bits (Center-aligned mode selection) */ -#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!< Bit 1 */ - -#define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!< Auto-reload Buffer enable */ - -#define TIM_CR1_CKD ((uint32_t)0x00000300) /*!< CKD[1:0] bits (clock division) */ -#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -/******************* Bit definition for TIM_CR2 register ********************/ -#define TIM_CR2_MMS ((uint32_t)0x00000070) /*!< MMS[2:0] bits (Master Mode Selection) */ -#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!< Bit 2 */ - -#define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!< TI1 Selection */ - -/******************* Bit definition for TIM_SMCR register *******************/ -#define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!< SMS[2:0] bits (Slave mode selection) */ -#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - -#define TIM_SMCR_TS ((uint32_t)0x00000070) /*!< TS[2:0] bits (Trigger selection) */ -#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!< Bit 2 */ - -#define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!< Master/slave mode */ - -#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!< ETF[3:0] bits (External trigger filter) */ -#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!< Bit 2 */ -#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - -#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!< ETPS[1:0] bits (External trigger prescaler) */ -#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!< Bit 1 */ - -#define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!< External clock enable */ -#define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!< External trigger polarity */ - -/******************* Bit definition for TIM_EGR register ********************/ -#define TIM_EGR_UG ((uint32_t)0x000001) /*!< Update Generation */ -#define TIM_EGR_CC1G ((uint32_t)0x000002) /*!< Capture/Compare 1 Generation */ -#define TIM_EGR_CC2G ((uint32_t)0x000004) /*!< Capture/Compare 2 Generation */ -#define TIM_EGR_CC3G ((uint32_t)0x000008) /*!< Capture/Compare 3 Generation */ -#define TIM_EGR_CC4G ((uint32_t)0x000010) /*!< Capture/Compare 4 Generation */ -#define TIM_EGR_COMG ((uint32_t)0x000020) /*!< Capture/Compare Control Update Generation */ -#define TIM_EGR_TG ((uint32_t)0x000040) /*!< Trigger Generation */ -#define TIM_EGR_BG ((uint32_t)0x000080) /*!< Break Generation */ - -/****************** Bit definition for TIM_CCMR1 register *******************/ -#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */ -#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!< Output Compare 1 Fast enable */ -#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!< Output Compare 1 Buffer enable */ - -#define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!< OC1M[2:0] bits (Output Compare 1 Mode) */ -#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!< Bit 2 */ - -#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */ -#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!< Output Compare 2 Fast enable */ -#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!< Output Compare 2 Buffer enable */ - -#define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!< OC2M[2:0] bits (Output Compare 2 Mode) */ -#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ -#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!< IC1F[3:0] bits (Input Capture 1 Filter) */ -#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ -#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!< Bit 1 */ - -#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!< IC2F[3:0] bits (Input Capture 2 Filter) */ -#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!< Bit 2 */ -#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!< Bit 3 */ - -/****************** Bit definition for TIM_CCMR2 register *******************/ -#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */ -#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!< Output Compare 3 Fast enable */ -#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!< Output Compare 3 Buffer enable */ - -#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!< OC3M[2:0] bits (Output Compare 3 Mode) */ -#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!< Bit 2 */ - -#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */ -#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!< Output Compare 4 Fast enable */ -#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!< Output Compare 4 Buffer enable */ - -#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!< OC4M[2:0] bits (Output Compare 4 Mode) */ -#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ -#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!< IC3F[3:0] bits (Input Capture 3 Filter) */ -#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ -#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!< Bit 1 */ - -#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!< IC4F[3:0] bits (Input Capture 4 Filter) */ -#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!< Bit 2 */ -#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!< Bit 3 */ - -/******************* Bit definition for TIM_CCER register *******************/ -#define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!< Capture/Compare 1 output enable */ -#define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!< Capture/Compare 1 output Polarity */ -#define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!< Capture/Compare 2 output enable */ -#define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!< Capture/Compare 2 output Polarity */ -#define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!< Capture/Compare 3 output enable */ -#define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!< Capture/Compare 3 output Polarity */ -#define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!< Capture/Compare 4 output enable */ -#define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!< Capture/Compare 4 output Polarity */ - -/******************* Bit definition for TIM_CNT register ********************/ -#define TIM_CNT_CNT ((uint32_t)0x0000FFFF) /*!< Counter Value */ - -/******************* Bit definition for TIM_PSC register ********************/ -#define TIM_PSC_PSC ((uint32_t)0x0000000F) /*!< Prescaler Value */ - -/******************* Bit definition for TIM_ARR register ********************/ -#define TIM_ARR_ARR ((uint32_t)0x0000FFFF) /*!< actual auto-reload Value */ - -/******************* Bit definition for TIM_RCR register ********************/ -#define TIM_RCR_REP ((uint32_t)0x0000FF) /*!< Repetition Counter Value */ - -/******************* Bit definition for TIM_CCR1 register *******************/ -#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!< Capture/Compare 1 Value */ - -/******************* Bit definition for TIM_CCR2 register *******************/ -#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!< Capture/Compare 2 Value */ - -/******************* Bit definition for TIM_CCR3 register *******************/ -#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!< Capture/Compare 3 Value */ - -/******************* Bit definition for TIM_CCR4 register *******************/ -#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!< Capture/Compare 4 Value */ - -/******************* Bit definition for TIM1_OR register *******************/ -#define TIM1_OR_EXTRIGSEL ((uint32_t)0x00000003) /*!< Selects the external trigger used in external clock mode 2 */ -#define TIM1_OR_EXTRIGSEL_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define TIM1_OR_EXTRIGSEL_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define TIM1_OR_CLKMSKEN ((uint32_t)0x00000004) /*!< Enables TIM1MSK when TIM1CLK is selected as the external trigger */ -#define TIM1_OR_ORRSVD ((uint32_t)0x00000008) /*!< Reserved: this bit must always be set to 0 */ - -/******************* Bit definition for TIM2_OR register *******************/ -#define TIM2_OR_EXTRIGSEL ((uint32_t)0x00000003) /*!< Selects the external trigger used in external clock mode 2 */ -#define TIM2_OR_EXTRIGSEL_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define TIM2_OR_EXTRIGSEL_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define TIM2_OR_CLKMSKEN ((uint32_t)0x00000004) /*!< Enables TIM2MSK when TIM2CLK is selected as the external trigger */ -#define TIM2_OR_ORRSVD ((uint32_t)0x00000008) /*!< Reserved: this bit must always be set to 0 */ -#define TIM2_OR_REMAPC1 ((uint32_t)0x00000010) /*!< Selects the GPIO used for TIM2_CH1 */ -#define TIM2_OR_REMAPC2 ((uint32_t)0x00000020) /*!< Selects the GPIO used for TIM2_CH2 */ -#define TIM2_OR_REMAPC3 ((uint32_t)0x00000040) /*!< Selects the GPIO used for TIM2_CH3 */ -#define TIM2_OR_REMAPC4 ((uint32_t)0x00000080) /*!< Selects the GPIO used for TIM2_CH4 */ - -/******************* Bit definition for TIM_IER register **************/ -#define TIM_IER_UIE ((uint32_t)0x00000001) /*!< Update interrupt enable */ -#define TIM_IER_CC1IE ((uint32_t)0x00000002) /*!< Capture or compare 1 interrupt enable */ -#define TIM_IER_CC2IE ((uint32_t)0x00000004) /*!< Capture or compare 2 interrupt enable */ -#define TIM_IER_CC3IE ((uint32_t)0x00000008) /*!< Capture or compare 3 interrupt enable */ -#define TIM_IER_CC4IE ((uint32_t)0x00000010) /*!< Capture or compare 4 interrupt enable */ -#define TIM_IER_TIE ((uint32_t)0x00000040) /*!< Trigger interrupt enable */ - -/******************* Bit definition for TIM_ISR register **************/ -#define TIM_ISR_UIP ((uint32_t)0x00000001) /*!< Update interrupt pending */ -#define TIM_ISR_CC1IP ((uint32_t)0x00000002) /*!< Capture or compare 1 interrupt pending */ -#define TIM_ISR_CC2IP ((uint32_t)0x00000004) /*!< Capture or compare 2 interrupt pending */ -#define TIM_ISR_CC3IP ((uint32_t)0x00000008) /*!< Capture or compare 3 interrupt pending */ -#define TIM_ISR_CC4IP ((uint32_t)0x00000010) /*!< Capture or compare 4 interrupt pending */ -#define TIM_ISR_TIP ((uint32_t)0x00000040) /*!< Trigger interrupt */ - -#define TIM_ISR_RSVD ((uint32_t)0x00001E00) /*!< Reserved: May change during normal operation */ -#define TIM_ISR_RSVD_0 ((uint32_t)0x00001E00) /*!< Bit 0 */ -#define TIM_ISR_RSVD_1 ((uint32_t)0x00001E00) /*!< Bit 1 */ -#define TIM_ISR_RSVD_3 ((uint32_t)0x00001E00) /*!< Bit 2 */ - -/******************* Bit definition for TIM_IMR register **************/ -#define TIM_IMR_RSVD ((uint32_t)0x000000EF) /*!< Reserved: May change during normal operation */ -#define TIM_IMR_RSVD_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define TIM_IMR_RSVD_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define TIM_IMR_RSVD_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define TIM_IMR_RSVD_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define TIM_IMR_RSVD_4 ((uint32_t)0x00000010) /*!< Bit 4 */ -#define TIM_IMR_RSVD_5 ((uint32_t)0x00000020) /*!< Bit 5 */ -#define TIM_IMR_RSVD_6 ((uint32_t)0x00000040) /*!< Bit 6 */ - -#define TIM_IMR_CC1IM ((uint32_t)0x00000200) /*!< Capture or compare 1 interrupt missed */ -#define TIM_IMR_CC2IM ((uint32_t)0x00000400) /*!< Capture or compare 2 interrupt missed */ -#define TIM_IMR_CC3IM ((uint32_t)0x00000800) /*!< Capture or compare 3 interrupt missed */ -#define TIM_IMR_CC4IM ((uint32_t)0x00001000) /*!< Capture or compare 4 interrupt missed */ - -/******************************************************************************/ -/* */ -/* SystemTick */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller */ -/* */ -/******************************************************************************/ - -/*Bit definition for NVIC_ISER, NVIC_ICER, NVIC_ISPR, NVIC_ICPR and NVIC_IABR**/ -#define NVIC_IxxR_TIM1 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_IxxR_TIM2 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_IxxR_MGMT ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_IxxR_SLEEPTMR ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_IxxR_SC1 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_IxxR_SC2 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_IxxR_ADC ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_IxxR_IRQA ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_IxxR_IRQB ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_IxxR_IRQC ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_IxxR_IRQD ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_IxxR_DEBUG ((uint32_t)0x00010000) /*!< bit 16 */ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_TIM1 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ISER_TIM2 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ISER_MGMT ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ISER_SLEEPTMR ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ISER_SC1 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ISER_SC2 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ISER_ADC ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ISER_IRQA ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ISER_IRQB ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ISER_IRQC ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ISER_IRQD ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ISER_DEBUG ((uint32_t)0x00010000) /*!< bit 16 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_TIM1 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ICER_TIM2 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ICER_MGMT ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ICER_SLEEPTMR ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ICER_SC1 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ICER_SC2 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ICER_ADC ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ICER_IRQA ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ICER_IRQB ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ICER_IRQC ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ICER_IRQD ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ICER_DEBUG ((uint32_t)0x00010000) /*!< bit 16 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_TIM1 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ISPR_TIM2 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ISPR_MGMT ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ISPR_SLEEPTMR ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ISPR_SC1 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ISPR_SC2 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ISPR_ADC ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ISPR_IRQA ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ISPR_IRQB ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ISPR_IRQC ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ISPR_IRQD ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ISPR_DEBUG ((uint32_t)0x00010000) /*!< bit 16 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_TIM1 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ICPR_TIM2 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ICPR_MGMT ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ICPR_SLEEPTMR ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ICPR_SC1 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ICPR_SC2 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ICPR_ADC ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ICPR_IRQA ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ICPR_IRQB ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ICPR_IRQC ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ICPR_IRQD ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ICPR_DEBUG ((uint32_t)0x00010000) /*!< bit 16 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_TIM1 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_IABR_TIM2 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_IABR_MGMT ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_IABR_SLEEPTMR ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_IABR_SC1 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_IABR_SC2 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_IABR_ADC ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_IABR_IRQA ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_IABR_IRQB ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_IABR_IRQC ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_IABR_IRQD ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_IABR_DEBUG ((uint32_t)0x00010000) /*!< bit 16 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ -#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *****************/ -#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ -#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ -#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ -#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */ -#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */ -#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */ -#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ - -/** - * @} - */ - - /** - * @} - */ -#ifdef USE_STDPERIPH_DRIVER - #include "stm32w108xx_conf.h" -#endif /* USE_STDPERIPH_DRIVER */ - -/** @addtogroup Exported_macro - * @{ - */ - -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32W108XX_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libs/CMSIS/Device/ST/STM32W108xx/Include/system_stm32w108xx.h b/libs/CMSIS/Device/ST/STM32W108xx/Include/system_stm32w108xx.h deleted file mode 100644 index d71d055..0000000 --- a/libs/CMSIS/Device/ST/STM32W108xx/Include/system_stm32w108xx.h +++ /dev/null @@ -1,104 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32w108xx.h - * @author MCD Application Team - * @version V1.0.1 - * @date 30-November-2012 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32w108xx_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32W108XX_H -#define __SYSTEM_STM32W108XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32W108xx_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32W108xx_System_Exported_types - * @{ - */ - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - * @} - */ - -/** @addtogroup STM32W108xx_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32W108xx_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32W108xx_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32W108XX_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libs/CMSIS/Device/ST/STM32W108xx/Release_Notes.html b/libs/CMSIS/Device/ST/STM32W108xx/Release_Notes.html deleted file mode 100644 index dc13597..0000000 --- a/libs/CMSIS/Device/ST/STM32W108xx/Release_Notes.html +++ /dev/null @@ -1,333 +0,0 @@ - - - - - - - -Release Notes for STM32W108xx CMSIS - - - - - - -
-


-

-
- - - - - - -
- - - - - - -
- -

Release -Notes for STM32W108xx CMSIS
-

-

Copyright 2012 STMicroelectronics

-

-
-

 

- - - - - - -
-

Contents

-
    -
  1. STM32W108xx CMSIS update history
    2. -
  2. License
    3. -
-

STM32W108xx CMSIS update history

V1.0.1 /30-November-2012

- -

Development Toolchains

-
  • IAR Embedded Workbench for ARM (EWARM) toolchain V6.40
    -
  • Keil (MDK-ARM) toolchain V4.54
  • TASKING VX-toolset for ARM Cortex-M3 toolchain V4.2r1
-
  • Raisonance IDE RIDE7 -(RIDE) toolchain V7.40
- -
  • Atollic TrueSTUDIO STM32 -(TrueSTUDIO) toolchain V3.2.0

V1.0.0 / -09-October-2012

-

Main -Changes

     First official release -for STM32W108xx devices running on MBxxx -boards
-

Development -Toolchains

-     IAR Embedded -Workbench for ARM (EWARM) toolchain V6.40
    - -

    License

    -

    Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:


    Unless -required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS,
    WITHOUT -WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See -the License for the specific language governing permissions and -limitations under the License.

    -
    -
    -

    For -complete documentation on STMicroelectronics Microcontrollers visit www.st.com

    -
    -

    -
    -
    -

     

    -
    - \ No newline at end of file diff --git a/libs/CMSIS/Device/ST/STM32W108xx/Source/Templates/TrueSTUDIO/startup_stm32w108xx.s b/libs/CMSIS/Device/ST/STM32W108xx/Source/Templates/TrueSTUDIO/startup_stm32w108xx.s deleted file mode 100644 index 79ff9eb..0000000 --- a/libs/CMSIS/Device/ST/STM32W108xx/Source/Templates/TrueSTUDIO/startup_stm32w108xx.s +++ /dev/null @@ -1,266 +0,0 @@ -/** - ****************************************************************************** - * @file : startup_stm32w108xx.s - * Author : MCD Application Team - * Version : V0.0.1RC1 - * Date : 18-April-2012 - * @brief : stm32w108xx Devices vector table for Atollic TrueSTUDIO toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the cortex-m3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2012 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - -.equ BootRAM, 0xF108F85F -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr r0, =_estack - mov sp, r0 /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2] - adds r2, r2, #4 - - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main - -LoopForever: - b LoopForever - - -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M0. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word TIM1_IRQHandler - .word TIM2_IRQHandler - .word MNG_IRQHandler - .word BASEBAND_IRQHandler - .word SLPTIM_IRQHandler - .word SC1_IRQHandler - .word SC2_IRQHandler - .word SECURITY_IRQHandler - .word MAC_TIM_IRQHandler - .word MAC_TR_IRQHandler - .word MAC_RE_IRQHandler - .word ADC_IRQHandler - .word EXTIA_IRQHandler - .word EXTIB_IRQHandler - .word EXTIC_IRQHandler - .word EXTID_IRQHandler - .word DEBUG_IRQHandler - .word BootRAM /* @0x108. This is for boot in RAM mode for - stm32w108xx devices. */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak TIM1_IRQHandler - .thumb_set TIM1_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak MNG_IRQHandler - .thumb_set MNG_IRQHandler,Default_Handler - - .weak BASEBAND_IRQHandler - .thumb_set BASEBAND_IRQHandler,Default_Handler - - .weak SLPTIM_IRQHandler - .thumb_set SLPTIM_IRQHandler,Default_Handler - - .weak SC1_IRQHandler - .thumb_set SC1_IRQHandler,Default_Handler - - .weak SC2_IRQHandler - .thumb_set SC2_IRQHandler,Default_Handler - - .weak SECURITY_IRQHandler - .thumb_set SECURITY_IRQHandler,Default_Handler - - .weak MAC_TIM_IRQHandler - .thumb_set MAC_TIM_IRQHandler,Default_Handler - - .weak MAC_TR_IRQHandler - .thumb_set MAC_TR_IRQHandler,Default_Handler - - .weak MAC_RE_IRQHandler - .thumb_set MAC_RE_IRQHandler,Default_Handler - - .weak ADC_IRQHandler - .thumb_set ADC_IRQHandler,Default_Handler - - .weak EXTIA_IRQHandler - .thumb_set EXTIA_IRQHandler,Default_Handler - - .weak EXTIB_IRQHandler - .thumb_set EXTIB_IRQHandler,Default_Handler - - .weak EXTIC_IRQHandler - .thumb_set EXTIC_IRQHandler,Default_Handler - - .weak EXTID_IRQHandler - .thumb_set EXTID_IRQHandler,Default_Handler - - .weak DEBUG_IRQHandler - .thumb_set DEBUG_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/libs/CMSIS/Device/ST/STM32W108xx/Source/Templates/arm/startup_stm32w108xx.s b/libs/CMSIS/Device/ST/STM32W108xx/Source/Templates/arm/startup_stm32w108xx.s deleted file mode 100644 index 46a62e6..0000000 --- a/libs/CMSIS/Device/ST/STM32W108xx/Source/Templates/arm/startup_stm32w108xx.s +++ /dev/null @@ -1,231 +0,0 @@ -;/**************************************************************************//** -; * @file startup_stm32w108.s -; * @brief CMSIS Core Device Startup File for -; * STM32W108 Device Series -; * @version V1.0.1 -; * @date 30 November 2012 -; * -; * @note -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - - -Stack_Size EQU 0x00001000 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD TIM1_IRQHandler ; 16+ 0 Timer 1 Interrupt - DCD TIM2_IRQHandler ; 16+ 1 Timer 2 Interrupt - DCD MNG_IRQHandler ; 16+ 2 Management Peripheral Interrupt - DCD BASEBAND_IRQHandler ; 16+ 3 Base Band Interrupt - DCD SLPTIM_IRQHandler ; 16+ 4 Sleep Timer Interrupt - DCD SC1_IRQHandler ; 16+ 5 Serial Controller 1 Interrupt - DCD SC2_IRQHandler ; 16+ 6 Serial Controller 2 Interrupt - DCD SECURITY_IRQHandler ; 16+ 7 Security Interrupt - DCD MAC_TIM_IRQHandler ; 16+ 8 MAC Timer Interrupt - DCD MAC_TR_IRQHandler ; 16+ 9 MAC Transmit Interrupt - DCD MAC_RE_IRQHandler ; 16+10 MAC Receive Interrupt - DCD ADC_IRQHandler ; 16+11 ADC Interrupt - DCD EXTIA_IRQHandler ; 16+12 EXTIA Interrupt - DCD EXTIB_IRQHandler ; 16+13 EXTIB Interrupt - DCD EXTIC_IRQHandler ; 16+14 EXTIC Interrupt - DCD EXTID_IRQHandler ; 16+15 EXTID Interrupt - DCD DEBUG_IRQHandler ; 16+16 Debug Interrupt - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT TIM1_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT MNG_IRQHandler [WEAK] - EXPORT BASEBAND_IRQHandler [WEAK] - EXPORT SLPTIM_IRQHandler [WEAK] - EXPORT SC1_IRQHandler [WEAK] - EXPORT SC2_IRQHandler [WEAK] - EXPORT SECURITY_IRQHandler [WEAK] - EXPORT MAC_TIM_IRQHandler [WEAK] - EXPORT MAC_TR_IRQHandler [WEAK] - EXPORT MAC_RE_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT EXTIA_IRQHandler [WEAK] - EXPORT EXTIB_IRQHandler [WEAK] - EXPORT EXTIC_IRQHandler [WEAK] - EXPORT EXTID_IRQHandler [WEAK] - EXPORT DEBUG_IRQHandler [WEAK] - -TIM1_IRQHandler -TIM2_IRQHandler -MNG_IRQHandler -BASEBAND_IRQHandler -SLPTIM_IRQHandler -SC1_IRQHandler -SC2_IRQHandler -SECURITY_IRQHandler -MAC_TIM_IRQHandler -MAC_TR_IRQHandler -MAC_RE_IRQHandler -ADC_IRQHandler -EXTIA_IRQHandler -EXTIB_IRQHandler -EXTIC_IRQHandler -EXTID_IRQHandler -DEBUG_IRQHandler - - B . - - ENDP - - ALIGN - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END diff --git a/libs/CMSIS/Device/ST/STM32W108xx/Source/Templates/gcc_ride7/startup_stm32w108xx.s b/libs/CMSIS/Device/ST/STM32W108xx/Source/Templates/gcc_ride7/startup_stm32w108xx.s deleted file mode 100644 index 7d3bfdc..0000000 --- a/libs/CMSIS/Device/ST/STM32W108xx/Source/Templates/gcc_ride7/startup_stm32w108xx.s +++ /dev/null @@ -1,252 +0,0 @@ -/** - ****************************************************************************** - * @file : startup_stm32w108xx.s - * Author : MCD Application Team - * Version : V0.0.1RC1 - * Date : 18-April-2012 - * @brief : stm32w108xx Devices vector table for Ride toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the cortex-m3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2012 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - -.equ BootRAM, 0xF108F85F -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word TIM1_IRQHandler - .word TIM2_IRQHandler - .word MNG_IRQHandler - .word BASEBAND_IRQHandler - .word SLPTIM_IRQHandler - .word SC1_IRQHandler - .word SC2_IRQHandler - .word SECURITY_IRQHandler - .word MAC_TIM_IRQHandler - .word MAC_TR_IRQHandler - .word MAC_RE_IRQHandler - .word ADC_IRQHandler - .word EXTIA_IRQHandler - .word EXTIB_IRQHandler - .word EXTIC_IRQHandler - .word EXTID_IRQHandler - .word DEBUG_IRQHandler - .word BootRAM /* @0x108. This is for boot in RAM mode for - stm32w108xx devices. */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak TIM1_IRQHandler - .thumb_set TIM1_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak MNG_IRQHandler - .thumb_set MNG_IRQHandler,Default_Handler - - .weak BASEBAND_IRQHandler - .thumb_set BASEBAND_IRQHandler,Default_Handler - - .weak SLPTIM_IRQHandler - .thumb_set SLPTIM_IRQHandler,Default_Handler - - .weak SC1_IRQHandler - .thumb_set SC1_IRQHandler,Default_Handler - - .weak SC2_IRQHandler - .thumb_set SC2_IRQHandler,Default_Handler - - .weak SECURITY_IRQHandler - .thumb_set SECURITY_IRQHandler,Default_Handler - - .weak MAC_TIM_IRQHandler - .thumb_set MAC_TIM_IRQHandler,Default_Handler - - .weak MAC_TR_IRQHandler - .thumb_set MAC_TR_IRQHandler,Default_Handler - - .weak MAC_RE_IRQHandler - .thumb_set MAC_RE_IRQHandler,Default_Handler - - .weak ADC_IRQHandler - .thumb_set ADC_IRQHandler,Default_Handler - - .weak EXTIA_IRQHandler - .thumb_set EXTIA_IRQHandler,Default_Handler - - .weak EXTIB_IRQHandler - .thumb_set EXTIB_IRQHandler,Default_Handler - - .weak EXTIC_IRQHandler - .thumb_set EXTIC_IRQHandler,Default_Handler - - .weak EXTID_IRQHandler - .thumb_set EXTID_IRQHandler,Default_Handler - - .weak DEBUG_IRQHandler - .thumb_set DEBUG_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ \ No newline at end of file diff --git a/libs/CMSIS/Device/ST/STM32W108xx/Source/Templates/iar/startup_stm32w108xx.s b/libs/CMSIS/Device/ST/STM32W108xx/Source/Templates/iar/startup_stm32w108xx.s deleted file mode 100644 index fe6e397..0000000 --- a/libs/CMSIS/Device/ST/STM32W108xx/Source/Templates/iar/startup_stm32w108xx.s +++ /dev/null @@ -1,261 +0,0 @@ -;/******************** (C) COPYRIGHT 2012 STMicroelectronics ******************** -;* File Name : startup_stm32w108xx.s -;* Author : MCD Application Team -;* Version : V1.0.1 -;* Date : 30-November-2012 -;* Description : STM32W108xx RF High Performance Devices vector table for * -;* EWARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == __iar_program_start, -;* - Set the vector table entries with the exceptions ISR -;* address. -;* After Reset the Cortex-M3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;*******************************************************************************/ -; -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD TIM1_IRQHandler ; Timer 1 Interrupt - DCD TIM2_IRQHandler ; Timer 2 Interrupt - DCD MNG_IRQHandler ; Management Peripheral Interrupt - DCD BASEBAND_IRQHandler ; Base Band Interrupt - DCD SLPTIM_IRQHandler ; Sleep Timer Interrupt - DCD SC1_IRQHandler ; Serial Controller 1 Interrupt - DCD SC2_IRQHandler ; Serial Controller 2 Interrupt - DCD SECURITY_IRQHandler ; Security Interrupt - DCD MAC_TIM_IRQHandler ; MAC Timer Interrupt - DCD MAC_TR_IRQHandler ; MAC Transmit Interrupt - DCD MAC_RE_IRQHandler ; MAC Receive Interrupt - DCD ADC_IRQHandler ; ADC Interrupt - DCD EXTIA_IRQHandler ; EXTIA Interrupt - DCD EXTIB_IRQHandler ; EXTIB Interrupt - DCD EXTIC_IRQHandler ; EXTIC Interrupt - DCD EXTID_IRQHandler ; EXTID Interrupt - DCD DEBUG_IRQHandler ; Debug Interrupt -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER(1) -NMI_Handler - B NMI_Handler - - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER(1) -HardFault_Handler - B HardFault_Handler - - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER(1) -MemManage_Handler - B MemManage_Handler - - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER(1) -BusFault_Handler - B BusFault_Handler - - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER(1) -SVC_Handler - B SVC_Handler - - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER(1) -PendSV_Handler - B PendSV_Handler - - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER(1) -SysTick_Handler - B SysTick_Handler - - - PUBWEAK TIM1_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM1_IRQHandler - B TIM1_IRQHandler - - - PUBWEAK TIM2_IRQHandler - SECTION .text:CODE:REORDER(1) -TIM2_IRQHandler - B TIM2_IRQHandler - - - PUBWEAK MNG_IRQHandler - SECTION .text:CODE:REORDER(1) -MNG_IRQHandler - B MNG_IRQHandler - - - PUBWEAK BASEBAND_IRQHandler - SECTION .text:CODE:REORDER(1) -BASEBAND_IRQHandler - B BASEBAND_IRQHandler - - - PUBWEAK SLPTIM_IRQHandler - SECTION .text:CODE:REORDER(1) -SLPTIM_IRQHandler - B SLPTIM_IRQHandler - - - PUBWEAK SC1_IRQHandler - SECTION .text:CODE:REORDER(1) -SC1_IRQHandler - B SC1_IRQHandler - - - PUBWEAK SC2_IRQHandler - SECTION .text:CODE:REORDER(1) -SC2_IRQHandler - B SC2_IRQHandler - - - PUBWEAK SECURITY_IRQHandler - SECTION .text:CODE:REORDER(1) -SECURITY_IRQHandler - B SECURITY_IRQHandler - - - PUBWEAK MAC_TIM_IRQHandler - SECTION .text:CODE:REORDER(1) -MAC_TIM_IRQHandler - B MAC_TIM_IRQHandler - - - PUBWEAK MAC_TR_IRQHandler - SECTION .text:CODE:REORDER(1) -MAC_TR_IRQHandler - B MAC_TR_IRQHandler - - - PUBWEAK MAC_RE_IRQHandler - SECTION .text:CODE:REORDER(1) -MAC_RE_IRQHandler - B MAC_RE_IRQHandler - - - PUBWEAK ADC_IRQHandler - SECTION .text:CODE:REORDER(1) -ADC_IRQHandler - B ADC_IRQHandler - - - PUBWEAK EXTIA_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTIA_IRQHandler - B EXTIA_IRQHandler - - - PUBWEAK EXTIB_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTIB_IRQHandler - B EXTIB_IRQHandler - - - PUBWEAK EXTIC_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTIC_IRQHandler - B EXTIC_IRQHandler - - - PUBWEAK EXTID_IRQHandler - SECTION .text:CODE:REORDER(1) -EXTID_IRQHandler - B EXTID_IRQHandler - - - PUBWEAK DEBUG_IRQHandler - SECTION .text:CODE:REORDER(1) -DEBUG_IRQHandler - B DEBUG_IRQHandler - - END - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libs/CMSIS/Device/ST/STM32W108xx/Source/Templates/system_stm32w108xx.c b/libs/CMSIS/Device/ST/STM32W108xx/Source/Templates/system_stm32w108xx.c deleted file mode 100644 index db84132..0000000 --- a/libs/CMSIS/Device/ST/STM32W108xx/Source/Templates/system_stm32w108xx.c +++ /dev/null @@ -1,237 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32w108xx.c - * @author MCD Application Team - * @version V1.0.1 - * @date 30-November-2012 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. - * - * 1. This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): Setups the system clock (System clock source). - * This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32w108xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * 2. After each device reset the HSI (12 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32w108xx.s" file, to - * configure the system clock before to branch to main program. - * - * 3. If the system clock source selected by user fails to startup, the SystemInit() - * function will do nothing and HSI still used as system clock source. User can - * add some code to deal with this issue inside the SetSysClock() function. - * - * 4. The default value of HSE crystal is set to 24MHz, refer to "HSE_VALUE" define - * in "stm32w108xx.h" file. When HSE is used as system clock source, directly or - * through PLL, and you are using different crystal you have to adapt the HSE - * value to your own configuration. - * - * 5. This file configures the system clock as follows: - *============================================================================= - * System Clock Configuration - *============================================================================= - * System Clock source | HSE - *----------------------------------------------------------------------------- - * SYSCLK | 24000000 Hz - *----------------------------------------------------------------------------- - * HCLK | 24000000 Hz - *----------------------------------------------------------------------------- - * FCLK | 12000000 Hz - *----------------------------------------------------------------------------- - * PCLK = SYSCLK/2 | 12000000 Hz - *----------------------------------------------------------------------------- - * HSE Frequency | 24000000 Hz - *----------------------------------------------------------------------------- - * VDD | 3.3 V - *----------------------------------------------------------------------------- - * Flash Latency | 1 WS - *----------------------------------------------------------------------------- - *============================================================================= - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2012 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32w108xx_system - * @{ - */ - -/** @addtogroup STM32W108xx_System_Private_Includes - * @{ - */ - -#include "stm32w108xx.h" - -/** - * @} - */ - -/** @addtogroup STM32W108xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32W108xx_System_Private_Defines - * @{ - */ -/** - * @} - */ - -/** @addtogroup STM32W108xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32W108xx_System_Private_Variables - * @{ - */ -uint32_t SystemCoreClock = 24000000; -/** - * @} - */ - -/** @addtogroup STM32W108xx_System_Private_FunctionPrototypes - * @{ - */ - -static void SetSysClock(void); - -/** - * @} - */ - -/** @addtogroup STM32W108xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system. - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemCoreClock variable. - * @param None - * @retval None - */ -void SystemInit (void) -{ - /* reset the CLK_HSECR2 register */ - CLK->HSECR2 &= (uint32_t)0x00000000; - - /* reset the CLK_CPUCR register */ - CLK->CPUCR &= (uint32_t)0x00000000; - - /* Configure the System clock frequency */ - SetSysClock(); -} - -/** - * @brief Update SystemCoreClock according to Clock Register Values - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * (*) HSI_VALUE is a constant defined in stm32w108xx.h file (default value - * 12 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32w108xx.h file (default value - * 24 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ - uint32_t tmp = 0; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = (CLK->HSECR2) & (uint32_t)0x0000003; - - if (tmp == 0x0000003) /* HSE used as system clock */ - { - SystemCoreClock = HSE_VALUE; - } - else /* HSI used as system clock */ - { - SystemCoreClock = HSI_VALUE; - } -} - -/** - * @brief Configures the System clock frequency, - * @note This function should be called only once the CLOCK configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ -static void SetSysClock(void) -{ - __IO uint32_t StartUpCounter = 0; - - /* Enable HSE */ - CLK->HSECR2 |= CLK_HSECR2_EN; - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - StartUpCounter++; - } while(StartUpCounter != HSE_STARTUP_TIMEOUT); - - /* Select HSE system clock */ - CLK->HSECR2 |= CLK_HSECR2_SW1; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libs/STM32W108xx_StdPeriph_Driver/Release_Notes.html b/libs/STM32W108xx_StdPeriph_Driver/Release_Notes.html deleted file mode 100644 index f77bb75..0000000 --- a/libs/STM32W108xx_StdPeriph_Driver/Release_Notes.html +++ /dev/null @@ -1,138 +0,0 @@ - - - - - - -Release Notes for STM32W108xx Standard Peripherals Library Drivers - - - - - -
    -


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    Back to Release page
    -

    Release -Notes for STM32W108xx Standard Peripherals Library Drivers -(StdPeriph_Driver)

    -

    Copyright 2012 STMicroelectronics

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    -

    Contents

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      -
    1. STM32W108xx Standard Peripherals Library -Drivers update History
      2. -
    2. License
      3. -
    - - -

    STM32W108xx Standard -Peripherals Library Drivers  update History


    V1.0.1 /30-November-2012

    - -

    Main -Changes 

    -     Add template project for MDK-ARM,TASKING,RIDE and Atollic toolchains.

    Development Toolchains

    -
    • IAR Embedded Workbench for ARM (EWARM) toolchain V6.40
      -
    • Keil (MDK-ARM) toolchain V4.54
    • TASKING VX-toolset for ARM Cortex-M3 toolchain V4.2r1
    -
    • Raisonance IDE RIDE7 -(RIDE) toolchain V7.40
    - -
    • Atollic TrueSTUDIO STM32 -(TrueSTUDIO) toolchain V3.2.0

    V1.0.0 / 09-October-2012

    Main -Changes

    - -      First official release for STM32W108xx devices running on MBxxx boards 

    Development Toolchains

    • IAR Embedded Workbench for ARM (EWARM) toolchain V6.40 -

    License

    Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:


    Unless -required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS,
    WITHOUT -WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See -the License for the specific language governing permissions and -limitations under the License.
    -
    -

    For -complete documentation on STM32(CORTEX M3) 32-Bit Microcontrollers -visit www.st.com/STM32

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    -

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    -
    - \ No newline at end of file diff --git a/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_adc.h b/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_adc.h deleted file mode 100644 index 9e122fe..0000000 --- a/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_adc.h +++ /dev/null @@ -1,366 +0,0 @@ -/** - ****************************************************************************** - * @file stm32w108xx_adc.h - * @author MCD Application Team - * @version V1.0.1 - * @date 30-November-2012 - * @brief This file contains all the functions prototypes for the ADC firmware - * library. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2012 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32W108XX_ADC_H -#define __STM32W108XX_ADC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32w108xx.h" - -/** @addtogroup STM32W108xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup ADC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief ADC Init structures definition - */ -typedef struct -{ - uint32_t ADC_Resolution; /*!< Selects the resolution of the conversion. - This parameter can be a value of ADC_Resolution */ - uint32_t ADC_VoltageP; /*!< Selects the voltage range for the P input channel. - This parameter can be a Low voltage range or High voltage range */ - uint32_t ADC_VoltageN; /*!< Selects the voltage range for the N input channel. - This parameter can be a Low voltage range or High voltage range */ - uint32_t ADC_Input; /*!< Selects the channels. - This parameter must range from 0x0 to 0x5 and from 0x9 to 0xB. - The other values are reserved */ - uint32_t ADC_Clock; /*!< Selects the ADC clock. - This parameter must be 0 or 1 */ - uint32_t ADC_DMAMode; /*!< Selects the ADC DMA mode. - This parameter must be linear or auto wrap */ - int32_t ADC_Offset; /*!< Specifies the offset added to the basic ADC conversion result. - This parameter must be 16 bits signed offset */ - uint32_t ADC_Gain; /*!< Specifies the gain factor that is multiplied by the offset-corrected ADC result - to produce the output value. - This parameter must be 16 bits unsigned gain */ -}ADC_InitTypeDef; - - -/** @defgroup ADC_Exported_Constants - * @{ - */ - -/** @defgroup ADC_resolution - * @{ - */ -#define ADC_Resolution_12b ((uint32_t)0x0000E000) -#define ADC_Resolution_11b ((uint32_t)0x0000C000) -#define ADC_Resolution_10b ((uint32_t)0x0000A000) -#define ADC_Resolution_9b ((uint32_t)0x00008000) -#define ADC_Resolution_8b ((uint32_t)0x00006000) -#define ADC_Resolution_7b ((uint32_t)0x00004000) -#define ADC_Resolution_6b ((uint32_t)0x00002000) -#define ADC_Resolution_5b ((uint32_t)0x00000000) - -#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \ - ((RESOLUTION) == ADC_Resolution_11b) || \ - ((RESOLUTION) == ADC_Resolution_10b) || \ - ((RESOLUTION) == ADC_Resolution_9b) || \ - ((RESOLUTION) == ADC_Resolution_8b) || \ - ((RESOLUTION) == ADC_Resolution_7b) || \ - ((RESOLUTION) == ADC_Resolution_6b) || \ - ((RESOLUTION) == ADC_Resolution_5b)) - -/** - * @} - */ - -/** @defgroup ADC_VoltageP - * @{ - */ -#define ADC_VoltageP_Low ((uint32_t)0x00000000) -#define ADC_VoltageP_High ((uint32_t)0x00001000) - -#define IS_ADC_VoltageP(VOLTAGE_P) (((VOLTAGE_P) == ADC_VoltageP_Low) || \ - ((VOLTAGE_P) == ADC_VoltageP_High)) - -/** - * @} - */ - -/** @defgroup ADC_VoltageN - * @{ - */ -#define ADC_VoltageN_Low ((uint32_t)0x00000000) -#define ADC_VoltageN_High ((uint32_t)0x00000800) - -#define IS_ADC_VoltageN(VOLTAGE_N) (((VOLTAGE_N) == ADC_VoltageN_Low) || \ - ((VOLTAGE_N) == ADC_VoltageN_High)) -/** - * @} - */ - -/** @defgroup ADC_Channels - * @{ - */ -#define ADC_MUX_ADC0 ((uint32_t)0x00000000) /* Channel 0 : ADC0 on PB5 */ -#define ADC_MUX_ADC1 ((uint32_t)0x00000001) /* Channel 1 : ADC0 on PB6 */ -#define ADC_MUX_ADC2 ((uint32_t)0x00000002) /* Channel 2 : ADC0 on PB7 */ -#define ADC_MUX_ADC3 ((uint32_t)0x00000003) /* Channel 3 : ADC0 on PC1 */ -#define ADC_MUX_ADC4 ((uint32_t)0x00000004) /* Channel 4 : ADC0 on PA4 */ -#define ADC_MUX_ADC5 ((uint32_t)0x00000005) /* Channel 5 : ADC0 on PA5 */ -#define ADC_MUX_GND ((uint32_t)0x00000008) /* Channel 8 : VSS (0V) - not for high voltage range */ -#define ADC_MUX_VREF2 ((uint32_t)0x00000009) /* Channel 9 : VREF/2 (0.6V) */ -#define ADC_MUX_VREF ((uint32_t)0x0000000A) /* Channel A : VREF (1.2V)*/ -#define ADC_MUX_VREG2 ((uint32_t)0x0000000B) /* Channel B : Regulator/2 (0.9V) - not for high voltage range */ - -#define ADC_MUXN_BITS ((uint32_t)0x00000004) /* number of bits to shift */ - -/* ADC_SOURCE__ selects as the positive input and as the negative input */ - -#define ADC_SOURCE_ADC0_VREF2 ((ADC_MUX_ADC0 << ADC_MUXN_BITS) | ADC_MUX_VREF2) -#define ADC_SOURCE_ADC0_GND ((ADC_MUX_ADC0 << ADC_MUXN_BITS) | ADC_MUX_GND) - -#define ADC_SOURCE_ADC1_VREF2 ((ADC_MUX_ADC1 << ADC_MUXN_BITS) | ADC_MUX_VREF2) -#define ADC_SOURCE_ADC1_GND ((ADC_MUX_ADC1 << ADC_MUXN_BITS) | ADC_MUX_GND) - -#define ADC_SOURCE_ADC2_VREF2 ((ADC_MUX_ADC2 << ADC_MUXN_BITS) | ADC_MUX_VREF2) -#define ADC_SOURCE_ADC2_GND ((ADC_MUX_ADC2 << ADC_MUXN_BITS) | ADC_MUX_GND) - -#define ADC_SOURCE_ADC3_VREF2 ((ADC_MUX_ADC3 << ADC_MUXN_BITS) | ADC_MUX_VREF2) -#define ADC_SOURCE_ADC3_GND ((ADC_MUX_ADC3 << ADC_MUXN_BITS) | ADC_MUX_GND) - -#define ADC_SOURCE_ADC4_VREF2 ((ADC_MUX_ADC4 << ADC_MUXN_BITS) | ADC_MUX_VREF2) - -#define ADC_SOURCE_ADC5_VREF2 ((ADC_MUX_ADC5 << ADC_MUXN_BITS) | ADC_MUX_VREF2) - -#define ADC_SOURCE_ADC1_ADC0 ((ADC_MUX_ADC1 << ADC_MUXN_BITS) | ADC_MUX_ADC0) -#define ADC_SOURCE_ADC0_ADC1 ((ADC_MUX_ADC1 << ADC_MUXN_BITS) | ADC_MUX_ADC0) - -#define ADC_SOURCE_ADC3_ADC2 ((ADC_MUX_ADC3 << ADC_MUXN_BITS) | ADC_MUX_ADC2) -#define ADC_SOURCE_ADC2_ADC3 ((ADC_MUX_ADC3 << ADC_MUXN_BITS) | ADC_MUX_ADC2) - -#define ADC_SOURCE_ADC5_ADC4 ((ADC_MUX_ADC5 << ADC_MUXN_BITS) | ADC_MUX_ADC4) - -#define ADC_SOURCE_GND_VREF2 ((ADC_MUX_GND << ADC_MUXN_BITS) | ADC_MUX_VREF2) -#define ADC_SOURCE_GND ((ADC_MUX_GND << ADC_MUXN_BITS) | ADC_MUX_GND) - -#define ADC_SOURCE_VREF_VREF2 ((ADC_MUX_VREF << ADC_MUXN_BITS) | ADC_MUX_VREF2) -#define ADC_SOURCE_VREF ((ADC_MUX_VREF << ADC_MUXN_BITS) | ADC_MUX_GND) - -#define ADC_SOURCE_VREF2_VREF2 ((ADC_MUX_VREF2 << ADC_MUXN_BITS) | ADC_MUX_VREF2) -#define ADC_SOURCE_VREF2 ((ADC_MUX_VREF2 << ADC_MUXN_BITS) | ADC_MUX_GND) - -#define ADC_SOURCE_VREG2_VREF2 ((ADC_MUX_VREG2 << ADC_MUXN_BITS) | ADC_MUX_VREF2) -#define ADC_SOURCE_VDD_GND ((ADC_MUX_VREG2 << ADC_MUXN_BITS) | ADC_MUX_GND) - -#define IS_ADC_CHANNEL(CHANNELS) (((CHANNELS) == ADC_SOURCE_ADC0_VREF2) || \ - ((CHANNELS) == ADC_SOURCE_ADC0_GND) || \ - ((CHANNELS) == ADC_SOURCE_ADC1_VREF2) || \ - ((CHANNELS) == ADC_SOURCE_ADC1_GND) || \ - ((CHANNELS) == ADC_SOURCE_ADC2_VREF2) || \ - ((CHANNELS) == ADC_SOURCE_ADC2_GND) || \ - ((CHANNELS) == ADC_SOURCE_ADC3_VREF2) || \ - ((CHANNELS) == ADC_SOURCE_ADC3_GND) || \ - ((CHANNELS) == ADC_SOURCE_ADC4_VREF2) || \ - ((CHANNELS) == ADC_SOURCE_ADC5_VREF2) || \ - ((CHANNELS) == ADC_SOURCE_ADC1_ADC0) || \ - ((CHANNELS) == ADC_SOURCE_ADC0_ADC1) || \ - ((CHANNELS) == ADC_SOURCE_ADC3_ADC2) || \ - ((CHANNELS) == ADC_SOURCE_ADC2_ADC3) || \ - ((CHANNELS) == ADC_SOURCE_ADC5_ADC4) || \ - ((CHANNELS) == ADC_SOURCE_GND_VREF2) || \ - ((CHANNELS) == ADC_SOURCE_GND) || \ - ((CHANNELS) == ADC_SOURCE_VREF_VREF2) || \ - ((CHANNELS) == ADC_SOURCE_VREF) || \ - ((CHANNELS) == ADC_SOURCE_VREF2_VREF2 ) || \ - ((CHANNELS) == ADC_SOURCE_VREF2) || \ - ((CHANNELS) == ADC_SOURCE_VREG2_VREF2) || \ - ((CHANNELS) == ADC_SOURCE_VDD_GND)) - -/** - * @} - */ - -/** @defgroup ADC_DMAMode - * @{ - */ - -#define ADC_DMAMode_Linear ((uint32_t)0x00000000) -#define ADC_DMAMode_AutoWrap ((uint32_t)0x00000002) - -#define IS_ADC_DMA_MODE(MODE) (((MODE) == ADC_DMAMode_Linear) || \ - ((MODE) == ADC_DMAMode_AutoWrap)) -/** - * @} - */ - - -/** @defgroup ADC_clock - * @{ - */ - -#define ADC_Clock_1MHz ADC_CR_CLK -#define ADC_Clock_6MHz 0x00000000 - -#define IS_ADC_CLOCK(CLOCK) (((CLOCK) == ADC_Clock_1MHz) || \ - ((CLOCK) == ADC_Clock_6MHz)) -/** - * @} - */ - -/** @defgroup ADC_offset - * @{ - */ -#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0x0000FFFF) -/** - * @} - */ - - -/** @defgroup ADC_gain - * @{ - */ -#define IS_ADC_GAIN(GAIN) ((GAIN) <= 0x0000FFFF) -/** - * @} - */ - -/** @defgroup ADC_begin - * @{ - */ -#if defined STM32W108CC -#define IS_ADC_BEGIN(BEGIN) (((BEGIN) <= 0x20003FFE) && ((BEGIN) >= 0x20000000) && (((BEGIN) & 0x00000001) == 0 )) -#else -#define IS_ADC_BEGIN(BEGIN) (((BEGIN) <= 0x20001FFE) && ((BEGIN) >= 0x20000000) && (((BEGIN) & 0x00000001) == 0 )) -#endif -/** - * @} - */ - -/** @defgroup ADC_size - * @{ - */ -#if defined STM32W108CC -#define IS_ADC_SIZE(SIZE) ((SIZE) <= 0x00001FFF) -#else -#define IS_ADC_SIZE(SIZE) ((SIZE) <= 0x00000FFF) -#endif -/** - * @} - */ - -/** @defgroup ADC_interrupts_definition - * @{ - */ - -#define ADC_IT_DMABHF ((uint32_t)0x00000002) -#define ADC_IT_DMABF ((uint32_t)0x00000004) -#define ADC_IT_SAT ((uint32_t)0x00000008) -#define ADC_IT_DMAOVF ((uint32_t)0x00000010) - -#define IS_ADC_IT(IT) (((IT) == ADC_IT_DMABHF )|| \ - ((IT) == ADC_IT_DMABF)|| \ - ((IT) == ADC_IT_SAT)|| \ - ((IT) == ADC_IT_DMAOVF)) - -/** - * @} - */ - -/** @defgroup ADC_DMA_flags_definition - * @{ - */ -#define ADC_FLAG_ACT ((uint32_t)0x00000001) -#define ADC_FLAG_OVF ((uint32_t)0x00000002) - -#define IS_ADC_DMA_FLAG(FLAG) (((FLAG) == ADC_FLAG_ACT) || \ - ((FLAG) == ADC_FLAG_OVF)) - -/** - * @} - */ - -/** @defgroup ADC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup ADC_Exported_Functions - * @{ - */ - -/* Function used to set the ADC configuration to the default reset state *****/ -void ADC_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void ADC_Init(ADC_InitTypeDef* ADC_InitStruct); -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); -void ADC_Cmd(FunctionalState NewState); - -/* ADC Channels Configuration functions ***************************************/ -void ADC_ChannelConfig(uint32_t ADC_Channels); - -/* DMA Configuration functions ************************************************/ -void ADC_DMA_ChannelLoadEnable(void); -void ADC_DMA_ChannelReset(void); -void ADC_DMA_Config(uint32_t ADC_DMABeg, uint32_t ADC_DMASize); -uint32_t ADC_DMA_GetNextAddress(void); -uint32_t ADC_DMA_GetCounter(void); - -/* Interrupts and flags management functions **********************************/ -void ADC_ITConfig(uint32_t ADC_IT, FunctionalState NewState); -FlagStatus ADC_DMA_GetFlagStatus(uint32_t ADC_DMA_FLAG); -ITStatus ADC_GetITStatus(uint32_t ADC_IT); -void ADC_ClearITPendingBit(uint32_t ADC_IT); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32W108XX_ADC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_clk.h b/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_clk.h deleted file mode 100644 index 316645c..0000000 --- a/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_clk.h +++ /dev/null @@ -1,146 +0,0 @@ -/** - ****************************************************************************** - * @file stm32w108xx_clk.h - * @author MCD Application Team - * @version V1.0.1 - * @date 30-November-2012 - * @brief This file contains all the functions prototypes for the CLK firmware - * library. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2012 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32W108XX_CLK_H -#define __STM32W108XX_CLK_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32w108xx.h" - -/** @addtogroup STM32W108xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CLK - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup CLK_Exported_Constants - * @{ - */ - -/** @defgroup CLK_HSE_configuration - * @{ - */ -#define CLK_MODE0 ((uint32_t)0x00000000) -#define CLK_MODE1 ((uint32_t)0x00000001) -#define CLK_MODE2 ((uint32_t)0x00000010) -#define CLK_MODE3 ((uint32_t)0x00000011) - -#define IS_CLK_MODE(MODE) (((MODE) == CLK_MODE0) || ((MODE) == CLK_MODE1) || \ - ((MODE) == CLK_MODE2) || ((MODE) == CLK_MODE3)) -/** - * @} - */ - - -/** @defgroup SLPTIM_Clocks - * @{ - */ -#define SLPTIM_CLK_32KH ((uint32_t)CLK_SLEEPCR_LSEEN) -#define SLPTIM_CLK_10KH ((uint32_t)CLK_SLEEPCR_LSI10KEN) -#define IS_SLPTIM_GET_CLK(CLK) (((CLK) == SLPTIM_CLK_32KH) || \ - ((CLK) == SLPTIM_CLK_10KH)) -/** - * @} - */ - - -/** @defgroup Period_Measering_Mode - * @{ - */ -#define MEASURE_CLKRC ((uint32_t)0x00000000) -#define MEASURE_OSCHF ((uint32_t)0x00000001) -#define MEASURE_TUNEFILT ((uint32_t)0x00000002) -#define IS_CLK_MEASURE(MEASURE) (((MEASURE) == MEASURE_CLKRC) || ((MEASURE) == MEASURE_OSCHF) || \ - ((MEASURE) == MEASURE_TUNEFILT)) -/** - * @} - */ - -#define IS_LSI1KCRINT(CALINT) (((CALINT) <= 0x0000001F)) -#define IS_LSI1KCRFRAC(CALFRAC) (((CALFRAC) <= 0x000007FF)) - -#define IS_CLK_TUNE_VALUE(TUNE_VALUE) (((TUNE_VALUE) <= 0x0000000F)) -/** - * @} - */ - -/** @defgroup CLK_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup CLK_Exported_Functions - * @{ - */ -/* Function used to set the CLK configuration to the default reset state *****/ -void CLK_DeInit(void); - -/* Internal/external clocks configuration functions *********/ -void CLK_InternalCalibrateLSI(void); -void CLK_InternalCalibrateHSI(void); -void CLK_Config(uint8_t MODE); -void CLK_HSECmd(FunctionalState NewState); -void CLK_SLPTIMClockConfig(uint32_t CLK_SLPTIM, FunctionalState NewState); -void CLK_1KClockCalibration(uint32_t CALINT, uint32_t CALFRAC); -void CLK_RCTuneConfig(uint32_t TUNE_VALUE); -void CLK_MeasurePeriod(uint32_t CLK_MEASURED); -uint32_t CLK_GetMeasurePeriod(void); -uint32_t CLK_GetClocksFreq(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32W108XX_CLK_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_exti.h b/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_exti.h deleted file mode 100644 index e32b952..0000000 --- a/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_exti.h +++ /dev/null @@ -1,212 +0,0 @@ -/** - ****************************************************************************** - * @file stm32w108xx_exti.h - * @author MCD Application Team - * @version V1.0.1 - * @date 30-November-2012 - * @brief This file contains all the functions prototypes for the EXTI - * firmware library. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2012 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32W108xx_EXTI_H -#define __STM32W108xx_EXTI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32w108xx.h" - -/** @addtogroup STM32W108xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup EXTI - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @brief EXTI Trigger enumeration - * @{ - */ -typedef enum -{ - EXTI_Trigger_Disable = 0x00, - EXTI_Trigger_Rising_Edge = 0x20, - EXTI_Trigger_Falling_Edge = 0x40, - EXTI_Trigger_Rising_Falling_Edge = 0x60, - EXTI_Trigger_High_Level = 0x80, - EXTI_Trigger_Low_Level = 0xA0 -}EXTITrigger_TypeDef; - -#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Disable) || \ - ((TRIGGER) == EXTI_Trigger_Rising_Edge) || \ - ((TRIGGER) == EXTI_Trigger_Falling_Edge) || \ - ((TRIGGER) == EXTI_Trigger_Rising_Falling_Edge) || \ - ((TRIGGER) == EXTI_Trigger_High_Level) || \ - ((TRIGGER) == EXTI_Trigger_Low_Level)) -/** - * @brief EXTI Init Structure definition - */ -typedef struct -{ - uint32_t EXTI_Source; /*!< Specifies the EXTI source to be configured. - This parameter can be GPIO_SourcePxy where x can be (A, B or C) and y can be (0..7). */ - - uint8_t EXTI_IRQn; /*!< Specifies the GPIO IRQ handler for the EXTI source. - This parameter can be EXTI_IRQn where n can be (A, B, C or D). */ - - EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. - This parameter can be a value of @ref EXTITrigger_TypeDef */ - - FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI line. - This parameter can be set either to ENABLE or DISABLE */ - - FunctionalState EXTI_DigitalFilterCmd; /*!< Specifies the new state of the digital filter. - This parameter can be set either to ENABLE or DISABLE */ - -}EXTI_InitTypeDef; - -/** @defgroup EXTI_Exported_Constants - * @{ - */ - -/** @defgroup EXTI_Pin_sources - * @{ - */ -#define EXTI_SourcePA0 ((uint8_t)0x00) -#define EXTI_SourcePA1 ((uint8_t)0x01) -#define EXTI_SourcePA2 ((uint8_t)0x02) -#define EXTI_SourcePA3 ((uint8_t)0x03) -#define EXTI_SourcePA4 ((uint8_t)0x04) -#define EXTI_SourcePA5 ((uint8_t)0x05) -#define EXTI_SourcePA6 ((uint8_t)0x06) -#define EXTI_SourcePA7 ((uint8_t)0x07) - -#define EXTI_SourcePB0 ((uint8_t)0x08) -#define EXTI_SourcePB1 ((uint8_t)0x09) -#define EXTI_SourcePB2 ((uint8_t)0x0A) -#define EXTI_SourcePB3 ((uint8_t)0x0B) -#define EXTI_SourcePB4 ((uint8_t)0x0C) -#define EXTI_SourcePB5 ((uint8_t)0x0D) -#define EXTI_SourcePB6 ((uint8_t)0x0E) -#define EXTI_SourcePB7 ((uint8_t)0x0F) - -#define EXTI_SourcePC0 ((uint8_t)0x10) -#define EXTI_SourcePC1 ((uint8_t)0x11) -#define EXTI_SourcePC2 ((uint8_t)0x12) -#define EXTI_SourcePC3 ((uint8_t)0x13) -#define EXTI_SourcePC4 ((uint8_t)0x14) -#define EXTI_SourcePC5 ((uint8_t)0x15) -#define EXTI_SourcePC6 ((uint8_t)0x16) -#define EXTI_SourcePC7 ((uint8_t)0x17) - -#define IS_EXTI_SOURCE(EXTI_SOURCE) (((EXTI_SOURCE) == EXTI_SourcePA0) || \ - ((EXTI_SOURCE) == EXTI_SourcePA1) || \ - ((EXTI_SOURCE) == EXTI_SourcePA2) || \ - ((EXTI_SOURCE) == EXTI_SourcePA3) || \ - ((EXTI_SOURCE) == EXTI_SourcePA4) || \ - ((EXTI_SOURCE) == EXTI_SourcePA5) || \ - ((EXTI_SOURCE) == EXTI_SourcePA6) || \ - ((EXTI_SOURCE) == EXTI_SourcePA7) || \ - ((EXTI_SOURCE) == EXTI_SourcePB0) || \ - ((EXTI_SOURCE) == EXTI_SourcePB1) || \ - ((EXTI_SOURCE) == EXTI_SourcePB2) || \ - ((EXTI_SOURCE) == EXTI_SourcePB3) || \ - ((EXTI_SOURCE) == EXTI_SourcePB4) || \ - ((EXTI_SOURCE) == EXTI_SourcePB5) || \ - ((EXTI_SOURCE) == EXTI_SourcePB6) || \ - ((EXTI_SOURCE) == EXTI_SourcePB7) || \ - ((EXTI_SOURCE) == EXTI_SourcePC0) || \ - ((EXTI_SOURCE) == EXTI_SourcePC1) || \ - ((EXTI_SOURCE) == EXTI_SourcePC2) || \ - ((EXTI_SOURCE) == EXTI_SourcePC3) || \ - ((EXTI_SOURCE) == EXTI_SourcePC4) || \ - ((EXTI_SOURCE) == EXTI_SourcePC5) || \ - ((EXTI_SOURCE) == EXTI_SourcePC6) || \ - ((EXTI_SOURCE) == EXTI_SourcePC7)) -/** - * @} - */ - -/** @defgroup EXTI_IRQ_Sources - * @{ - */ -#define EXTI_IRQA ((uint32_t)0x00000000) -#define EXTI_IRQB ((uint32_t)0x00000010) -#define EXTI_IRQC ((uint32_t)0x00000020) -#define EXTI_IRQD ((uint32_t)0x00000031) - -#define IS_EXTI_IRQ(EXTI_IRQ) (((EXTI_IRQ) == EXTI_IRQA) || \ - ((EXTI_IRQ) == EXTI_IRQB) || \ - ((EXTI_IRQ) == EXTI_IRQC) || \ - ((EXTI_IRQ) == EXTI_IRQD)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup EXTI_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup EXTI_Exported_Functions - * @{ - */ - -/* EXTI Initialization and Configuration **************************************/ -void EXTI_DeInit(void); -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); -/* Interrupts and flags management functions **********************************/ -ITStatus EXTI_GetITStatus(uint32_t EXTI_IRQn); -void EXTI_ClearITPendingBit(uint32_t EXTI_IRQn); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32W108xx_EXTI_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_flash.h b/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_flash.h deleted file mode 100644 index 9e4a755..0000000 --- a/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_flash.h +++ /dev/null @@ -1,327 +0,0 @@ -/** - ****************************************************************************** - * @file stm32w108xx_flash.h - * @author MCD Application Team - * @version V1.0.1 - * @date 30-November-2012 - * @brief This file contains all the functions prototypes for the FLASH - * firmware library. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2012 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32W108xx_FLASH_H -#define __STM32W108xx_FLASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32w108xx.h" - -/** @addtogroup STM32W108xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup FLASH - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief FLASH Status - */ -typedef enum -{ - FLASH_BUSY = 1, - FLASH_ERROR_PG, - FLASH_ERROR_WRP, - FLASH_COMPLETE, - FLASH_TIMEOUT -}FLASH_Status; - -/** @defgroup FLASH_Exported_Constants - * @{ - */ - -/** @defgroup Flash_Latency - * @{ - */ - -#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */ -#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */ -#define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */ -#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ - ((LATENCY) == FLASH_Latency_1) || \ - ((LATENCY) == FLASH_Latency_2)) -/** - * @} - */ - -/** @defgroup Half_Cycle_Enable_Disable - * @{ - */ - -#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */ -#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */ -#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \ - ((STATE) == FLASH_HalfCycleAccess_Disable)) -/** - * @} - */ - -/** @defgroup Prefetch_Buffer_Enable_Disable - * @{ - */ - -#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */ -#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */ -#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \ - ((STATE) == FLASH_PrefetchBuffer_Disable)) -/** - * @} - */ - -/** @defgroup Option_Bytes_Write_Protection - * @{ - */ -/* Values to be used with STM32W Low and Medium density devices */ -#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32W Low and Medium density devices: Write protection of page 0 to 3 */ -#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32W Low and Medium density devices: Write protection of page 4 to 7 */ -#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32W Low and Medium density devices: Write protection of page 8 to 11 */ -#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32W Low and Medium density devices: Write protection of page 12 to 15 */ -#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32W Low and Medium density devices: Write protection of page 16 to 19 */ -#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32W Low and Medium density devices: Write protection of page 20 to 23 */ -#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32W Low and Medium density devices: Write protection of page 24 to 27 */ -#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32W Low and Medium density devices: Write protection of page 28 to 31 */ -#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32W Medium-density devices: Write protection of page 32 to 35 */ -#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32W Medium-density devices: Write protection of page 36 to 39 */ -#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32W Medium-density devices: Write protection of page 40 to 43 */ -#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32W Medium-density devices: Write protection of page 44 to 47 */ -#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32W Medium-density devices: Write protection of page 48 to 51 */ -#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32W Medium-density devices: Write protection of page 52 to 55 */ -#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32W Medium-density devices: Write protection of page 56 to 59 */ -#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32W Medium-density devices: Write protection of page 60 to 63 */ - -/* Values to be used with STM32W Medium-density devices */ -#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32W Medium-density devices: Write protection of page 64 to 67 */ -#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32W Medium-density devices: Write protection of page 68 to 71 */ -#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32W Medium-density devices: Write protection of page 72 to 75 */ -#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32W Medium-density devices: Write protection of page 76 to 79 */ -#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32W Medium-density devices: Write protection of page 80 to 83 */ -#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32W Medium-density devices: Write protection of page 84 to 87 */ -#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32W Medium-density devices: Write protection of page 88 to 91 */ -#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32W Medium-density devices: Write protection of page 92 to 95 */ -#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32W Medium-density devices: Write protection of page 96 to 99 */ -#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32W Medium-density devices: Write protection of page 100 to 103 */ -#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32W Medium-density devices: Write protection of page 104 to 107 */ -#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32W Medium-density devices: Write protection of page 108 to 111 */ -#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32W Medium-density devices: Write protection of page 112 to 115 */ -#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32W Medium-density devices: Write protection of page 115 to 119 */ -#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32W Medium-density devices: Write protection of page 120 to 123 */ -#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32W Medium-density devices: Write protection of page 124 to 127 */ - - -/* Values to be used with STM32W High-density and Connectivity line devices */ -#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32W High-density and Connectivity line devices: - Write protection of page 0 to 1 */ -#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32W High-density and Connectivity line devices: - Write protection of page 2 to 3 */ -#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32W High-density and Connectivity line devices: - Write protection of page 4 to 5 */ -#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32W High-density and Connectivity line devices: - Write protection of page 6 to 7 */ -#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32W High-density and Connectivity line devices: - Write protection of page 8 to 9 */ -#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32W High-density and Connectivity line devices: - Write protection of page 10 to 11 */ -#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32W High-density and Connectivity line devices: - Write protection of page 12 to 13 */ -#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32W High-density and Connectivity line devices: - Write protection of page 14 to 15 */ -#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32W High-density and Connectivity line devices: - Write protection of page 16 to 17 */ -#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32W High-density and Connectivity line devices: - Write protection of page 18 to 19 */ -#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32W High-density and Connectivity line devices: - Write protection of page 20 to 21 */ -#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32W High-density and Connectivity line devices: - Write protection of page 22 to 23 */ -#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32W High-density and Connectivity line devices: - Write protection of page 24 to 25 */ -#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32W High-density and Connectivity line devices: - Write protection of page 26 to 27 */ -#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32W High-density and Connectivity line devices: - Write protection of page 28 to 29 */ -#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32W High-density and Connectivity line devices: - Write protection of page 30 to 31 */ -#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32W High-density and Connectivity line devices: - Write protection of page 32 to 33 */ -#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32W High-density and Connectivity line devices: - Write protection of page 34 to 35 */ -#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32W High-density and Connectivity line devices: - Write protection of page 36 to 37 */ -#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32W High-density and Connectivity line devices: - Write protection of page 38 to 39 */ -#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32W High-density and Connectivity line devices: - Write protection of page 40 to 41 */ -#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32W High-density and Connectivity line devices: - Write protection of page 42 to 43 */ -#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32W High-density and Connectivity line devices: - Write protection of page 44 to 45 */ -#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32W High-density and Connectivity line devices: - Write protection of page 46 to 47 */ -#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32W High-density and Connectivity line devices: - Write protection of page 48 to 49 */ -#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32W High-density and Connectivity line devices: - Write protection of page 50 to 51 */ -#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32W High-density and Connectivity line devices: - Write protection of page 52 to 53 */ -#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32W High-density and Connectivity line devices: - Write protection of page 54 to 55 */ -#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32W High-density and Connectivity line devices: - Write protection of page 56 to 57 */ -#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32W High-density and Connectivity line devices: - Write protection of page 58 to 59 */ -#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32W High-density and Connectivity line devices: - Write protection of page 60 to 61 */ -#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32W High-density devices: - Write protection of page 62 to 127 */ -#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */ - -#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000)) - -#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x08040000)) - -/** - * @} - */ - - -/** @defgroup FLASH_Interrupts - * @{ - */ - -#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */ -#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */ - -#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) - -/** - * @} - */ - -/** @defgroup FLASH_Flags - * @{ - */ - -#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ -#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ -#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ -#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ -#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ - -#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) -#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ - ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ - ((FLAG) == FLASH_FLAG_OPTERR)) - -/** - * @} - */ - -/** @defgroup FPEC_Flags - * @{ - */ - -#define FPEC_FLAG_ACK ((uint32_t)0x00000001) /*!< FPEC_CLK running flag */ -#define FPEC_FLAG_BSY ((uint32_t)0x00000002) /*!< FPEC Busy flag */ - -#define IS_FPEC_GET_FLAG(FLAG) (((FLAG) == FPEC_FLAG_ACK) || \ - ((FLAG) == FPEC_FLAG_BSY)) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Functions - * @{ - */ - -/*------------ Functions used for all STM32W108xx devices -----*/ -/* FLASH Interface configuration functions ************************************/ -void FLASH_SetLatency(uint32_t FLASH_Latency); -FlagStatus FLASH_GetPrefetchBufferStatus(void); -void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer); -/* FLASH Memory Programming functions *****************************************/ -void FPEC_ClockCmd(FunctionalState NewState); -void FLASH_Unlock(void); -void FLASH_Lock(void); -void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess); -FLASH_Status FLASH_ErasePage(uint32_t Page_Address); -FLASH_Status FLASH_EraseAllPages(void); -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); -/* Option Bytes Programming functions *****************************************/ -FLASH_Status FLASH_EraseOptionBytes(void); -FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); -FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); -uint32_t FLASH_GetWriteProtectionOptionByte(void); -FlagStatus FLASH_GetReadOutProtectionStatus(void); -/* Interrupts and flags management functions **********************************/ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); -void FLASH_ClearFlag(uint32_t FLASH_FLAG); -FLASH_Status FLASH_GetStatus(void); -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32W108xx_FLASH_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_gpio.h b/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_gpio.h deleted file mode 100644 index dfc9273..0000000 --- a/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_gpio.h +++ /dev/null @@ -1,196 +0,0 @@ -/** - ****************************************************************************** - * @file stm32w108xx_gpio.h - * @author MCD Application Team - * @version V1.0.1 - * @date 30-November-2012 - * @brief This file contains all the functions prototypes for the GPIO - * firmware library. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2012 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32W108xx_GPIO_H -#define __STM32W108xx_GPIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32w108xx.h" - -/** @addtogroup STM32W108xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup GPIO - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @brief GPIO Mode enumeration - * @{ - */ -typedef enum -{ - GPIO_Mode_AN = 0x00, /*!< GPIO Analog Mode */ - GPIO_Mode_OUT_PP = 0x01, /*!< GPIO Output Mode PP */ - GPIO_Mode_IN = 0x04, /*!< GPIO Input Mode NOPULL */ - GPIO_Mode_OUT_OD = 0x05, /*!< GPIO Output Mode OD */ - GPIO_Mode_IN_PUD = 0x08, /*!< GPIO Input Mode PuPd */ - GPIO_Mode_AF_PP = 0x09, /*!< GPIO Alternate function Mode PP */ - GPIO_Mode_AF_PP_SPI = 0x0B, /*!< GPIO Alternate function Mode SPI SCLK PP */ - GPIO_Mode_AF_OD = 0x0D /*!< GPIO Alternate function Mode OD */ -}GPIOMode_TypeDef; - -#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AN) || ((MODE) == GPIO_Mode_OUT_PP) || \ - ((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT_OD) || \ - ((MODE) == GPIO_Mode_IN_PUD)|| ((MODE) == GPIO_Mode_AF_PP) || \ - ((MODE) == GPIO_Mode_AF_PP_SPI) ||((MODE) == GPIO_Mode_AF_OD)) - -/** - * @brief GPIO Init structure definition - */ -typedef struct -{ - uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins_define */ - - GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIOMode_TypeDef */ -}GPIO_InitTypeDef; - -/** @defgroup GPIO_Exported_Constants - * @{ - */ - -#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ - ((PERIPH) == GPIOB) || \ - ((PERIPH) == GPIOC)) - -/** @defgroup Bit_SET_and_Bit_RESET_enumeration - * @{ - */ -typedef enum -{ Bit_RESET = 0, - Bit_SET -}BitAction; - -#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) -/** - * @} - */ - -/** @defgroup GPIO_pins_define - * @{ - */ -#define GPIO_Pin_0 ((uint32_t)0x00000001) /*!< Pin 0 selected */ -#define GPIO_Pin_1 ((uint32_t)0x00000002) /*!< Pin 1 selected */ -#define GPIO_Pin_2 ((uint32_t)0x00000004) /*!< Pin 2 selected */ -#define GPIO_Pin_3 ((uint32_t)0x00000008) /*!< Pin 3 selected */ -#define GPIO_Pin_4 ((uint32_t)0x00000010) /*!< Pin 4 selected */ -#define GPIO_Pin_5 ((uint32_t)0x00000020) /*!< Pin 5 selected */ -#define GPIO_Pin_6 ((uint32_t)0x00000040) /*!< Pin 6 selected */ -#define GPIO_Pin_7 ((uint32_t)0x00000080) /*!< Pin 7 selected */ -#define GPIO_Pin_All ((uint32_t)0x000000FF) /*!< All pins selected */ - -#define IS_GPIO_PIN(PIN) ((PIN) != (uint32_t)0x00000000) -#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ - ((PIN) == GPIO_Pin_1) || \ - ((PIN) == GPIO_Pin_2) || \ - ((PIN) == GPIO_Pin_3) || \ - ((PIN) == GPIO_Pin_4) || \ - ((PIN) == GPIO_Pin_5) || \ - ((PIN) == GPIO_Pin_6) || \ - ((PIN) == GPIO_Pin_7)) -/** - * @} - */ - -#define IS_GPIO_GET_DBGFLAG(DBGFLAG) (((DBGFLAG) == GPIO_DBGSR_SWEN) || \ - ((DBGFLAG) == GPIO_DBGSR_FORCEDBG) || \ - ((DBGFLAG) == GPIO_DBGSR_BOOTMODE)) -/** - * @} - */ - -/** @defgroup CLK_PC_Trace_Select - * @{ - */ -#define GPIO_BBDEBUG ((uint32_t)0x00000000) -#define GPIO_PCTRACE ((uint32_t)0x00000001) -#define IS_GPIO_PCTRACE(PCTRACE) (((PCTRACE) == GPIO_BBDEBUG) || \ - ((PCTRACE) == GPIO_PCTRACE)) -/** - * @} - */ -/** @defgroup GPIO_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup GPIO_Exported_Functions - * @{ - */ -/* Function used to set the GPIO configuration to the default reset state ****/ -void GPIO_DeInit(GPIO_TypeDef* GPIOx); -/* Initialization and Configuration functions *********************************/ -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); -/* GPIO Read and Write functions **********************************************/ -uint32_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin); -uint32_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); -uint32_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin); -uint32_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin); -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin); -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin, BitAction BitVal); -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); -/* Debug functions ***********************************************************/ -void GPIO_PCTraceConfig(uint32_t PCTRACE_SEL); -void GPIO_DebugInterfaceCmd(FunctionalState NewState); -void GPIO_ExternalOverrideCmd(FunctionalState NewState); -FlagStatus GPIO_GetDebugFlagStatus(uint16_t GPIO_DBGFLAG); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32W108xx_GPIO_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_misc.h b/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_misc.h deleted file mode 100644 index 8de8732..0000000 --- a/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_misc.h +++ /dev/null @@ -1,204 +0,0 @@ -/** - ****************************************************************************** - * @file stm32w108xx_misc.h - * @author MCD Application Team - * @version V1.0.1 - * @date 30-November-2012 - * @brief This file contains all the functions prototypes for the miscellaneous - * firmware library functions (add-on to CMSIS functions). - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2012 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MISC_H -#define __MISC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32w108xx.h" - -/** @addtogroup STM32W108xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup MISC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief NVIC Init Structure definition - */ -typedef struct -{ - uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. - This parameter can be a value of @ref IRQn_Type - (For the complete STM32 Devices IRQ Channels list, please - refer to stm32w108.h file) */ - - uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel - specified in NVIC_IRQChannel. This parameter can be a value - between 0 and 15 as described in the table @ref NVIC_Priority_Table */ - - uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified - in NVIC_IRQChannel. This parameter can be a value - between 0 and 15 as described in the table @ref NVIC_Priority_Table */ - - FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel - will be enabled or disabled. - This parameter can be set either to ENABLE or DISABLE */ -} NVIC_InitTypeDef; - -/** @defgroup NVIC_Priority_Table - * @{ - */ - -/** - * -@verbatim - The table below gives the allowed values of the pre-emption priority and subpriority according - to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function - ============================================================================================================================ - NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description - ============================================================================================================================ - NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority - | | | 4 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority - | | | 3 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority - | | | 2 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority - | | | 1 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority - | | | 0 bits for subpriority - ============================================================================================================================ -@endverbatim -*/ - -/** - * @} - */ - -/** @defgroup MISC_Exported_Constants - * @{ - */ - -/** @defgroup Vector_Table_Base - * @{ - */ -#define NVIC_VectTab_RAM ((uint32_t)0x20000000) -#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) -#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ - ((VECTTAB) == NVIC_VectTab_FLASH)) -/** - * @} - */ - -/** @defgroup System_Low_Power - * @{ - */ -#define NVIC_LP_SEVONPEND ((uint8_t)0x10) -#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) -#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) -#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ - ((LP) == NVIC_LP_SLEEPDEEP) || \ - ((LP) == NVIC_LP_SLEEPONEXIT)) -/** - * @} - */ - -/** @defgroup Preemption_Priority_Group - * @{ - */ -#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority - 4 bits for subpriority */ -#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority - 3 bits for subpriority */ -#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority - 2 bits for subpriority */ -#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority - 1 bits for subpriority */ -#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority - 0 bits for subpriority */ - -#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ - ((GROUP) == NVIC_PriorityGroup_1) || \ - ((GROUP) == NVIC_PriorityGroup_2) || \ - ((GROUP) == NVIC_PriorityGroup_3) || \ - ((GROUP) == NVIC_PriorityGroup_4)) - -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0005FFFF) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup MISC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup MISC_Exported_Functions - * @{ - */ -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); -void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); -void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __MISC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_pwr.h b/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_pwr.h deleted file mode 100644 index 59a2e06..0000000 --- a/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_pwr.h +++ /dev/null @@ -1,213 +0,0 @@ -/** - ****************************************************************************** - * @file stm32w108xx_pwr.h - * @author MCD Application Team - * @version V1.0.1 - * @date 30-November-2012 - * @brief This file contains all the functions prototypes for the power - * firmware library. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2012 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32W108XX_PWR_H -#define __STM32W108XX_PWR_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32w108xx.h" - -/** @addtogroup STM32W108xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup POWER_MANAGEMENT - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief VREG Init structure definition - */ -typedef struct -{ - uint32_t PWR_VREFCmd; /*!< Specifies the new state of the selected VREF. - This parameter can be set either to ENABLE or DISABLE */ - uint32_t PWR_1V8Cmd; /*!< Specifies the new state of the selected 1V8. - This parameter can be set either to ENABLE or DISABLE */ - uint32_t PWR_1V8TRIM; /*!< Specifies wether the 1V8 regulator trim value.*/ - uint32_t PWR_1V2Cmd; /*!< Specifies the new state of the selected 1V2. - This parameter can be set either to ENABLE or DISABLE */ - uint32_t PWR_1V2TRIM; /*!< Specifies wether the 1V2 regulator trim value.*/ -}PWR_VREG_InitTypeDef; - - -/** @defgroup PWR_Exported_Constants - * @{ - */ - -/** @defgroup LowPower_VoltageCommand_definition - * @{ - */ -#define POWER_ENABLE ((uint32_t)0x00) -#define POWER_DISABLE ((uint32_t)!POWER_ENABLE) - -#define IS_POWER_FUNCTIONAL_STATE(STATE) (((STATE) == POWER_ENABLE) || ((STATE) == POWER_DISABLE)) -/** - * @} - */ - -/** @defgroup LowPower_WakeUpFilter_definition - * @{ - */ -#define PWR_WAKEFILTER_IRQD ((uint32_t)PWR_WAKEFILTR_IRQD) -#define PWR_WAKEFILTER_SC2 ((uint32_t)PWR_WAKEFILTR_SC2) -#define PWR_WAKEFILTER_SC1 ((uint32_t)PWR_WAKEFILTR_SC1) -#define PWR_WAKEFILTER_GPIO ((uint32_t)PWR_WAKEFILTR_GPIO) - -#define IS_PWR_WAKEUPFILTERSOURCE(WAKEUP) (((WAKEUP) == PWR_WAKEFILTER_GPIO) || \ - ((WAKEUP) == PWR_WAKEFILTER_SC1) || \ - ((WAKEUP) == PWR_WAKEFILTER_SC2) || \ - ((WAKEUP) == PWR_WAKEFILTER_IRQD )) -/** - * @} - */ - -/** @defgroup LowPower_WakeUpMethod_definition - * @{ - */ -#define PWR_WAKEUP_CSYSPWRRUPREQ ((uint32_t)PWR_WAKECR1_CSYSPWRRUPREQ) -#define PWR_WAKEUP_CPWRRUPREQ ((uint32_t)PWR_WAKECR1_CPWRRUPREQ) -#define PWR_WAKEUP_CORE ((uint32_t)PWR_WAKECR1_CORE) -#define PWR_WAKEUP_WRAP ((uint32_t)PWR_WAKECR1_WRAP) -#define PWR_WAKEUP_COMPB ((uint32_t)PWR_WAKECR1_COMPB) -#define PWR_WAKEUP_COMPA ((uint32_t)PWR_WAKECR1_COMPA) -#define PWR_WAKEUP_IRQD ((uint32_t)PWR_WAKECR1_IRQD) -#define PWR_WAKEUP_SC2 ((uint32_t)PWR_WAKECR1_SC2) -#define PWR_WAKEUP_SC1 ((uint32_t)PWR_WAKECR1_SC1) -#define PWR_WAKEUP_MON ((uint32_t)PWR_WAKECR1_MONEN) - - -#define IS_PWR_WAKEUPSOURCE(WAKEUP) (((WAKEUP) == PWR_WAKEUP_CSYSPWRRUPREQ) || \ - ((WAKEUP) == PWR_WAKEUP_CPWRRUPREQ) || \ - ((WAKEUP) == PWR_WAKEUP_CORE) || \ - ((WAKEUP) == PWR_WAKEUP_WRAP) || \ - ((WAKEUP) == PWR_WAKEUP_COMPB) || \ - ((WAKEUP) == PWR_WAKEUP_COMPA) || \ - ((WAKEUP) == PWR_WAKEUP_IRQD) || \ - ((WAKEUP) == PWR_WAKEUP_SC2) || \ - ((WAKEUP) == PWR_WAKEUP_SC1) || \ - ((WAKEUP) == PWR_WAKEUP_MON)) -/** - * @} - */ - -/** @defgroup LowPower_flags_definition - * @{ - */ -#define PWR_FLAG_CSYSPWRRUPREQ ((uint32_t)PWR_WAKESR_CSYSPWRRUPREQ) -#define PWR_FLAG_CPWRRUPREQ ((uint32_t)PWR_WAKESR_CPWRRUPREQ) -#define PWR_FLAG_CORE ((uint32_t)PWR_WAKESR_CORE) -#define PWR_FLAG_WRAP ((uint32_t)PWR_WAKESR_WRAP) -#define PWR_FLAG_COMPB ((uint32_t)PWR_WAKESR_COMPB) -#define PWR_FLAG_COMPA ((uint32_t)PWR_WAKESR_COMPA) -#define PWR_FLAG_IRQD ((uint32_t)PWR_WAKESR_IRQD) -#define PWR_FLAG_SC2 ((uint32_t)PWR_WAKESR_SC2) -#define PWR_FLAG_SC1 ((uint32_t)PWR_WAKESR_SC1) -#define PWR_FLAG_MON ((uint32_t)PWR_WAKESR_MON) - -#define PWR_FLAG_CPWRUPREQ ((uint32_t)0x10000001) -#define PWR_FLAG_CSYSPWRUPREQ ((uint32_t)0x20000001) -#define PWR_FLAG_CSYSPWRUPACK ((uint32_t)0x30000001) - -#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_CSYSPWRRUPREQ) || ((FLAG) == PWR_FLAG_CPWRRUPREQ) || \ - ((FLAG) == PWR_FLAG_CORE) || ((FLAG) == PWR_FLAG_WRAP) || \ - ((FLAG) == PWR_FLAG_COMPB) || ((FLAG) == PWR_FLAG_COMPA) || \ - ((FLAG) == PWR_FLAG_IRQD) || ((FLAG) == PWR_FLAG_SC2) || \ - ((FLAG) == PWR_FLAG_SC1) || ((FLAG) == PWR_FLAG_MON) || \ - ((FLAG) == PWR_FLAG_CPWRUPREQ) || ((FLAG) == PWR_FLAG_CSYSPWRUPREQ) || \ - ((FLAG) == PWR_FLAG_CSYSPWRUPACK)) - -#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_CSYSPWRRUPREQ) || ((FLAG) == PWR_FLAG_CPWRRUPREQ) || \ - ((FLAG) == PWR_FLAG_CORE) || ((FLAG) == PWR_FLAG_WRAP) || \ - ((FLAG) == PWR_FLAG_COMPB) || ((FLAG) == PWR_FLAG_COMPA) || \ - ((FLAG) == PWR_FLAG_IRQD) || ((FLAG) == PWR_FLAG_SC2) || \ - ((FLAG) == PWR_FLAG_SC1) || ((FLAG) == PWR_FLAG_MON)) -/** - * @} - */ - -#define IS_TRIM_VALUE(TRIM) ((TRIM) < 8) - -/** - * @} - */ - -/** @defgroup PWR_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup PWR_Exported_Functions - * @{ - */ - -void PWR_DeInit(void); -void PWR_VREGStructInit(PWR_VREG_InitTypeDef* VREG_InitStruct); -void PWR_VREGInit(PWR_VREG_InitTypeDef* VREG_InitStruct); - -void PWR_GPIOWakeUpPinCmd(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin, FunctionalState NewState); -void PWR_WakeUpFilterConfig(uint32_t PWR_WakeUpSource, FunctionalState NewState); -void PWR_WakeUpSourceConfig(uint32_t PWR_WakeUpSource, FunctionalState NewState); -void PWR_DeepSleepMode0Cmd(FunctionalState NewState); -void PWR_FreezestateLVoutput(FunctionalState NewState); -void PWR_CoreWake(void); -void PWR_InhibitCSYSPWRUPACK(void); -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); -void PWR_ClearFlag(uint32_t PWR_FLAG); - -/** - * @} - */ - -#ifdef __cplusplus -} - -#endif - -#endif /*__STM32W108XX_PWR_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_rst.h b/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_rst.h deleted file mode 100644 index 2a3093c..0000000 --- a/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_rst.h +++ /dev/null @@ -1,110 +0,0 @@ -/** - ****************************************************************************** - * @file stm32w108xx_rst.h - * @author MCD Application Team - * @version V1.0.1 - * @date 30-November-2012 - * @brief This file contains all the functions prototypes for the RST firmware - * library. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2012 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32W108XX_RST_H -#define __STM32W108XX_RST_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32w108xx.h" - -/** @addtogroup STM32W108xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RST - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup RST_Exported_Constants - * @{ - */ - -/** @defgroup RESET_Event - * @{ - */ -#define RST_FLAG_PWRHV ((uint32_t)RST_SR_PWRHV) -#define RST_FLAG_PWRLV ((uint32_t)RST_SR_PWRLV) -#define RST_FLAG_PIN ((uint32_t)RST_SR_PIN) -#define RST_FLAG_WDG ((uint32_t)RST_SR_WDG) -#define RST_FLAG_SWRST ((uint32_t)RST_SR_SWRST) -#define RST_FLAG_WKUP ((uint32_t)RST_SR_WKUP) -#define RST_FLAG_OBFAIL ((uint32_t)RST_SR_OBFAIL) -#define RST_FLAG_LKUP ((uint32_t)RST_SR_LKUP) - -#define IS_RST_FLAG(FLAG) (((FLAG) == RST_FLAG_PWRHV) || ((FLAG) == RST_FLAG_PWRLV) || \ - ((FLAG) == RST_FLAG_PIN) || ((FLAG) == RST_FLAG_WDG) || \ - ((FLAG) == RST_FLAG_SWRST) || ((FLAG) == RST_FLAG_WKUP) || \ - ((FLAG) == RST_FLAG_OBFAIL) || ((FLAG) == RST_FLAG_LKUP)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup RST_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup RST_Exported_Functions - * @{ - */ -FlagStatus RST_GetFlagStatus(uint32_t RST_FLAG); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32W108XX_RST_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_sc.h b/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_sc.h deleted file mode 100644 index ab88279..0000000 --- a/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_sc.h +++ /dev/null @@ -1,635 +0,0 @@ -/** - ****************************************************************************** - * @file stm32w108xx_sc.h - * @author MCD Application Team - * @version V1.0.1 - * @date 30-November-2012 - * @brief This file contains all the functions prototypes for the serial controller - * firmware library. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2012 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32W108XX_SC_H -#define __STM32W108XX_SC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32w108xx.h" - -/** @addtogroup STM32W108xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SERIAL_CONTROLLER - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief SPI Init structure definition - */ -typedef struct -{ - - uint16_t SPI_Mode; /*!< Specifies the SPI mode (Master/Slave). - This parameter can be a value of @ref SPI_mode */ - - uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. - This parameter can be a value of @ref SPI_Clock_Polarity */ - - uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. - This parameter can be a value of @ref SPI_Clock_Phase */ - - uint32_t SPI_ClockRate; /*!< This member configures the SPI communication clock rate. - The clock rate is computed using the following formula: - - clock rate = 12MHz/((LIN+1)*(2^EXP)*/ - - uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. - This parameter can be a value of @ref SPI_MSB_LSB_transmission */ -}SPI_InitTypeDef; - -/** - * @brief UART Init Structure definition - */ -typedef struct -{ - uint32_t UART_BaudRate; /*!< This member configures the UART communication baud rate. - The baud rate is computed using the following formula: - - Baudrate = 24MHz/(2*N+F)*/ - - uint32_t UART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref UART_Word_Length */ - - uint32_t UART_StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref UART_Stop_Bits */ - - uint32_t UART_Parity; /*!< Specifies the parity mode. - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits) - This parameter can be a value of @ref UART_Parity */ - - - uint32_t UART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled or disabled. - This parameter can be a value of @ref UART_Hardware_Flow_Control */ -}UART_InitTypeDef; - - -/** - * @brief I2C Init structure definition - */ -typedef struct -{ - uint32_t I2C_ClockRate; /*!< This member configures the I2C communication clock rate. - The clock rate is computed using the following formula: - - clock rate = 12MHz/((LIN+1)*(2^EXP) - This parameter must be set to a value lower than 400kHz */ - -}I2C_InitTypeDef; - -/** - * @brief DMA Init structure definition - */ -typedef struct -{ - uint32_t DMA_BeginAddrA; /*!< Specifies the peripheral begin address A for the selected - DMA_channel */ - uint32_t DMA_EndAddrA; /*!< Specifies the peripheral end address A for the selected - DMA_channel */ - uint32_t DMA_BeginAddrB; /*!< Specifies the peripheral begin address B for the selected - DMA_channel */ - uint32_t DMA_EndAddrB; /*!< Specifies the peripheral end address B for the selected - DMA_channel */ -}SC_DMA_InitTypeDef; - -/** @defgroup SC_Exported_Constants - * @{ - */ - -#define IS_UART_PERIPH(PERIPH) (((PERIPH) == SC1_UART)) - -#define IS_SPI_PERIPH(PERIPH) (((PERIPH) == SC1_SPI) || \ - ((PERIPH) == SC2_SPI)) -#define IS_I2C_PERIPH(PERIPH) (((PERIPH) == SC1_I2C) || \ - ((PERIPH) == SC2_I2C)) -#define IS_DMA_PERIPH(PERIPH) (((PERIPH) == SC1_DMA) || \ - ((PERIPH) == SC2_DMA)) - -#define IS_I2C_SPI_DMA_IT_PERIPH(PERIPH) (((PERIPH) == SC1_IT) || \ - ((PERIPH) == SC2_IT)) - -#define IS_UART_IT_PERIPH(PERIPH) (((PERIPH) == SC1_IT)) - -/** @defgroup SC_mode - * @{ - */ - -#define SC_Mode_Disable ((uint32_t)0x00000000) -#define SC_Mode_UART ((uint32_t)0x00000001) -#define SC_Mode_SPI ((uint32_t)0x00000002) -#define SC_Mode_I2C ((uint32_t)0x00000003) - -#define IS_SC_MODE(MODE) (((MODE) == SC_Mode_Disable) || ((MODE) == SC_Mode_SPI) || \ - ((MODE) == SC_Mode_I2C) || ((MODE) == SC_Mode_UART)) - -/** - * @} - */ - -/** @defgroup Trigger_Event - * @{ - */ - -#define SC_TriggerEvent_Edge ((uint32_t)0x00000000) -#define SC_TriggerEvent_Level ((uint32_t)0x00000001) - -#define IS_SC_TRIGGEREVENT(EVENT) (((EVENT) == SC_TriggerEvent_Edge) || ((EVENT) == SC_TriggerEvent_Level)) - -/** - * @} - */ - -/** @defgroup SC_SPI_Exported_Constants - * @{ - */ - -/** @defgroup SPI_mode - * @{ - */ - -#define SPI_Mode_Slave ((uint32_t)0x00000000) -#define SPI_Mode_Master ((uint32_t)SC_SPICR_MSTR) -#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ - ((MODE) == SPI_Mode_Slave)) -/** - * @} - */ - - -/** @defgroup SPI_Clock_Polarity - * @{ - */ - -#define SPI_CPOL_Low ((uint32_t)0x00000000) -#define SPI_CPOL_High ((uint32_t)SC_SPICR_CPOL) -#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ - ((CPOL) == SPI_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Phase - * @{ - */ - -#define SPI_CPHA_1Edge ((uint32_t)0x00000000) -#define SPI_CPHA_2Edge ((uint32_t)SC_SPICR_CPHA) -#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ - ((CPHA) == SPI_CPHA_2Edge)) -/** - * @} - */ - -/** @defgroup SPI_MSB_LSB_transmission - * @{ - */ - -#define SPI_FirstBit_MSB ((uint32_t)0x00000000) -#define SPI_FirstBit_LSB ((uint32_t)SC_SPICR_LSBFIRST) -#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ - ((BIT) == SPI_FirstBit_LSB)) -/** - * @} - */ - -/** @defgroup SPI_Receiver_driven_Mode - * @{ - */ - -#define SPI_ReceiverMode_TxDataReady ((uint32_t)0x00000000) -#define SPI_ReceiverMode_RxFIFOFree ((uint32_t)SC_SPICR_RXMODE) -#define IS_SPI_RECEIVER_DRIVEN_MODE(MODE) (((MODE) == SPI_ReceiverMode_TxDataReady) || \ - ((MODE) == SPI_ReceiverMode_RxFIFOFree)) -/** - * @} - */ - -/** @defgroup SPI_flags_definition - * @{ - */ - -#define SPI_FLAG_OVR ((uint32_t)SC_SPISR_OVR) -#define SPI_FLAG_TXE ((uint32_t)SC_SPISR_TXE) -#define SPI_FLAG_RXNE ((uint32_t)SC_SPISR_RXNE) -#define SPI_FLAG_IDLE ((uint32_t)SC_SPISR_IDLE) -#define IS_SPI_GET_FLAG(FLAG) (((FLAG) == SPI_FLAG_IDLE) || ((FLAG) == SPI_FLAG_RXNE) || \ - ((FLAG) == SPI_FLAG_TXE) || ((FLAG) == SPI_FLAG_OVR)) -/** - * @} - */ - -/** @defgroup SPI_interrupts_definition - * @{ - */ -#define SPI_IT_UND ((uint32_t)SC_ISR_UND) -#define SPI_IT_OVR ((uint32_t)SC_ISR_OVR) -#define SPI_IT_IDLE ((uint32_t)SC_ISR_IDLE) -#define SPI_IT_TXE ((uint32_t)SC_ISR_TXE) -#define SPI_IT_RXNE ((uint32_t)SC_ISR_RXNE) -#define IS_SPI_IT(IT) (((IT) == SPI_IT_UND) || ((IT) == SPI_IT_OVR) || \ - ((IT) == SPI_IT_IDLE) || ((IT) == SPI_IT_TXE) || \ - ((IT) == SPI_IT_RXNE)) -#define IS_SPI_TRIGGEREVENT_IT(IT) (((IT) == SPI_IT_IDLE) || ((IT) == SPI_IT_TXE) || \ - ((IT) == SPI_IT_RXNE)) -/** - * @} - */ - - -#define IS_SPI_CLOCK_RATE(RATE) (((RATE) > 0) && ((RATE) <= 6000000)) - -/** - * @} - */ - -/** @defgroup SC_UART_Exported_Constants - * @{ - */ - -/** @defgroup UART_Word_Length - * @{ - */ - -#define UART_WordLength_7b ((uint32_t)0x00000000) -#define UART_WordLength_8b ((uint32_t)SC_UARTCR_M) -#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WordLength_7b) || \ - ((LENGTH) == UART_WordLength_8b)) -/** - * @} - */ - -/** @defgroup UART_Stop_Bits - * @{ - */ - -#define UART_StopBits_1 ((uint32_t)0x00000000) -#define UART_StopBits_2 ((uint32_t)SC_UARTCR_STOP) - -#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_StopBits_1) || \ - ((STOPBITS) == UART_StopBits_2)) -/** - * @} - */ - -/** @defgroup UART_Parity - * @{ - */ - -#define UART_Parity_No ((uint32_t)0x00000000) -#define UART_Parity_Even ((uint32_t)SC_UARTCR_PCE) -#define UART_Parity_Odd ((uint32_t)SC_UARTCR_PCE | SC_UARTCR_PS) -#define IS_UART_PARITY(PARITY) (((PARITY) == UART_Parity_No) || \ - ((PARITY) == UART_Parity_Even) || \ - ((PARITY) == UART_Parity_Odd)) -/** - * @} - */ - -/** @defgroup UART_Hardware_Flow_Control - * @{ - */ - -#define UART_HardwareFlowControl_Disable ((uint32_t)0x00000000) -#define UART_HardwareFlowControl_Enable ((uint32_t)0x00000020) -#define UART_HardwareFlowControl_Automatic ((uint32_t)0x00000060) -#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == UART_HardwareFlowControl_Disable) || \ - ((CONTROL) == UART_HardwareFlowControl_Enable) || \ - ((CONTROL) == UART_HardwareFlowControl_Automatic)) -/** - * @} - */ - - - -/** @defgroup UART_flags_definition - * @{ - */ -#define UART_FLAG_CTS ((uint32_t)SC_UARTSR_CTS) -#define UART_FLAG_RXNE ((uint32_t)SC_UARTSR_RXNE) -#define UART_FLAG_TXE ((uint32_t)SC_UARTSR_TXE) -#define UART_FLAG_OVR ((uint32_t)SC_UARTSR_OVR) -#define UART_FLAG_FE ((uint32_t)SC_UARTSR_FE) -#define UART_FLAG_PE ((uint32_t)SC_UARTSR_PE) -#define UART_FLAG_IDLE ((uint32_t)SC_UARTSR_IDLE) - -#define IS_UART_GET_FLAG(FLAG) (((FLAG) == UART_FLAG_CTS) || ((FLAG) == UART_FLAG_RXNE) || \ - ((FLAG) == UART_FLAG_TXE) || ((FLAG) == UART_FLAG_OVR) || \ - ((FLAG) == UART_FLAG_FE) || ((FLAG) == UART_FLAG_PE)|| \ - ((FLAG) == UART_FLAG_IDLE)) -/** - * @} - */ - -/** @defgroup UART_interrupts_definition - * @{ - */ - -#define UART_IT_PE ((uint32_t)SC_ISR_PE) -#define UART_IT_FE ((uint32_t)SC_ISR_FE) -#define UART_IT_UND ((uint32_t)SC_ISR_UND) -#define UART_IT_OVR ((uint32_t)SC_ISR_OVR) -#define UART_IT_IDLE ((uint32_t)SC_ISR_IDLE) -#define UART_IT_TXE ((uint32_t)SC_ISR_TXE) -#define UART_IT_RXNE ((uint32_t)SC_ISR_RXNE) - -#define IS_UART_IT(IT) (((IT) == UART_IT_PE) || ((IT) == UART_IT_FE) || \ - ((IT) == UART_IT_UND) || ((IT) == UART_IT_OVR) || \ - ((IT) == UART_IT_IDLE) || ((IT) == UART_IT_TXE) || \ - ((IT) == UART_IT_RXNE)) -#define IS_UART_TRIGGEREVENT_IT(IT) (((IT) == UART_IT_IDLE) || ((IT) == UART_IT_TXE) || \ - ((IT) == UART_IT_RXNE)) -/** - * @} - */ - -#define IS_UART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) <= 1500000)) - -/** - * @} - */ - - -/** @defgroup SC_I2C_Exported_Constants - * @{ - */ - -/** @defgroup I2C_transfer_direction - * @{ - */ - -#define I2C_Direction_Transmitter ((uint8_t)0x00) -#define I2C_Direction_Receiver ((uint8_t)0x01) -#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ - ((DIRECTION) == I2C_Direction_Receiver)) -/** - * @} - */ - -/** @defgroup I2C_flags_definition - * @{ - */ -#define I2C_FLAG_NACK ((uint32_t)SC_I2CSR_NACK) -#define I2C_FLAG_BTF ((uint32_t)SC_I2CSR_BTF) -#define I2C_FLAG_BRF ((uint32_t)SC_I2CSR_BRF) -#define I2C_FLAG_CMDFIN ((uint32_t)SC_I2CSR_CMDFIN) - -#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == SC_I2CSR_NACK) || ((FLAG) == SC_I2CSR_BTF) || \ - ((FLAG) == SC_I2CSR_BRF) || ((FLAG) == SC_I2CSR_CMDFIN)) -/** - * @} - */ - -/** @defgroup I2C_interrupts_definition - * @{ - */ -#define I2C_IT_NACK ((uint32_t)SC_ISR_NACK) -#define I2C_IT_CMDFIN ((uint32_t)SC_ISR_CMDFIN) -#define I2C_IT_BTF ((uint32_t)SC_ISR_BTF) -#define I2C_IT_BRF ((uint32_t)SC_ISR_BRF) - -#define IS_I2C_IT(IT) (((IT) == I2C_IT_NACK) || ((IT) == I2C_IT_CMDFIN) || \ - ((IT) == I2C_IT_BTF) || ((IT) == I2C_IT_BRF)) -/** - * @} - */ - -#define IS_I2C_CLOCK_RATE(RATE) (((RATE) > 0) && ((RATE) <= 400000)) - -/** - * @} - */ - -/** @defgroup SC_DMA_Exported_Constants - * @{ - */ - -/** @defgroup DMA_Channel_Load - * @{ - */ - -#define DMA_ChannelLoad_BTx ((uint32_t)SC_DMACR_TXLODB) -#define DMA_ChannelLoad_ATx ((uint32_t)SC_DMACR_TXLODA) -#define DMA_ChannelLoad_BRx ((uint32_t)SC_DMACR_RXLODB) -#define DMA_ChannelLoad_ARx ((uint32_t)SC_DMACR_RXLODA) - -#define IS_DMA_CHANNEL_LOAD(CHANNEL) (((CHANNEL) == DMA_ChannelLoad_BTx) || ((CHANNEL) == DMA_ChannelLoad_ATx) || \ - ((CHANNEL) == DMA_ChannelLoad_BRx) || ((CHANNEL) == DMA_ChannelLoad_ARx)) -/** - * @} - */ - -/** @defgroup DMA_Counter_Register - * @{ - */ - -#define DMA_Counter_RXCNTA ((uint32_t)0x00000000) -#define DMA_Counter_RXCNTB ((uint32_t)0x00000004) -#define DMA_Counter_TXCNT ((uint32_t)0x00000008) -#define DMA_Counter_RXCNTSAVED ((uint32_t)0x00000050) - -#define IS_DMA_COUNTER(COUNTER) (((COUNTER) == DMA_Counter_RXCNTA) || ((COUNTER) == DMA_Counter_RXCNTB) || \ - ((COUNTER) == DMA_Counter_TXCNT) || ((COUNTER) == DMA_Counter_RXCNTSAVED)) - -/** - * @} - */ - -/** @defgroup DMA_Receiver_Error_Register - * @{ - */ - -#define DMA_ReceiverError_CNTA ((uint32_t)0x00000014) -#define DMA_ReceiverError_CNTB ((uint32_t)0x00000018) - - -#define IS_DMA_RECEIVER_ERROR(REGISTER) (((REGISTER) == DMA_ReceiverError_CNTA) || ((REGISTER) == DMA_ReceiverError_CNTB)) - -/** - * @} - */ - -/** @defgroup DMA_Channel_Reset - * @{ - */ - -#define DMA_ChannelReset_Tx ((uint32_t)SC_DMACR_TXRST) -#define DMA_ChannelReset_Rx ((uint32_t)SC_DMACR_RXRST) - -#define IS_DMA_CHANNEL_RESET(CHANNEL) (((CHANNEL) == DMA_ChannelReset_Tx) || ((CHANNEL) == DMA_ChannelReset_Rx)) - -/** - * @} - */ - -/** @defgroup DMA_flags_definition - * @{ - */ -#define DMA_FLAG_RXAACK ((uint32_t)SC_DMASR_RXAACK) -#define DMA_FLAG_RXBACK ((uint32_t)SC_DMASR_RXBACK) -#define DMA_FLAG_TXAACK ((uint32_t)SC_DMASR_TXAACK) -#define DMA_FLAG_TXBACK ((uint32_t)SC_DMASR_TXBACK) -#define DMA_FLAG_OVRA ((uint32_t)SC_DMASR_OVRA) -#define DMA_FLAG_OVRB ((uint32_t)SC_DMASR_OVRB) -#define DMA_FLAG_PEA ((uint32_t)SC_DMASR_PEA) -#define DMA_FLAG_PEB ((uint32_t)SC_DMASR_PEB) -#define DMA_FLAG_FEA ((uint32_t)SC_DMASR_FEA) -#define DMA_FLAG_FEB ((uint32_t)SC_DMASR_FEB) -#define DMA_FLAG_NSSS ((uint32_t)SC_DMASR_NSSS) - -#define IS_DMA_FLAG(FLAG) (((FLAG) == DMA_FLAG_RXAACK) || ((FLAG) == DMA_FLAG_RXBACK) || \ - ((FLAG) == DMA_FLAG_TXAACK) || ((FLAG) == DMA_FLAG_TXBACK) || \ - ((FLAG) == DMA_FLAG_OVRA) || ((FLAG) == DMA_FLAG_OVRB) || \ - ((FLAG) == DMA_FLAG_PEA) || ((FLAG) == DMA_FLAG_PEB) || \ - ((FLAG) == DMA_FLAG_FEA) || ((FLAG) == DMA_FLAG_FEB) || \ - ((FLAG) == DMA_FLAG_NSSS)) -/** - * @} - */ - -/** @defgroup DMA_interrupts_definition - * @{ - */ -#define DMA_IT_TXULODB ((uint32_t)SC_ISR_TXULODB) -#define DMA_IT_TXULODA ((uint32_t)SC_ISR_TXULODA) -#define DMA_IT_RXULODB ((uint32_t)SC_ISR_RXULODB) -#define DMA_IT_RXULODA ((uint32_t)SC_ISR_RXULODA) - -#define IS_DMA_IT(IT) (((IT) == DMA_IT_TXULODB) || ((IT) == DMA_IT_TXULODA) || \ - ((IT) == DMA_IT_RXULODB) || ((IT) == DMA_IT_RXULODA)) -/** - * @} - */ - -#define IS_DMA_CHANNEL_PERIPH(PERIPH) (((PERIPH) == SC1_DMA_ChannelTx) || \ - ((PERIPH) == SC1_DMA_ChannelRx) || \ - ((PERIPH) == SC2_DMA_ChannelTx) || \ - ((PERIPH) == SC2_DMA_ChannelRx)) - -#define IS_DMA_VALID_ADDRESS(ADDRESS) (((ADDRESS) >= 0x20000000) && ((ADDRESS) <= 0x20000FFF)) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup SC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup SC_Exported_Functions - * @{ - */ -void UART_DeInit(SC_UART_TypeDef* SCx_UART); -void UART_Init(SC_UART_TypeDef* SCx_UART, UART_InitTypeDef* UART_InitStruct); -void UART_StructInit(UART_InitTypeDef* UART_InitStruct); -void UART_Cmd(SC_UART_TypeDef* SCx_UART, FunctionalState NewState); -void UART_ITConfig(SC_IT_TypeDef* SCx_IT, uint32_t UART_IT, FunctionalState NewState); -void UART_TriggerEventConfig(SC_IT_TypeDef* SCx_IT, uint32_t UART_IT, uint32_t TriggerEvent); -void UART_RTSAssertionCmd(SC_UART_TypeDef* SCx_UART, FunctionalState NewState); -void UART_SendData(SC_UART_TypeDef* SCx_UART, uint8_t Data); -uint8_t UART_ReceiveData(SC_UART_TypeDef* SCx_UART); -FlagStatus UART_GetFlagStatus(SC_UART_TypeDef* SCx_UART, uint32_t UART_FLAG); -ITStatus UART_GetITStatus(SC_IT_TypeDef* SCx_IT, uint32_t UART_IT); -void UART_ClearITPendingBit(SC_IT_TypeDef* SCx_IT, uint32_t UART_IT); - -void SPI_DeInit(SC_SPI_TypeDef* SCx_SPI); -void SPI_Init(SC_SPI_TypeDef* SCx_SPI, SPI_InitTypeDef* SPI_InitStruct); -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); -void SPI_ReceiverModeConfig(SC_SPI_TypeDef* SCx_SPI, uint32_t SPI_ReceiverMode); -void SPI_LastByteRepeatCmd(SC_SPI_TypeDef* SCx_SPI, FunctionalState NewState); -void SPI_Cmd(SC_SPI_TypeDef* SCx_SPI, FunctionalState NewState); -void SPI_ITConfig(SC_IT_TypeDef* SCx_IT, uint32_t SPI_IT, FunctionalState NewState); -void SPI_TriggerEventConfig(SC_IT_TypeDef* SCx_IT, uint32_t SPI_IT, uint32_t TriggerEvent); -void SPI_SendData(SC_SPI_TypeDef* SCx_SPI, uint8_t Data); -uint8_t SPI_ReceiveData(SC_SPI_TypeDef* SCx_SPI); -FlagStatus SPI_GetFlagStatus(SC_SPI_TypeDef* SCx_SPI, uint32_t SPI_FLAG); -ITStatus SPI_GetITStatus(SC_IT_TypeDef* SCx_IT, uint32_t SPI_IT); -void SPI_ClearITPendingBit(SC_IT_TypeDef* SCx_IT, uint32_t SPI_IT); - -void I2C_DeInit(SC_I2C_TypeDef* SCx_I2C); -void I2C_Init(SC_I2C_TypeDef* SCx_I2C, I2C_InitTypeDef* I2C_InitStruct); -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); -void I2C_Cmd(SC_I2C_TypeDef* SCx_I2C, FunctionalState NewState); -void I2C_ITConfig(SC_IT_TypeDef* SCx_IT, uint32_t I2C_IT, FunctionalState NewState); -void I2C_GenerateSTART(SC_I2C_TypeDef* SCx_I2C); -void I2C_GenerateSTOP(SC_I2C_TypeDef* SCx_I2C); -void I2C_AcknowledgeConfig(SC_I2C_TypeDef* SCx_I2C, FunctionalState NewState); -void I2C_Send7bitAddress(SC_I2C_TypeDef* SCx_I2C, uint8_t Address, uint8_t I2C_Direction); -void I2C_SendData(SC_I2C_TypeDef* SCx_I2C, uint8_t Data); -uint8_t I2C_ReceiveData(SC_I2C_TypeDef* SCx_I2C); -FlagStatus I2C_GetFlagStatus(SC_I2C_TypeDef* SCx_I2C, uint32_t I2C_FLAG); -ITStatus I2C_GetITStatus(SC_IT_TypeDef* SCx_IT, uint32_t I2C_IT); -void I2C_ClearITPendingBit(SC_IT_TypeDef* SCx_IT, uint32_t I2C_IT); - -void SC_DMA_ChannelReset(SC_DMA_TypeDef* SCx_DMA, uint32_t Channely); -void SC_DMA_Init(SC_DMA_Channel_TypeDef* SCx_DMA_Channely, SC_DMA_InitTypeDef* SC_DMA_InitStruct); -void SC_DMA_StructInit(SC_DMA_InitTypeDef* SC_DMA_InitStruct); -void SC_DMA_ChannelLoadEnable(SC_DMA_TypeDef* SCx_DMA, uint32_t Channelxy); -void SC_DMA_ITConfig(SC_IT_TypeDef* SCx_IT, uint32_t DMA_IT, FunctionalState NewState); -uint32_t SC_DMA_GetCounter(SC_DMA_TypeDef* SCx_DMA, uint32_t Counter); -uint32_t SC_DMA_GetReceiverErrorOffset(SC_DMA_TypeDef* SCx_DMA, uint32_t RegisterError); -FlagStatus SC_DMA_GetFlagStatus(SC_DMA_TypeDef* SCx_DMA, uint32_t DMA_FLAG); -ITStatus SC_DMA_GetITStatus(SC_IT_TypeDef* SCx_IT, uint32_t DMA_IT); -void SC_DMA_ClearITPendingBit(SC_IT_TypeDef* SCx_IT, uint32_t DMA_IT); - -/** - * @} - */ - -#ifdef __cplusplus -} - -#endif - -#endif /*__STM32W108XX_SC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_slptim.h b/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_slptim.h deleted file mode 100644 index 6a799db..0000000 --- a/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_slptim.h +++ /dev/null @@ -1,213 +0,0 @@ -/** - ****************************************************************************** - * @file stm32w108xx_slptim.h - * @author MCD Application Team - * @version V1.0.1 - * @date 30-November-2012 - * @brief This file contains all the functions prototypes for the TIM - * firmware library. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2012 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32W108XX_SLPTIM_H -#define __STM32W108XX_SLPTIM_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32w108xx.h" - -/** @addtogroup STM32W108xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SLPTIM - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - - /** - * @brief SLPTIM Init structure definition - */ -typedef struct -{ - uint32_t SLPTIM_Clock; /*!< Specifies the clock to be used. - This parameter must be a value of @ref SLPTIM_Clocks_Select */ - - uint32_t SLPTIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. - This parameter can be a value of @ref SLPTIM_Clock_Division */ - - uint32_t SLPTIM_DebugMode; /*!< Specifies whether the timer is running or paused during debug mode. - This parameter must be a value of @ref SLPTIM_Debug_Mode */ - - uint32_t SLPTIM_CounterMode; /*!< Specifies the counter mode. - This parameter can be a value of @ref SLPTIM_Counter_Mode */ -} SLPTIM_InitTypeDef; - -/** @defgroup SLPTIM_Exported_Constants - * @{ - */ - -/** @defgroup SLPTIM_Clocks_Select - * @{ - */ -#define SLPTIM_CLK_32KHZ ((uint32_t)SLPTMR_CR_CLKSEL) -#define SLPTIM_CLK_1KHZ ((uint32_t)0x00000000) -#define IS_SLPTIM_GET_CLKSEL(CLK) (((CLK) == SLPTIM_CLK_32KHZ) || \ - ((CLK) == SLPTIM_CLK_1KHZ)) -/** - * @} - */ - -/** @defgroup SLPTIM_Clock_Division - * @{ - */ -#define SLPTIM_CLK_DIV0 ((uint32_t)0x00000000) -#define SLPTIM_CLK_DIV1 ((uint32_t)0x00000010) -#define SLPTIM_CLK_DIV2 ((uint32_t)0x00000020) -#define SLPTIM_CLK_DIV3 ((uint32_t)0x00000030) -#define SLPTIM_CLK_DIV4 ((uint32_t)0x00000040) -#define SLPTIM_CLK_DIV5 ((uint32_t)0x00000050) -#define SLPTIM_CLK_DIV6 ((uint32_t)0x00000060) -#define SLPTIM_CLK_DIV7 ((uint32_t)0x00000070) -#define SLPTIM_CLK_DIV8 ((uint32_t)0x00000080) -#define SLPTIM_CLK_DIV9 ((uint32_t)0x00000090) -#define SLPTIM_CLK_DIV10 ((uint32_t)0x000000A0) -#define SLPTIM_CLK_DIV11 ((uint32_t)0x000000B0) -#define SLPTIM_CLK_DIV12 ((uint32_t)0x000000C0) -#define SLPTIM_CLK_DIV13 ((uint32_t)0x000000D0) -#define SLPTIM_CLK_DIV14 ((uint32_t)0x000000E0) -#define SLPTIM_CLK_DIV15 ((uint32_t)0x000000F0) -#define IS_SLPTIM_CLKDIV(CLKDIV) (((CLKDIV) == SLPTIM_CLK_DIV0) || ((CLKDIV) == SLPTIM_CLK_DIV1) || \ - ((CLKDIV) == SLPTIM_CLK_DIV2) || ((CLKDIV) == SLPTIM_CLK_DIV3) || \ - ((CLKDIV) == SLPTIM_CLK_DIV4) || ((CLKDIV) == SLPTIM_CLK_DIV5) || \ - ((CLKDIV) == SLPTIM_CLK_DIV6) || ((CLKDIV) == SLPTIM_CLK_DIV7) || \ - ((CLKDIV) == SLPTIM_CLK_DIV8) || ((CLKDIV) == SLPTIM_CLK_DIV9) || \ - ((CLKDIV) == SLPTIM_CLK_DIV10) || ((CLKDIV) == SLPTIM_CLK_DIV11) || \ - ((CLKDIV) == SLPTIM_CLK_DIV12) || ((CLKDIV) == SLPTIM_CLK_DIV13) || \ - ((CLKDIV) == SLPTIM_CLK_DIV14) || ((CLKDIV) == SLPTIM_CLK_DIV15)) -/** - * @} - */ - -/** @defgroup SLPTIM_Debug_Mode - * @{ - */ -#define SLPTIM_DBGRUN ((uint32_t)0x00000000) -#define SLPTIM_DBGPAUSE ((uint32_t)SLPTMR_CR_DBGP) -#define IS_SLPTIM_DBGMODE(DBGMODE) (((DBGMODE) == SLPTIM_DBGRUN) || \ - ((DBGMODE) == SLPTIM_DBGPAUSE)) -/** - * @} - */ - -/** @defgroup SLPTIM_Counter_Mode - * @{ - */ -#define SLPTIM_CountForward ((uint32_t)0x00000000) -#define SLPTIM_CountBackward ((uint32_t)SLPTMR_CR_REVERSE) -#define IS_SLPTIM_COUNTER_MODE(MODE) (((MODE) == SLPTIM_CountForward) || \ - ((MODE) == SLPTIM_CountBackward)) -/** - * @} - */ - -/** @defgroup SLPTIM_interrupt_sources - * @{ - */ -#define SLPTIM_IT_WRAP ((uint32_t)SLPTMR_IER_WRAP) -#define SLPTIM_IT_CMPA ((uint32_t)SLPTMR_IER_CMPA) -#define SLPTIM_IT_CMPB ((uint32_t)SLPTMR_IER_CMPB) -#define IS_SLPTIM_IT(IT) (((IT) == SLPTIM_IT_WRAP) || \ - ((IT) == SLPTIM_IT_CMPA) || \ - ((IT) == SLPTIM_IT_CMPB)) -/** - * @} - */ - -/** @defgroup SLPTIM_flags - * @{ - */ -#define SLPTIM_FLAG_WRAP ((uint32_t)SLPTMR_ISR_WRAP) -#define SLPTIM_FLAG_CMPA ((uint32_t)SLPTMR_ISR_CMPA) -#define SLPTIM_FLAG_CMPB ((uint32_t)SLPTMR_ISR_CMPB) -#define IS_SLPTIM_FLAG(FLAG) (((FLAG) == SLPTIM_FLAG_WRAP) || \ - ((FLAG) == SLPTIM_FLAG_CMPA) || \ - ((FLAG) == SLPTIM_FLAG_CMPB)) -/** - * @} - */ -/** - * @} - */ - -/** @defgroup SLPTIM_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup SLPTIM_Exported_Functions - * @{ - */ -/* SLPTIM management functions ************************************************/ -void SLPTIM_DeInit(void); -void SLPTIM_Init(SLPTIM_InitTypeDef* SLPTIM_InitStruct); -void SLPTIM_StructInit(SLPTIM_InitTypeDef* SLPTIM_InitStruct); -void SLPTIM_Cmd(FunctionalState NewState); -void SLPTIM_SetCompareA(uint32_t CompareA); -void SLPTIM_SetCompareB(uint32_t CompareB); -uint32_t SLPTIM_GetCounter(void); -uint32_t SLPTIM_GetCounterHigh(void); -uint32_t SLPTIM_GetCounterLow(void); -/* Interrupts and flags management functions **********************************/ -void SLPTIM_ForceIT(uint32_t SLPTIM_IT); -void SLPTIM_ITConfig(uint32_t SLPTIM_IT, FunctionalState NewState); -FlagStatus SLPTIM_GetFlagStatus(uint32_t SLPTIM_FLAG); -void SLPTIM_ClearFlag(uint32_t SLPTIM_FLAG); -ITStatus SLPTIM_GetITStatus(uint32_t SLPTIM_IT); -void SLPTIM_ClearITPendingBit(uint32_t SLPTIM_IT); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32W108XX_SLPTIM_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_tim.h b/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_tim.h deleted file mode 100644 index e317e6e..0000000 --- a/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_tim.h +++ /dev/null @@ -1,658 +0,0 @@ -/** - ****************************************************************************** - * @file stm32w108xx_tim.h - * @author MCD Application Team - * @version V1.0.1 - * @date 30-November-2012 - * @brief This file contains all the functions prototypes for the TIM - * firmware library. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2012 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32W108XX_TIM_H -#define __STM32W108XX_TIM_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32w108xx.h" - -/** @addtogroup STM32W108xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup TIM - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief TIM Time Base Init structure definition - * @note This sturcture is used with all TIMx. - */ -typedef struct -{ - uint32_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between 0x0000 and 0x000F */ - - uint32_t TIM_CounterMode; /*!< Specifies the counter mode. - This parameter can be a value of @ref TIM_Counter_Mode */ - - uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter must be a number between 0x0000 and 0xFFFF. */ -} TIM_TimeBaseInitTypeDef; - -/** - * @brief TIM Output Compare Init structure definition - */ -typedef struct -{ - uint32_t TIM_OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint32_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_state */ - - uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint32_t TIM_OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ -} TIM_OCInitTypeDef; - -/** - * @brief TIM Input Capture Init structure definition - */ -typedef struct -{ - - uint32_t TIM_Channel; /*!< Specifies the TIM channel. - This parameter can be a value of @ref TIM_Channel */ - - uint32_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t TIM_ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t TIM_ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between 0x0 and 0xF */ -} TIM_ICInitTypeDef; - - -/** @defgroup TIM_Exported_constants - * @{ - */ - -#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2)) - -#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM2)) - -#define IS_TIM_IT_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1_IT) || \ - ((PERIPH) == TIM2_IT)) - -/** @defgroup TIM_Output_Compare_and_PWM_modes - * @{ - */ -#define TIM_OCMode_Timing ((uint32_t)0x00000000) -#define TIM_OCMode_Active ((uint32_t)0x00000010) -#define TIM_OCMode_Inactive ((uint32_t)0x00000020) -#define TIM_OCMode_Toggle ((uint32_t)0x00000030) -#define TIM_OCMode_PWM1 ((uint32_t)0x00000060) -#define TIM_OCMode_PWM2 ((uint32_t)0x00000070) -#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ - ((MODE) == TIM_OCMode_Active) || \ - ((MODE) == TIM_OCMode_Inactive) || \ - ((MODE) == TIM_OCMode_Toggle)|| \ - ((MODE) == TIM_OCMode_PWM1) || \ - ((MODE) == TIM_OCMode_PWM2)) -#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ - ((MODE) == TIM_OCMode_Active) || \ - ((MODE) == TIM_OCMode_Inactive) || \ - ((MODE) == TIM_OCMode_Toggle)|| \ - ((MODE) == TIM_OCMode_PWM1) || \ - ((MODE) == TIM_OCMode_PWM2) || \ - ((MODE) == TIM_ForcedAction_Active) || \ - ((MODE) == TIM_ForcedAction_InActive)) -/** - * @} - */ - -/** @defgroup TIM_One_Pulse_Mode - * @{ - */ -#define TIM_OPMode_Single ((uint32_t)0x00000008) -#define TIM_OPMode_Repetitive ((uint32_t)0x00000000) -#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ - ((MODE) == TIM_OPMode_Repetitive)) -/** - * @} - */ - -/** @defgroup TIM_Channel - * @{ - */ -#define TIM_Channel_1 ((uint32_t)0x00000000) -#define TIM_Channel_2 ((uint32_t)0x00000004) -#define TIM_Channel_3 ((uint32_t)0x00000008) -#define TIM_Channel_4 ((uint32_t)0x0000000C) - -#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2) || \ - ((CHANNEL) == TIM_Channel_3) || \ - ((CHANNEL) == TIM_Channel_4)) -#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2)) -/** - * @} - */ - -/** @defgroup TIM_Counter_Mode - * @{ - */ -#define TIM_CounterMode_Up ((uint32_t)0x00000000) -#define TIM_CounterMode_Down ((uint32_t)0x00000010) -#define TIM_CounterMode_CenterAligned1 ((uint32_t)0x00000020) -#define TIM_CounterMode_CenterAligned2 ((uint32_t)0x00000040) -#define TIM_CounterMode_CenterAligned3 ((uint32_t)0x00000060) -#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ - ((MODE) == TIM_CounterMode_Down) || \ - ((MODE) == TIM_CounterMode_CenterAligned1) || \ - ((MODE) == TIM_CounterMode_CenterAligned2) || \ - ((MODE) == TIM_CounterMode_CenterAligned3)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Polarity - * @{ - */ -#define TIM_OCPolarity_High ((uint32_t)0x00000000) -#define TIM_OCPolarity_Low ((uint32_t)0x00000002) -#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ - ((POLARITY) == TIM_OCPolarity_Low)) -/** - * @} - */ - - -/** @defgroup TIM_Output_Compare_state - * @{ - */ -#define TIM_OutputState_Disable ((uint32_t)0x00000000) -#define TIM_OutputState_Enable ((uint32_t)0x00000001) -#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ - ((STATE) == TIM_OutputState_Enable)) -/** - * @} - */ - - -/** @defgroup TIM_Capture_Compare_state - * @{ - */ -#define TIM_CCx_Enable ((uint32_t)0x00000001) -#define TIM_CCx_Disable ((uint32_t)0x00000000) -#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ - ((CCX) == TIM_CCx_Disable)) -/** - * @} - */ - - -/** @defgroup TIM_Input_Capture_Polarity - * @{ - */ -#define TIM_ICPolarity_Rising ((uint32_t)0x00000000) -#define TIM_ICPolarity_Falling ((uint32_t)0x00000002) -#define TIM_ICPolarity_BothEdge ((uint32_t)0x0000000A) -#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ - ((POLARITY) == TIM_ICPolarity_Falling)|| \ - ((POLARITY) == TIM_ICPolarity_BothEdge)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Selection - * @{ - */ -#define TIM_ICSelection_DirectTI ((uint32_t)0x00000001) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSelection_IndirectTI ((uint32_t)0x00000002) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC2, IC1, IC4 or IC3, respectively. */ -#define TIM_ICSelection_TRGI ((uint32_t)0x00000003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ -#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ - ((SELECTION) == TIM_ICSelection_IndirectTI) || \ - ((SELECTION) == TIM_ICSelection_TRGI)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Prescaler - * @{ - */ -#define TIM_ICPSC_DIV1 ((uint32_t)0x00000000) /*!< Capture performed each time an edge is detected on the capture input. */ -#define TIM_ICPSC_DIV2 ((uint32_t)0x00000004) /*!< Capture performed once every 2 events. */ -#define TIM_ICPSC_DIV4 ((uint32_t)0x00000008) /*!< Capture performed once every 4 events. */ -#define TIM_ICPSC_DIV8 ((uint32_t)0x0000000C) /*!< Capture performed once every 8 events. */ -#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ - ((PRESCALER) == TIM_ICPSC_DIV2) || \ - ((PRESCALER) == TIM_ICPSC_DIV4) || \ - ((PRESCALER) == TIM_ICPSC_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_interrupt_sources - * @{ - */ -#define TIM_IT_Update ((uint32_t)0x00000001) -#define TIM_IT_CC1 ((uint32_t)0x00000002) -#define TIM_IT_CC2 ((uint32_t)0x00000004) -#define TIM_IT_CC3 ((uint32_t)0x00000008) -#define TIM_IT_CC4 ((uint32_t)0x00000010) -#define TIM_IT_Trigger ((uint32_t)0x00000040) -#define IS_TIM_ITRPT(IT) ((((IT) & (uint32_t)0xFFFFFF00) == 0x00000000) && ((IT) != 0x00000000)) - -#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ - ((IT) == TIM_IT_CC1) || \ - ((IT) == TIM_IT_CC2) || \ - ((IT) == TIM_IT_CC3) || \ - ((IT) == TIM_IT_CC4) || \ - ((IT) == TIM_IT_Trigger)) -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Prescaler - * @{ - */ -#define TIM_ExtTRGPSC_OFF ((uint32_t)0x00000000) -#define TIM_ExtTRGPSC_DIV2 ((uint32_t)0x00001000) -#define TIM_ExtTRGPSC_DIV4 ((uint32_t)0x00002000) -#define TIM_ExtTRGPSC_DIV8 ((uint32_t)0x00003000) -#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_Internal_Trigger_Selection - * @{ - */ -#define TIM_TS_ITR0 ((uint32_t)0x00000000) -#define TIM_TS_TI1F_ED ((uint32_t)0x00000040) -#define TIM_TS_TI1FP1 ((uint32_t)0x00000050) -#define TIM_TS_TI2FP2 ((uint32_t)0x00000060) -#define TIM_TS_ETRF ((uint32_t)0x00000070) -#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_TI1F_ED) || \ - ((SELECTION) == TIM_TS_TI1FP1) || \ - ((SELECTION) == TIM_TS_TI2FP2) || \ - ((SELECTION) == TIM_TS_ETRF)) -#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0)) -/** - * @} - */ - -/** @defgroup TIM_TIx_External_Clock_Source - * @{ - */ -#define TIM_TIxExternalCLK1Source_TI1 ((uint32_t)0x00000050) -#define TIM_TIxExternalCLK1Source_TI2 ((uint32_t)0x00000060) -#define TIM_TIxExternalCLK1Source_TI1ED ((uint32_t)0x00000040) - -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Polarity - * @{ - */ -#define TIM_ExtTRGPolarity_Inverted ((uint32_t)0x00008000) -#define TIM_ExtTRGPolarity_NonInverted ((uint32_t)0x00000000) -#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ - ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) -/** - * @} - */ - -/** @defgroup TIM_Prescaler_Reload_Mode - * @{ - */ -#define TIM_PSCReloadMode_Update ((uint32_t)0x00000000) -#define TIM_PSCReloadMode_Immediate ((uint32_t)0x00000001) -#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ - ((RELOAD) == TIM_PSCReloadMode_Immediate)) -/** - * @} - */ - -/** @defgroup TIM_Forced_Action - * @{ - */ -#define TIM_ForcedAction_Active ((uint32_t)0x00000050) -#define TIM_ForcedAction_InActive ((uint32_t)0x00000040) -#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ - ((ACTION) == TIM_ForcedAction_InActive)) -/** - * @} - */ - -/** @defgroup TIM_Encoder_Mode - * @{ - */ -#define TIM_EncoderMode_TI1 ((uint32_t)0x00000001) -#define TIM_EncoderMode_TI2 ((uint32_t)0x00000002) -#define TIM_EncoderMode_TI12 ((uint32_t)0x00000003) -#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ - ((MODE) == TIM_EncoderMode_TI2) || \ - ((MODE) == TIM_EncoderMode_TI12)) -/** - * @} - */ - -/** @defgroup TIM_Event_Source - * @{ - */ -#define TIM_EventSource_Update ((uint32_t)0x00000001) -#define TIM_EventSource_CC1 ((uint32_t)0x00000002) -#define TIM_EventSource_CC2 ((uint32_t)0x00000004) -#define TIM_EventSource_CC3 ((uint32_t)0x00000008) -#define TIM_EventSource_CC4 ((uint32_t)0x00000010) -#define TIM_EventSource_Trigger ((uint32_t)0x00000040) -#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint32_t)0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000)) - -/** - * @} - */ - -/** @defgroup TIM_Update_Source - * @{ - */ -#define TIM_UpdateSource_Global ((uint32_t)0x00000000) /*!< Source of update is the counter overflow/underflow - or the setting of UG bit, or an update generation - through the slave mode controller. */ -#define TIM_UpdateSource_Regular ((uint32_t)0x00000001) /*!< Source of update is counter overflow/underflow. */ -#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ - ((SOURCE) == TIM_UpdateSource_Regular)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Preload_State - * @{ - */ -#define TIM_OCPreload_Enable ((uint32_t)0x00000008) -#define TIM_OCPreload_Disable ((uint32_t)0x00000000) -#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ - ((STATE) == TIM_OCPreload_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Fast_State - * @{ - */ -#define TIM_OCFast_Enable ((uint32_t)0x00000004) -#define TIM_OCFast_Disable ((uint32_t)0x00000000) -#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ - ((STATE) == TIM_OCFast_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Trigger_Output_Source - * @{ - */ -#define TIM_TRGOSource_Reset ((uint32_t)0x00000000) -#define TIM_TRGOSource_Enable ((uint32_t)0x00000010) -#define TIM_TRGOSource_Update ((uint32_t)0x00000020) -#define TIM_TRGOSource_OC1 ((uint32_t)0x00000030) -#define TIM_TRGOSource_OC1Ref ((uint32_t)0x00000040) -#define TIM_TRGOSource_OC2Ref ((uint32_t)0x00000050) -#define TIM_TRGOSource_OC3Ref ((uint32_t)0x00000060) -#define TIM_TRGOSource_OC4Ref ((uint32_t)0x00000070) -#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ - ((SOURCE) == TIM_TRGOSource_Enable) || \ - ((SOURCE) == TIM_TRGOSource_Update) || \ - ((SOURCE) == TIM_TRGOSource_OC1) || \ - ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC4Ref)) -/** - * @} - */ - -/** @defgroup TIM_Slave_Mode - * @{ - */ -#define TIM_SlaveMode_Reset ((uint32_t)0x00000004) -#define TIM_SlaveMode_Gated ((uint32_t)0x00000005) -#define TIM_SlaveMode_Trigger ((uint32_t)0x00000006) -#define TIM_SlaveMode_External1 ((uint32_t)0x00000007) -#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ - ((MODE) == TIM_SlaveMode_Gated) || \ - ((MODE) == TIM_SlaveMode_Trigger) || \ - ((MODE) == TIM_SlaveMode_External1)) -/** - * @} - */ - -/** @defgroup TIM_Master_Slave_Mode - * @{ - */ -#define TIM_MasterSlaveMode_Enable ((uint32_t)0x00000080) -#define TIM_MasterSlaveMode_Disable ((uint32_t)0x00000000) -#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ - ((STATE) == TIM_MasterSlaveMode_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Filer_Value - * @{ - */ -#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Filter - * @{ - */ -#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_OCReferenceClear - * @{ - */ -#define TIM_OCReferenceClear_ETRF ((uint32_t)0x00000008) -#define TIM_OCReferenceClear_OCREFCLR ((uint32_t)0x00000000) -#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \ - ((SOURCE) == TIM_OCReferenceClear_OCREFCLR)) -/** - * @} - */ - -/** @defgroup TIM_Remap - * @{ - */ -#define TIM_REMAPC1 ((uint32_t)0x00000010) -#define TIM_REMAPC2 ((uint32_t)0x00000020) -#define TIM_REMAPC3 ((uint32_t)0x00000040) -#define TIM_REMAPC4 ((uint32_t)0x00000080) -#define IS_TIM_REMAP(TIM_Remap) (((TIM_Remap) == TIM_REMAPC1) || \ - ((TIM_Remap) == TIM_REMAPC2) || \ - ((TIM_Remap) == TIM_REMAPC3) || \ - ((TIM_Remap) == TIM_REMAPC4)) -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Selection - * @{ - */ -#define TIM_EXTRIGPCLK ((uint32_t)0x00000000) -#define TIM_EXTRIG1KHCLK ((uint32_t)0x00000001) -#define TIM_EXTRIG32KHCLK ((uint32_t)0x00000002) -#define TIM_EXTRIGTIMxCLK ((uint32_t)0x00000003) -#define IS_TIM_EXTRIGCLK(EXTRIGCLK) (((EXTRIGCLK) == TIM_EXTRIGPCLK) || \ - ((EXTRIGCLK) == TIM_EXTRIG1KHCLK) || \ - ((EXTRIGCLK) == TIM_EXTRIG32KHCLK) || \ - ((EXTRIGCLK) == TIM_EXTRIGTIMxCLK)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup TIM_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions - * @{ - */ -/* TimeBase management ********************************************************/ -void TIM_DeInit(TIM_TypeDef* TIMx); -void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); -void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint32_t Prescaler, uint32_t TIM_PSCReloadMode); -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint32_t TIM_CounterMode); -void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter); -void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload); -uint32_t TIM_GetCounter(TIM_TypeDef* TIMx); -uint32_t TIM_GetPrescaler(TIM_TypeDef* TIMx); -void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint32_t TIM_UpdateSource); -void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint32_t TIM_OPMode); -void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); -/* Output Compare management **************************************************/ -void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint32_t TIM_Channel, uint32_t TIM_OCMode); -void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1); -void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2); -void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3); -void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4); -void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint32_t TIM_ForcedAction); -void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint32_t TIM_ForcedAction); -void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint32_t TIM_ForcedAction); -void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint32_t TIM_ForcedAction); -void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPreload); -void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPreload); -void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPreload); -void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPreload); -void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCFast); -void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCFast); -void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCFast); -void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCFast); -void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPolarity); -void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPolarity); -void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPolarity); -void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPolarity); -void TIM_CCxCmd(TIM_TypeDef* TIMx, uint32_t TIM_Channel, uint32_t TIM_CCx); -/* Input Capture management ***************************************************/ -void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); -uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx); -uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx); -uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx); -uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx); -void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint32_t TIM_ICPSC); -void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint32_t TIM_ICPSC); -void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint32_t TIM_ICPSC); -void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint32_t TIM_ICPSC); -/* Interrupts and flags management functions **********************************/ -void TIM_ITConfig(TIM_IT_TypeDef* TIMx_IT, uint32_t TIM_ITRPT, FunctionalState NewState); -ITStatus TIM_GetITStatus(TIM_IT_TypeDef* TIMx_IT, uint32_t TIM_ITRPT); -void TIM_ClearITPendingBit(TIM_IT_TypeDef* TIMx_IT, uint32_t TIM_ITRPT); -void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint32_t TIM_EventSource); -/* Clocks management **********************************************************/ -void TIM_InternalClockConfig(TIM_TypeDef* TIMx); -void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint32_t TIM_InputTriggerSource); -void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint32_t TIM_TIxExternalCLKSource, - uint32_t TIM_ICPolarity, uint32_t ICFilter); -void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, - uint32_t ExtTRGFilter); -void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, - uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); -/* Synchronization management *************************************************/ -void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint32_t TIM_InputTriggerSource); -void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint32_t TIM_TRGOSource); -void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint32_t TIM_SlaveMode); -void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint32_t TIM_MasterSlaveMode); -void TIM_ETRConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, - uint32_t ExtTRGFilter); -/* Specific interface management **********************************************/ -void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint32_t TIM_EncoderMode, - uint32_t TIM_IC1Polarity, uint32_t TIM_IC2Polarity); -void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); -/* Specific remapping management **********************************************/ -void TIM_ClockMaskConfig(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectExternalTriggerClock(TIM_TypeDef* TIMx, uint32_t TIM_EXTRIGCLK); -void TIM_RemapCmd(TIM_TypeDef* TIMx, uint32_t TIM_Remap, FunctionalState NewState); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32W108XX_TIM_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_wdg.h b/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_wdg.h deleted file mode 100644 index 8d5798c..0000000 --- a/libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_wdg.h +++ /dev/null @@ -1,105 +0,0 @@ -/** - ****************************************************************************** - * @file stm32w108xx_wdg.h - * @author MCD Application Team - * @version V1.0.1 - * @date 30-November-2012 - * @brief This file contains all the functions prototypes for the WDG - * firmware library. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2012 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32W108XX_WDG_H -#define __STM32W108XX_WDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32w108xx.h" - -/** @addtogroup STM32W108xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup WDG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup WDG_Exported_Constants - * @{ - */ - -/** @defgroup WDG_DebugStatus - * @{ - */ -#define WDG_DBG_RUN ((uint32_t)0x00000000) -#define WDG_DBG_PAUSE ((uint32_t)0x00000400) -#define IS_WDG_DEBUG_STATUS(STATUS) (((STATUS) == WDG_DBG_RUN) || ((STATUS) == WDG_DBG_PAUSE)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup WDG_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup WDG_Exported_Functions - * @{ - */ -/* WDG activation function ****************************************************/ -void WDG_DeInit(void); -void WDG_ReloadCounter(void); -void WDG_Cmd(FunctionalState NewState); -void WDG_DebugConfig(uint32_t DBG_STATUS); -FunctionalState WDG_GetStatus(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32W108XX_WDG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_adc.c b/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_adc.c deleted file mode 100644 index 81f5704..0000000 --- a/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_adc.c +++ /dev/null @@ -1,501 +0,0 @@ - /** - ****************************************************************************** - * @file stm32w108xx_adc.c - * @author MCD Application Team - * @version V1.0.1 - * @date 30-November-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the Analog to Digital Convertor (ADC) peripheral: - * + ADC initialization and Configuration - * + DMA Configuration functions - * + Interrupts and flags management functions - * - * @verbatim - * - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - (#) Configure GPIO pins to be used by the ADC in analog mode. - (#) Configure the voltage reference (internal or external). - (#) Set the offset and gain values. - (#) Reset the ADC DMA, define the DMA buffer, and start the DMA in the - proper transfer mode. - (#) Write the ADC configuration register to define the inputs, voltage - range, sample time and start the conversions. - - @endverbatim - * - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2012 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ - -#include "stm32w108xx_adc.h" - -/** @addtogroup STM32W108xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup ADC - * @brief ADC driver modules - * @{ - */ - -/* External variables --------------------------------------------------------*/ -/* Private typedef -----------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -/* ADC INPUTN and INPUTP channel mask */ -#define ADC_INPUT_NP_Reset ((uint16_t)0xF807) - -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup ADC_Private_Functions - * @{ - */ - -/** @defgroup ADC_Group1 Initialization and Control functions - * @brief Initialization and Control functions - * -@verbatim - =============================================================================== - ##### Initialization and Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the ADC - (+) ADC Conversion Resolution (5bits --> 12bits) - (+) Enable or disable the ADC peripheral - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes ADC peripheral registers to their default reset - * values. - * @param None - * @retval None - */ -void ADC_DeInit(void) -{ - ADC->ISR = 0x0000001F; - ADC->IER = 0x00000000; - ADC->CR = 0x00001800; - ADC->OFFSETR = 0x00000000; - ADC->GAINR = 0x00008000; - ADC->DMACR = 0x00000010; - ADC->DMAMSAR = 0x20000000; - ADC->DMANDTR = 0x00000000; -} - -/** - * @brief Initializes the ADC peripheral according to the specified - * parameters in the ADC_InitStruct. - * @param ADC_InitStruct: pointer to ADC_InitTypeDef structure - * that contains the configuration information for the ADC peripheral. - * @retval None - */ -void ADC_Init(ADC_InitTypeDef* ADC_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution)); - assert_param(IS_ADC_VoltageP(ADC_InitStruct->ADC_VoltageP)); - assert_param(IS_ADC_VoltageN(ADC_InitStruct->ADC_VoltageN)); - assert_param(IS_ADC_CHANNEL(ADC_InitStruct->ADC_Input)); - assert_param(IS_ADC_DMA_MODE(ADC_InitStruct->ADC_DMAMode)); - assert_param(IS_ADC_CLOCK(ADC_InitStruct->ADC_Clock)); - assert_param(IS_ADC_OFFSET(ADC_InitStruct->ADC_Offset)); - assert_param(IS_ADC_GAIN(ADC_InitStruct->ADC_Gain)); - - /*---------------------------- ADC CR Configuration -----------------------*/ - - /* Configure ADC: scan conversion mode and resolution */ - /* Set ADC_1MHZCLK bit according to ADC_Clock value */ - /* Set ADC_MUX bits according to ADC_Input values */ - /* Set ADC_HVSELN bit according to ADC_VoltageN value */ - /* Set ADC_HVSELP bit according to ADC_VoltageP value */ - /* Set ADC_PERIOD[0:2] bits according to ADC_Clock value */ - tmpreg |= (uint32_t)(ADC_InitStruct->ADC_Resolution | ADC_InitStruct->ADC_VoltageP | - ADC_InitStruct->ADC_VoltageN | (uint32_t)((ADC_InitStruct->ADC_Input) << 0x3) | - ADC_InitStruct->ADC_Clock); - - /* Write to ADC CR */ - ADC->CR = (uint32_t)tmpreg; - - /*---------------------------- ADC DMA Configuration -----------------------*/ - /* Write to ADC DMA */ - ADC->DMACR = (uint32_t)(ADC_InitStruct->ADC_DMAMode); - - /*---------------------------- ADC ADC_OFFSETR Configuration ---------------*/ - /* Write to ADC ADC_OFFSETR */ - ADC->OFFSETR = (int32_t)(ADC_InitStruct->ADC_Offset); - - /*---------------------------- ADC ADC_GAINR Configuration -----------------*/ - /* Write to ADC ADC_GAINR */ - ADC->GAINR = (uint32_t)(ADC_InitStruct->ADC_Gain); -} - -/** - * @brief Fills each ADC_InitStruct member with its default value - * @param ADC_InitStruct: pointer to a ADC_InitTypeDef structure - * which will be initialized. - * @retval None - */ -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) -{ - /* Initialize the ADC resolution */ - ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b; - ADC_InitStruct->ADC_VoltageP = ADC_VoltageP_Low; - ADC_InitStruct->ADC_VoltageN = ADC_VoltageN_Low; - ADC_InitStruct->ADC_Input = ADC_SOURCE_VREF; - ADC_InitStruct->ADC_DMAMode = ADC_DMAMode_Linear; - ADC_InitStruct->ADC_Clock = ADC_Clock_6MHz; - ADC_InitStruct->ADC_Offset = 0; - ADC_InitStruct->ADC_Gain = 0x00008000; -} - -/** - * @brief Enables or disables the specified ADC peripheral - * @param NewState: new state of the ADC peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the ADC peripheral */ - ADC->CR |= (uint32_t)ADC_CR_ADON; - } - else - { - /* Disable the ADC peripheral */ - ADC->CR &= (uint32_t)(~ADC_CR_ADON); - } -} - -/** - * @} - */ - -/** @defgroup ADC_Group2 ADC channel Configuration functions - * @brief ADC channel Configuration functions - * -@verbatim - =============================================================================== - ##### ADC channel Configuration functions ##### - =============================================================================== - [..] This section provides function allowing to configure the ADC channels - -@endverbatim - * @{ - */ - -/** - * @brief Selects the ADC channel - * @param ADC_Channels: specifies the ADC channel - * This parameter can be one of the following values: - * @arg ADC_SOURCE_ADC0_VREF2 - * @arg ADC_SOURCE_ADC0_GND - * @arg ADC_SOURCE_ADC1_VREF2 - * @arg ADC_SOURCE_ADC1_GND - * @arg ADC_SOURCE_ADC2_VREF2 - * @arg ADC_SOURCE_ADC2_GND - * @arg ADC_SOURCE_ADC3_VREF2 - * @arg ADC_SOURCE_ADC3_GND - * @arg ADC_SOURCE_ADC4_VREF2 - * @arg ADC_SOURCE_ADC5_VREF2 - * @arg ADC_SOURCE_ADC1_ADC0 - * @arg ADC_SOURCE_ADC0_ADC1 - * @arg ADC_SOURCE_ADC3_ADC2 - * @arg ADC_SOURCE_ADC2_ADC3 - * @arg ADC_SOURCE_ADC5_ADC4 - * @arg ADC_SOURCE_GND_VREF2 - * @arg ADC_SOURCE_VGND - * @arg ADC_SOURCE_VREF_VREF2 - * @arg ADC_SOURCE_VREF - * @retval None - */ -void ADC_ChannelConfig(uint32_t ADC_Channels) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_CHANNEL(ADC_Channels)); - - /* Get the old register value */ - tmpreg = ADC->CR; - /* Clear the old channels */ - tmpreg &= ADC_INPUT_NP_Reset; - /* Set the new channels */ - tmpreg |= (uint32_t)((ADC_Channels << 0x3)); - /* Store the new register value */ - ADC->CR = (uint32_t)tmpreg; -} - -/** - * @} - */ - -/** @defgroup ADC_Group3 DMA Configuration functions - * @brief DMA Configuration functions - * -@verbatim - =============================================================================== - ##### DMA Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) initialize and configure the DMA - (+) reset and enable the DMA -@endverbatim - * @{ - */ - -/** - * @brief Selects the specified DMA configuration - * @param ADC_DMABeg: specifies the ADC buffer start address - * @param ADC_DMASize: specifies the ADC buffer size - * @retval None - */ - -void ADC_DMA_Config(uint32_t ADC_DMABeg, uint32_t ADC_DMASize) -{ - /* Check the parameters */ - assert_param(IS_ADC_BEGIN(ADC_DMABeg)); - assert_param(IS_ADC_SIZE(ADC_DMASize)); - - ADC->DMAMSAR = (uint32_t)ADC_DMABeg; - ADC->DMANDTR = (uint32_t)ADC_DMASize; -} - - /** - * @brief Enables specified ADC DMA Channel - * @param None - * @retval None - */ -void ADC_DMA_ChannelLoadEnable(void) -{ - /* Start the ADC DMA */ - ADC->DMACR |= (uint32_t)ADC_DMACR_LOAD; -} - - /** - * @brief Reset specified ADC DMA - * @param None - * @retval None - */ -void ADC_DMA_ChannelReset(void) -{ - /* Reset the ADC DMA */ - ADC->DMACR = (uint32_t)ADC_DMACR_RST; -} - - /** - * @brief Gets the the location that will be written next by the DMA - * @param None - * @retval the current DMA address - */ -uint32_t ADC_DMA_GetNextAddress(void) -{ - /*return the next address buffer*/ - return (uint32_t) ADC->DMAMNAR; -} - - /** - * @brief Gets the number of 16-bit conversion results that have been - * written to the buffer - * @param None - * @retval The number of conversions - */ -uint32_t ADC_DMA_GetCounter(void) -{ - /*return the number of conversions*/ - return (uint32_t) ADC->DMACNDTR; -} - -/** @defgroup ADC_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - - [..] This section provides functions allowing to : - (+) configure the ADC Interrupts and to get the status and clear flags - and Interrupts pending bits. - (+) get the status of DMA and clear flags - - *** Flags and Interrupts for ADC *** - ============================================== - [..] - (+)Flags : - (##) ADC_IT_DMABHF: DMA buffer half full interrupt pending - (##) ADC_IT_DMABF: DMA buffer full interrupt pending - (##) ADC_IT_SAT: Gain correction saturation interrupt pending - (##) ADC_IT_DMAOVF: DMA buffer overflow interrupt pending - - (+)Interrupts : - (##) ADC_IT_DMABHF: DMA buffer half full interrupt enable - (##) ADC_IT_DMABF: DMA buffer full interrupt enable - (##) ADC_IT_SAT: Gain correction saturation interrupt enable - (##) ADC_IT_DMAOVF: DMA buffer overflow interrupt enable - - *** Flags for ADC_DMA *** - ============================================== - [..] - (+)Flags : - (##) ADC_FLAG_ACT: DMA active - (##) ADC_FLAG_OVF: DMA over flow - -@endverbatim - - * @{ - */ - -/** - * @brief Enables or disables the specified ADC interrupts - * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled - * This parameter can be one of the following values: - * @arg ADC_IT_DMABHF: DMA buffer half full interrupt enable - * @arg ADC_IT_DMABF: DMA buffer full interrupt enable - * @arg ADC_IT_SAT: Gain correction saturation interrupt enable - * @arg ADC_IT_DMAOVF: DMA buffer overflow interrupt enable - * @param NewState: new state of the specified ADC interrupts - * This parameter can be: ENABLE or DISABLE - * @retval None - */ -void ADC_ITConfig(uint32_t ADC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_ADC_IT(ADC_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected ADC interrupts */ - ADC->IER |= (uint32_t)ADC_IT; - } - else - { - /* Disable the selected ADC interrupts */ - ADC->IER &= ~(uint32_t)ADC_IT; - } -} - -/** - * @brief Checks whether the specified ADC interrupt has occurred or not - * @param ADC_DMA_FLAG: specifies the flag to check - * This parameter can be one of the following values: - * @arg ADC_FLAG_ACT: DMA active - * @arg ADC_FLAG_OVF: DMA over flow - * @retval The new state of ADC_DMA_FLAG (SET or RESET). - */ -FlagStatus ADC_DMA_GetFlagStatus(uint32_t ADC_DMA_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_ADC_DMA_FLAG(ADC_DMA_FLAG)); - - if ((ADC->ISR & ADC_DMA_FLAG) != RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Checks whether the specified ADC pending interrupt has occurred or not - * @param ADC_IT: specifies the flag to check - * This parameter can be one of the following values: - * @arg ADC_IT_DMABHF: DMA buffer half full interrupt pending - * @arg ADC_IT_DMABF: DMA buffer full interrupt pending - * @arg ADC_IT_SAT: Gain correction saturation interrupt pending - * @arg ADC_IT_DMAOVF: DMA buffer overflow interrupt pending - * @retval The new state of ADC_IT (SET or RESET) - */ - -ITStatus ADC_GetITStatus(uint32_t ADC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_ADC_IT(ADC_IT)); - - enablestatus = (uint32_t)(ADC->IER & ADC_IT); - if (((ADC->ISR & ADC_IT) != (uint32_t)RESET) && enablestatus) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the ADC interrupt pending bits - * @param ADC_IT: specifies the flag to clear - * This parameter can be one of the following values: - * @arg ADC_IT_DMABHF: DMA buffer half full interrupt pending - * @arg ADC_IT_DMABF: DMA buffer full interrupt pending - * @arg ADC_IT_SAT: Gain correction saturation interrupt pending - * @arg ADC_IT_DMAOVF: DMA buffer overflow interrupt pending - * @retval None - */ -void ADC_ClearITPendingBit(uint32_t ADC_IT) -{ - /* Check the parameters */ - assert_param(IS_ADC_IT(ADC_IT)); - - /* Clear the selected ADC flags */ - ADC->ISR = (uint32_t)ADC_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_clk.c b/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_clk.c deleted file mode 100644 index 54eefdc..0000000 --- a/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_clk.c +++ /dev/null @@ -1,557 +0,0 @@ -/** - ****************************************************************************** - * @file stm32w108xx_clk.c - * @author MCD Application Team - * @version V1.0.1 - * @date 30-November-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the clock peripheral: - * + Internal/external clocks, - * + Modes management - * - * @verbatim - * - =============================================================================== - ##### CLK specific features ##### - =============================================================================== - [..] After reset the device is running from OSCHF (12 MHz) - - [..] Once the device started from reset, the user application has to: - (#) Configure the clock source to be used to drive the System clock - (#) Configure the System clock frequency: 24Mhz/12Mhz - (#) Configure the Flash clock frequency: 24Mhz/12Mhz/6Mhz - - - @endverbatim - * - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2012 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32w108xx_clk.h" - -/** @addtogroup STM32W108xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CLK - * @brief CLK driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -#define SLOWRC_PERIOD_SETTLE_TIME 4250 -#define SLOWRC_PERIOD_SAMPLES 8 -#define CLK1K_NUMERATOR 384000000 - -#define FASTRC_PERIOD_SETTLE_TIME 128 - -/* CLK_HSECR2 register Mask */ -#define CLK_HSECR2_Mask ((uint32_t)0x00000003) - -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup CLK_Private_Functions - * @{ - */ - -/** @defgroup CLK_Group1 Internal and external clocks - * @brief Internal and external clocks configuration functions - * -@verbatim - =============================================================================== - ##### Internal-external clocks configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to configure the internal/external clocks, - - (#) HSI (high-frequency RC oscillator (OSCHF)), is used as the default system clock - source when power is applied to the core domain. The nominal frequency coming - out of reset is 12 MHz. - (#) HSE (high-frequency crystal oscillator), 24 MHz crystal oscillator - -@endverbatim - * @{ - */ - -/** - * @brief Resets the CLOCK configuration to the default reset state. - * @note The default reset state of the clock configuration is given below: - * HSI ON and used as system clock source - * @param None - * @retval None - */ -void CLK_DeInit(void) -{ - CLK->SLEEPCR = 0x00000002; - CLK->LSI10KCR = 0x00000000; - CLK->LSI1KCR = 0x00005000; - CLK->HSECR1 = 0x0000000F; - CLK->HSICR = 0x00000017; - CLK->PERIODCR = 0x00000000; - CLK->DITHERCR = 0x00000000; - CLK->HSECR2 = 0x00000000; - CLK->CPUCR = 0x00000000; -} - -/** - * @brief Calibrate the low speed internal clock (LSI) to be close to 10KHZ in - * order to generate 1KHZ clock. - * @param None - * @retval None - */ -void CLK_InternalCalibrateLSI(void) -{ - uint8_t i = 0; - uint32_t average = 0; - int16_t delta = 0; - uint32_t period = 0; - __IO uint32_t StartUpCounter = 0; - __IO uint32_t LSI10KCR_RESET = 0x0, LSI1KCR_RESET = 0x5000; - - /* The slowest frequency for the 10kHz RC source is 8kHz (125us). The PERIODSR - register updates every 16 cycles, so to be safe 17 cycles = 2125us. But, - we need twice this maximum time because the period measurement runs - asynchronously, and the value of LSI10KCR is changed immediately before - the delay. - SLOWRC_PERIOD_SETTLE_TIME 4250 - The CLK_PERIOD register measures the number of 12MHz clock cycles that - occur in 16 cycles of the SlowRC clock. This is meant to smooth out the the - noise inherently present in the analog RC source. While these 16 cycles - smooths out most noise, there is still some jitter in the bottom bits of - PERIODSR. To further smooth out the noise, we take several readings of - PERIODSR and average them out. Testing has shown that the bottom 3 and 4 - bits of PERIODSR contain most of the jitter. Averaging 8 samples will - smooth out 3 bits of jitter and provide a realiable and stable reading useful - in the calculations, while taking much less time than 16 or 32 samples. - SLOWRC_PERIOD_SAMPLES 8 - The register LSI1KCR is a fractional divider that divides the 10kHz analog - source with the goal of generating a 1024Hz, clk1k output. - 10000Hz / LSI1KCR = 1024Hz. - Since the PERIODSR register measures the number of 12MHz cycles in 16 - cycles of the RC: - 16 * 12000000 - ------------- = ~10kHz - PERIODSR - and - ~10kHz / 1024 = X - where X is the fractional number that belongs in LSI1KCR. Since the - integer portion of LSI1KCR is bits 15:11 and the fractional is 10:0, - multiplying X by 2048 (bit shift left by 11) generates the proper LSI1KCR - register value. - - Putting this all together: - 16 * 12000000 * 2048 384000000 - -------------------- = ------------ = LSI1KCR - PERIODSR * 1024 PERIODSR - - CLK1K_NUMERATOR 384000000 */ - - /* ---- STEP 1: coarsely tune SlowRC in analog section to ~10kHz ---- */ - /* To operate properly across the full temperature and voltage range, - the RC source in the analog section needs to be first coarsely tuned - to 10kHz. The LSI10KCR register, which is 2's compliment, provides 16 - steps at ~400Hz per step yielding approximate frequences of 8kHz at 7 - and 15kHz at -8. */ - /* Start with our reset values for TUNE and CAL */ - CLK->PERIODCR = 0; /* measure SlowRC */ - CLK->LSI10KCR = LSI10KCR_RESET; - CLK->LSI1KCR = LSI1KCR_RESET; - - /* wait for the PERIODSR register to properly update */ - do - { - StartUpCounter++; - } while(StartUpCounter != SLOWRC_PERIOD_SETTLE_TIME); - - /* Measure the current PERIODSR to obtain a baseline - For 10kHz, the ideal PERIODSR value is 19200. Calculate the PERIOD delta. - It's possible for a chip's 10kHz source RC to be too far out of range - for the LSI10KCR to bring it back to 10kHz. Therefore, we have to - ensure that our delta correction does not exceed the tune range so - tune has to be capped to the end of the vailable range so it does not - wrap. Even if we cannot achieve 10kHz, the 1kHz calibration can still - properly correct to 1kHz. - Each LSI10KCR step yields a PERIODSR delta of *approximately* 800. - Calculate how many steps we are off. While dividing by 800 may seem - like an ugly calculation, the precision of the result is worth the small - bit of code and time needed to do a divide. */ - period = CLK->PERIODSR; - - /* Round to the nearest integer */ - delta = (19200+400) - period; - delta /= 800; - - /* LSI10KCR is a 4 bit signed number. cap the delta to 7/-8 */ - if(delta > 7) { - delta = 7; - } - if(delta < -8) { - delta = -8; - } - CLK->LSI10KCR = delta; - - /* Wait for PERIOD to update before taking another sample */ - StartUpCounter = 0; - do - { - StartUpCounter++; - } while(StartUpCounter != SLOWRC_PERIOD_SETTLE_TIME); - - /* The analog section should now be producing an output of ~10kHz */ - - /* ---- STEP 2: fine tune the SlowRC to 1024Hz ---- */ - /* Our goal is to generate a 1024Hz source. The register LSI1KCR is a - fractional divider that divides the 10kHz analog source and generates - the clk1k output. At reset, the default value is 0x5000 which yields a - division of 10.000. By averaging several samples of CLK_PERIOD, we - can then calculate the proper divisor need for LSI1KCR to make 1024Hz. */ - for(i=0;iPERIODSR; - } - - /* Calculate the average, with proper rounding */ - average = (average+(SLOWRC_PERIOD_SAMPLES/2))/SLOWRC_PERIOD_SAMPLES; - - /* Using an average period sample, calculate the clk1k divisor */ - CLK->LSI1KCR = (uint16_t)(CLK1K_NUMERATOR/average); - - /* The SlowRC timer is now producing a 1024Hz tick (+/-2Hz). */ -} - -/** - * @brief Calibrate the high speed internal clock (HSI) to be close to 12MHZ. - * @note To calibrate the HSI, the high speed external clock (HSE) must be the - * system clock. - * @param None - * @retval None - */ -void CLK_InternalCalibrateHSI(void) -{ - __IO uint32_t StartUpCounter = 0, CLK_PERIOD = 0; - __IO int32_t newTune = -16; - /* ---- coarsely tune FastRC in analog section to ~12MHz ---- */ - /* The slowest frequency for the FastRC source is 4MHz (250ns). The PERIODSR - register updates every 256 cycles, so to be safe 257 cycles = 64us. But, - we need twice this maximum time because the period measurement runs - asynchronously, and the value of HSICR1 is changed immediately before - the delay. - The CLK_PERIODSR register measures the number of 12MHz cycles in 256 - cycles of OSCHF: - - 256 * 12000000 - ------------- = ~12MHz - CLK_PERIOD - - The RC source in the analog section needs to be coarsely tuned - to 12MHz. The HSICR1 register, which is 2's compliment, provides 32 - steps at ~0.5MHz per step yielding approximate frequences of 4MHz at 15 - and 20MHz at -16. */ - - CLK->PERIODCR = 1; /* Measure FastRC */ - - /* Start at the fastest possible frequency */ - CLK->HSICR = newTune; - - /* Wait for the PERIOD register to properly update */ - do - { - StartUpCounter++; - } while(StartUpCounter != FASTRC_PERIOD_SETTLE_TIME); - - /* For 12MHz, the ideal CLK_PERIOD is 256. Tune the frequency down until - the period is <= 256, which says the frequency is as close to 12MHz as - possible (without going over 12MHz) - Start at the fastest possible frequency (-16) and increase to the slowest - possible (15). When CLK_PERIOD is <=256 or we run out of tune values, - we're done. */ - for(;newTune<16;newTune++) - { - StartUpCounter = 0; - /* Decrease frequency by one step (by increasing tune value) */ - CLK->HSICR = newTune; - - /* Wait for the PERIOD register to properly update */ - do - { - StartUpCounter++; - } while(StartUpCounter != FASTRC_PERIOD_SETTLE_TIME); - - /* Kickout if we're tuned */ - CLK_PERIOD = CLK->PERIODSR; - if(CLK_PERIOD >= 256) { - break; - } - } - /* The analog section should now be producing an output of 11.5MHz - 12.0MHz */ -} - -/** - * @brief Configures the clock mode to use: - * @param MODE: specifies the frequency mode to use. - * This parameter can be one of the following values: - * @arg MODE0: Normal CPU, SCLK =12MHZ, PCLK=6MHZ, Flash Program/Erase Inactive =6Mhz, - * FlashProgram/Erase Active = 12Mhz. - * @arg MODE1: Fast CPU, SCLK =12MHZ, PCLK=6MHZ, Flash Program/Erase Inactive =12Mhz, - * FlashProgram/Erase Active = 12Mhz. - * @arg MODE2: Normal CPU, SCLK =24MHZ, PCLK=12MHZ, Flash Program/Erase Inactive =12Mhz, - * FlashProgram/Erase Active = 12Mhz. - * @arg MODE3: Fast CPU, SCLK =24MHZ, PCLK=12MHZ, Flash Program/Erase Inactive =24Mhz, - * FlashProgram/Erase Active = 12Mhz. - * @retval None - */ -void CLK_Config(uint8_t MODE) -{ - __IO uint32_t StartUpCounter = 0; - - /* Check the parameters */ - assert_param(IS_CLK_MODE(MODE)); - - switch (MODE) - { - case CLK_MODE0: /* HSI used as system clock : Normal CPU*/ - CLK->HSECR2 &= ~CLK_HSECR2_SW1; - CLK->CPUCR &= ~CLK_CPUCR_SW2; - break; - - case CLK_MODE1: /* HSI used as system clock : Fast CPU */ - CLK->HSECR2 &= ~CLK_HSECR2_SW1; - CLK->CPUCR |= CLK_CPUCR_SW2; - break; - - case CLK_MODE2: /* HSE used as system clock : Normal CPU*/ - /* Enable HSE */ - CLK->HSECR2 |= CLK_HSECR2_EN; - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - StartUpCounter++; - } while(StartUpCounter != HSE_STARTUP_TIMEOUT); - - CLK->HSECR2 |= CLK_HSECR2_SW1; - CLK->CPUCR &= ~CLK_CPUCR_SW2; - break; - - case CLK_MODE3: /* HSE used as system clock : Fast CPU*/ - /* Enable HSE */ - CLK->HSECR2 |= CLK_HSECR2_EN; - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - StartUpCounter++; - } while(StartUpCounter != HSE_STARTUP_TIMEOUT); - - CLK->HSECR2 |= CLK_HSECR2_SW1; - CLK->CPUCR |= CLK_CPUCR_SW2; - break; - default: /* HSI used as system clock */ - CLK->HSECR2 &= ~CLK_HSECR2_SW1; - CLK->CPUCR &= ~CLK_CPUCR_SW2; - break; - } -} - -/** - * @brief Enables or disables the External High Speed oscillator (HSE). - * @note After enabling HSE the user should wait for HSE_STARTUP_TIMEOUT - * @note to be sure that the clok is stabilized. - * @param NewState: new state of the HSE. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CLK_HSECmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - CLK->HSECR2 |= CLK_HSECR2_EN; - } - else - { - CLK->HSECR2 = 0x00; - } -} - -/** - * @brief Enables or disables the specified SLPTIM clock. - * @param CLK_SLPTIM: specifies the SLPTIM clock to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg SLPTIM_CLK_32KH: 32kHz external XTAL - * @arg SLPTIM_CLK_10KH: 10kHz internal RC (during deep sleep) - * @param NewState: new state of the SLPTIM clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CLK_SLPTIMClockConfig(uint32_t CLK_SLPTIM, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SLPTIM_GET_CLK(CLK_SLPTIM)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - if (CLK_SLPTIM == SLPTIM_CLK_32KH) - { - CLK->SLEEPCR &= 0x0; - } - /* Enable the clock */ - CLK->SLEEPCR |= (uint32_t)CLK_SLPTIM; - } - else - { - /* Disable the clock */ - CLK->SLEEPCR &= (uint32_t)~CLK_SLPTIM; - } -} - -/** - * @brief Calibration of CLK1K clock. - * @param CALINT: specifies the divider value integer portion. - * This parameter can be a value between 0x0 and 0x1F. - * @param CALFRAC: specifies the divider value fractional portion. - * This parameter can be a value between 0x0 and 0x7FF. - * @retval None. - */ -void CLK_1KClockCalibration(uint32_t CALINT, uint32_t CALFRAC) -{ - uint32_t tmpclk1k; - /* Check the parameters */ - assert_param(IS_LSI1KCRINT(CALINT)); - assert_param(IS_LSI1KCRFRAC(CALFRAC)); - - CLK->LSI1KCR = 0x00000000; - - /* set the divider value integer portion */ - tmpclk1k = (uint32_t)(CALINT <<11); - - /* set the divider value fractional portion */ - tmpclk1k |= CALFRAC; - - CLK->LSI1KCR = tmpclk1k; -} - -/** - * @brief Set tune value for CLKRC clock. - * @param TUNE_VALUE: specifies the tune value for CLKRC clock. - * This parameter can be a value between 0x0 and 0xF. - * @retval None. - */ -void CLK_RCTuneConfig(uint32_t TUNE_VALUE) -{ - /* Check the parameters */ - assert_param(IS_CLK_TUNE_VALUE(TUNE_VALUE)); - - CLK->LSI10KCR = 0x00000000; - - /* set the tune value for CLKRC */ - CLK->LSI10KCR = TUNE_VALUE; -} - -/** - * @brief Select the clock period to be measured. - * @param CLK_MEASURED: specifies the clock for which the period will be measured. - * This parameter can be : - * @arg MEASURE_CLKRC: Measure CLKRC. - * @arg MEASURE_OSCHF: Measure OSCHF. - * @arg MEASURE_TUNEFILT: Measure TUNE_FILTER_RESULT. - * @retval None. - */ -void CLK_MeasurePeriod(uint32_t CLK_MEASURED) -{ - /* Check the parameters */ - assert_param(IS_CLK_MEASURE(CLK_MEASURED)); - - CLK->PERIODCR = CLK_MEASURED; -} - -/** - * @brief Returns the clock period measured depend on clock selected. - *@note measured period is equal to: - * 16 x Clock period in clk12m cycles (CLKRC/TUNE_FILTER_RESULT modes) - * 256 x clock period in clk12m cycles (OSCHF mode) - * @param None. - * @retval None. - */ -uint32_t CLK_GetMeasurePeriod(void) -{ - return CLK->PERIODSR; -} - -/** - * @brief Returns the clock source used as system clock. - * @param None - * @retval The clock source used as system clock. The returned value can - * be one of the following: - * - 0x00,0x01,0x10: HSI used as system clock - * - 0x03: HSE used as system clock - */ -uint32_t CLK_GetClocksFreq(void) -{ - uint32_t tmp = 0; - uint32_t clockvalue = 0; - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = CLK->HSECR2 & CLK_HSECR2_Mask; - - switch (tmp) - { - case 0x00: - case 0x02: /* HSI used as system clock */ - clockvalue = (uint32_t)HSI_VALUE; - break; - case 0x03: /* HSE used as system clock */ - clockvalue = (uint32_t)HSE_VALUE; - break; - - default: /* HSI used as system clock */ - clockvalue = (uint32_t)HSI_VALUE; - break; - } - return clockvalue; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_exti.c b/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_exti.c deleted file mode 100644 index e080135..0000000 --- a/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_exti.c +++ /dev/null @@ -1,238 +0,0 @@ -/** - ****************************************************************************** - * @file stm32w108xx_exti.c - * @author MCD Application Team - * @version V1.0.1 - * @date 30-November-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the EXTI peripheral: - * + Initialization and Configuration - * + Interrupts and flags management - * - * @verbatim - * - ============================================================================== - ##### EXTI features ##### - ============================================================================== - [..] External interrupt/event lines are mapped as following: - (#) All available GPIO pins are connected to the 4 external - interrupt/event lines from EXTIA to EXTID. - (#) EXTIA and EXTIB have fixed pins assignement (PB0 and PB6). - (#) EXTIC and EXTID can use any GPIO pin. - - ##### How to use this driver ##### - ============================================================================== - [..] In order to use an I/O pin as an external interrupt source, follow - steps below: - (#) Configure the I/O in input mode using GPIO_Init() - (#) Select the mode(interrupt, event) and configure the trigger selection - using EXTI_Init(). - (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init(). - - @endverbatim - * - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2012 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32w108xx_exti.h" - -/** @addtogroup STM32W108xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup EXTI - * @brief EXTI driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - - -/** @defgroup EXTI_Private_Functions - * @{ - */ - -/** @defgroup EXTI_Group1 EXTI Initialization and Configuration - * @brief Initialization and Configuration of External Interrupt - * -@verbatim - =============================================================================== - EXTI Initialization and Configuration - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the EXTI_IRQn line registers to their default reset values. - * @param None - * @retval None - */ -void EXTI_DeInit(void) -{ - uint8_t i; - EXTI->PR = 0x00000000; - EXTI->CR[0] = 0x0000000F; - EXTI->CR[1] = 0x00000010; - for (i=0; i<4; i++) - { - EXTI->TSR[i] = 0x00000000; - } -} - - -/** - * @brief Initializes the EXTI peripheral according to the specified - * parameters in the EXTI_InitStruct. - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure - * that contains the configuration information for the EXTI peripheral. - * @retval None - */ -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) -{ - /* Check the parameters */ - assert_param(IS_EXTI_SOURCE(EXTI_InitStruct->EXTI_Source)); - assert_param(IS_EXTI_IRQ(EXTI_InitStruct->EXTI_IRQn)); - assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); - assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); - assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_DigitalFilterCmd)); - - if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) - { - /* Clear Rising Falling edge configuration */ - EXTI->TSR[(uint32_t)(EXTI_InitStruct->EXTI_IRQn & 0x000000F0) >>4] &= (uint32_t)(~EXTI_TSR_INTMOD); - - /* Rising Falling edge */ - EXTI->TSR[(uint32_t)(EXTI_InitStruct->EXTI_IRQn & 0x000000F0) >>4] |= (uint32_t)(EXTI_InitStruct->EXTI_Trigger); - } - else - { - EXTI->TSR[(uint32_t)(EXTI_InitStruct->EXTI_IRQn & 0x000000F0) >>4] &= (uint32_t)(~EXTI_TSR_INTMOD); - } - - if (EXTI_InitStruct->EXTI_DigitalFilterCmd != DISABLE) - { - /* Set the EXTI_TSR_FILTEN bit to Enable degital filtering on the EXTI_IRQn */ - EXTI->TSR[(uint32_t)(EXTI_InitStruct->EXTI_IRQn & 0x000000F0) >>4] |= (uint32_t)EXTI_TSR_FILTEN; - - } - else - { - /* Clear the EXTI_TSR_FILTEN bit to disable degital filtering on the EXTI_IRQn */ - EXTI->TSR[(uint32_t)(EXTI_InitStruct->EXTI_IRQn & 0x000000F0) >>4] &= (uint32_t)~EXTI_TSR_FILTEN; - } - - /* Connect The EXTI_PinSource to the EXTI_IRQn handler */ - if ((EXTI_InitStruct->EXTI_IRQn == EXTI_IRQC) || (EXTI_InitStruct->EXTI_IRQn == EXTI_IRQD)) - { - EXTI->CR[(uint32_t)(EXTI_InitStruct->EXTI_IRQn & 0x0000000F)] &= 0x00000000; - EXTI->CR[(uint32_t)(EXTI_InitStruct->EXTI_IRQn & 0x0000000F)] |= (uint32_t)(EXTI_InitStruct->EXTI_Source); - } - else - {} -} - -/** - * @brief Fills each EXTI_InitStruct member with its reset value. - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) -{ - EXTI_InitStruct->EXTI_Source = EXTI_SourcePB0; - EXTI_InitStruct->EXTI_IRQn = EXTI_IRQA; - EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Disable; - EXTI_InitStruct->EXTI_LineCmd = DISABLE; - EXTI_InitStruct->EXTI_DigitalFilterCmd = DISABLE; -} - -/** @defgroup EXTI_Group2 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - ============================================================================== - ##### Interrupts and flags management functions ##### - ============================================================================== -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the specified EXTI line is asserted or not. - * @param EXTI_IRQn: specifies the EXTI line to check. - * This parameter can be: - * EXTI_IRQn: External interrupt line n where x(A, B, C or D). - * @retval The new state of EXTI_IRQn (SET or RESET). - */ -ITStatus EXTI_GetITStatus(uint32_t EXTI_IRQn) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_EXTI_IRQ(EXTI_IRQn)); - if ((EXTI->PR & (uint32_t)(1<< ((uint32_t)(EXTI_IRQn & 0x000000F0) >>4))) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the EXTI's line pending bits. - * @param EXTI_IRQn: specifies the EXTI lines to clear. - * This parameter can be any combination of EXTI_IRQn where n can be (A, B, C or D). - * @retval None - */ -void EXTI_ClearITPendingBit(uint32_t EXTI_IRQn) -{ - /* Check the parameters */ - assert_param(IS_EXTI_IRQ(EXTI_IRQn)); - - EXTI->PR = (uint32_t)(1<< ((EXTI_IRQn & 0x000000F0) >>4)); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_flash.c b/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_flash.c deleted file mode 100644 index 9a5fd08..0000000 --- a/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_flash.c +++ /dev/null @@ -1,925 +0,0 @@ -/** - ****************************************************************************** - * @file stm32w108xx_flash.c - * @author MCD Application Team - * @version V1.0.1 - * @date 30-November-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the FLASH peripheral: - * + FLASH Interface configuration - * + FLASH Memory Programming - * + Option Bytes Programming - * + Interrupts and flags management - * - * @verbatim - * - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] This driver provides functions to configure and program the Flash - memory of all STM32W108xx devices. These functions are split in 4 groups - (#) FLASH Interface configuration functions: this group includes the - management of following features: - (++) Set the latency - (++) Enable/Disable the prefetch buffer - - (#) FLASH Memory Programming functions: this group includes all needed - functions to erase and program the main memory: - (++) Lock and Unlock the Flash interface. - (++) Erase function: Erase Page, erase all pages. - (++) Program functions: Half Word and Word write. - - (#) FLASH Option Bytes Programming functions: this group includes all - needed functions to: - (++) Set/Reset the write protection - (++) Set the Read protection Level - (++) Get the Write protection - (++) Get the read protection status - - (#) FLASH Interrupts and flag management functions: this group includes - all needed functions to: - (++) Enable/Disable the flash interrupt sources - (++) Get flags status - (++) Clear flags - (++) Get Flash operation status - (++) Wait for last flash operation - - @endverbatim - * - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2012 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32w108xx_flash.h" - -/** @addtogroup STM32W108xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup FLASH - * @brief FLASH driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* Flash Access Control Register bits */ -#define ACR_LATENCY_Mask ((uint32_t)0x00000038) -#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7) -#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF) - -/* Flash Access Control Register bits */ -#define ACR_PRFTBS_Mask ((uint32_t)0x00000020) - -/* Flash Control Register bits */ -#define CR_PG_Set ((uint32_t)0x00000001) -#define CR_PG_Reset ((uint32_t)0x00001FFE) -#define CR_PER_Set ((uint32_t)0x00000002) -#define CR_PER_Reset ((uint32_t)0x00001FFD) -#define CR_MER_Set ((uint32_t)0x00000004) -#define CR_MER_Reset ((uint32_t)0x00001FFB) -#define CR_OPTPG_Set ((uint32_t)0x00000010) -#define CR_OPTPG_Reset ((uint32_t)0x00001FEF) -#define CR_OPTER_Set ((uint32_t)0x00000020) -#define CR_OPTER_Reset ((uint32_t)0x00001FDF) -#define CR_STRT_Set ((uint32_t)0x00000040) -#define CR_LOCK_Set ((uint32_t)0x00000080) - -/* FLASH Mask */ -#define RDPRT_Mask ((uint32_t)0x00000002) -#define WRP0_Mask ((uint32_t)0x000000FF) -#define WRP1_Mask ((uint32_t)0x0000FF00) -#define WRP2_Mask ((uint32_t)0x00FF0000) -#define WRP3_Mask ((uint32_t)0xFF000000) - -/* FLASH Keys */ -#define RDP_Key ((uint16_t)0x00A5) -#define FLASH_KEY1 ((uint32_t)0x45670123) -#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) - -/* Delay definition */ -#define EraseTimeout ((uint32_t)0x000B0000) -#define ProgramTimeout ((uint32_t)0x00002000) -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - - -/** @defgroup FLASH_Private_Functions - * @{ - */ - -/** -@code - - This driver provides functions to configure and program the Flash memory of all STM32W108xx devices. - - STM32W108xx devices features only one bank with memory up to 256 Kbytes. - -@endcode -*/ - -/** @defgroup FLASH_Group1 FLASH Interface configuration functions - * @brief FLASH Interface configuration functions - * -@verbatim - =============================================================================== - ##### FLASH Interface configuration functions ##### - =============================================================================== - - [..] FLASH_Interface configuration_Functions, includes the following functions: - (+) void FLASH_SetLatency(uint32_t FLASH_Latency): - [..] To correctly read data from Flash memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock (SCLK) - (+) FlagStatus FLASH_GetPrefetchBufferStatus(void); - (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState); - [..] - All these functions don't need the unlock sequence. - -@endverbatim - * @{ - */ - -/** - * @brief Sets the code latency value. - * @param FLASH_Latency: specifies the FLASH Latency value. - * This parameter can be one of the following values: - * @arg FLASH_Latency_0: FLASH Zero Latency cycle - * @arg FLASH_Latency_1: FLASH One Latency cycle - * @arg FLASH_Latency_2: FLASH Two Latency cycles - * @retval None - */ -void FLASH_SetLatency(uint32_t FLASH_Latency) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_FLASH_LATENCY(FLASH_Latency)); - - /* Read the ACR register */ - tmpreg = FLASH->ACR; - - /* Sets the Latency value */ - tmpreg &= ACR_LATENCY_Mask; - tmpreg |= FLASH_Latency; - - /* Write the ACR register */ - FLASH->ACR = tmpreg; -} - -/** - * @brief Checks whether the FLASH Prefetch Buffer status is set or not. - * @param None - * @retval FLASH Prefetch Buffer Status (SET or RESET). - */ -FlagStatus FLASH_GetPrefetchBufferStatus(void) -{ - FlagStatus bitstatus = RESET; - - if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */ - return bitstatus; -} - -/** - * @brief Enables or disables the Prefetch Buffer. - * @param FLASH_PrefetchBuffer: specifies the Prefetch buffer status. - * This parameter can be one of the following values: - * @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable - * @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable - * @retval None - */ -void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer) -{ - /* Check the parameters */ - assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer)); - - /* Enable or disable the Prefetch Buffer */ - FLASH->ACR &= ACR_PRFTBE_Mask; - FLASH->ACR |= FLASH_PrefetchBuffer; -} -/** - * @} - */ -/** @defgroup FLASH_Group2 FLASH Memory Programming functions - * @brief FLASH Memory Programming functions - * -@verbatim - =============================================================================== - ##### FLASH Memory Programming functions ##### - =============================================================================== - - [..] The FLASH Memory Programming functions, includes the following functions: - (+) void FPEC_ClockCmd(FunctionalState NewState) - (+) void FLASH_Unlock(void); - (+) void FLASH_Lock(void); - (+) void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess) - (+) FLASH_Status FLASH_ErasePage(uint32_t Page_Address); - (+) FLASH_Status FLASH_EraseAllPages(void); - (+) FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); - (+) FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); - - [..] Any operation of erase or program should follow these steps: - - (#) Call the FPEC_ClockCmd() function to enable/disable the flash control - register and enable/disable flash clock. - (#) Call the desired function to erase page or program data. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the FPEC clock. - * @param NewState: new state of the FPEC clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void FPEC_ClockCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - - if (NewState != DISABLE) - { - /* Unlock the FPEC */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; - /* Unlock the Option bytes write enable (OPTWRE) */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - - /* Enable the FPEC Clock */ - FLASH->CLKER |= (uint32_t)FLASH_CLKER_EN; - - /* Verifying that the FPEC clock is running before proceeding */ - while( (FLASH->CLKSR&FLASH_CLKSR_ACK) != FLASH_CLKSR_ACK) - {} - - /* Wait until the flash is no longer busy */ - while( (FLASH->SR&FLASH_SR_BSY) == (uint32_t)FLASH_SR_BSY ) - {} - } - else - { - /* Verifying the FPEC is completely idle before turning off the clock */ - while( (FLASH->CLKSR&FLASH_CLKSR_BSY) == FLASH_CLKSR_BSY) - {} - /* Disable the FPEC Clock */ - FLASH->CLKER &= (uint32_t)~FLASH_CLKER_EN; - /* Set the Lock Bit to lock the FPEC and the CR of flash */ - FLASH->CR |= (uint32_t)FLASH_CR_LOCK; - } -} - -/** - * @brief Unlocks the FLASH Program Erase Controller. - * @param None - * @retval None - */ -void FLASH_Unlock(void) -{ - /* Unlock the FPEC */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; -} - -/** - * @brief Locks the FLASH Program Erase Controller. - * @param None - * @retval None - */ -void FLASH_Lock(void) -{ - /* Set the Lock Bit to lock the FPEC and the CR of flash */ - FLASH->CR |= CR_LOCK_Set; - -} - -/** - * @brief Enables or disables the Half cycle flash access. - * @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode. - * This parameter can be one of the following values: - * @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable - * @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable - * @retval None - */ -void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess) -{ - /* Check the parameters */ - assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess)); - - /* Enable or disable the Half cycle access */ - FLASH->ACR &= ACR_HLFCYA_Mask; - FLASH->ACR |= FLASH_HalfCycleAccess; -} - -/** - * @brief Erases a specified FLASH page. - * @param Page_Address: The page address to be erased. - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ErasePage(uint32_t Page_Address) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Page_Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase the page */ - FLASH->CR|= CR_PER_Set; - FLASH->AR = Page_Address; - FLASH->CR|= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - - /* Disable the PER Bit */ - FLASH->CR &= CR_PER_Reset; - } - /* Return the Erase Status */ - return status; -} - -/** - * @brief Erases all FLASH pages. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseAllPages(void) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all pages */ - FLASH->CR |= CR_MER_Set; - FLASH->CR |= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - - /* Disable the MER Bit */ - FLASH->CR &= CR_MER_Reset; - } - /* Return the Erase Status */ - return status; -} - -/** - * @brief Programs a word at a specified address. - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new first - half word */ - FLASH->CR |= CR_PG_Set; - - *(__IO uint16_t*)Address = (uint16_t)Data; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new second - half word */ - tmp = Address + 2; - - *(__IO uint16_t*) tmp = Data >> 16; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - else - { - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - } - /* Return the Program Status */ - return status; -} - -/** - * @brief Programs a half word at a specified address. - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR |= CR_PG_Set; - - *(__IO uint16_t*)Address = Data; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - /* Return the Program Status */ - return status; -} - -/** - * @} - */ - -/** @defgroup FLASH_Group3 Option Bytes Programming functions - * @brief Option Bytes Programming functions - * -@verbatim - =============================================================================== - ##### Option Bytes Programming functions ##### - =============================================================================== - - [..] The FLASH_Option Bytes Programming_functions, includes the following functions: - (+) FLASH_Status FLASH_EraseOptionBytes(void); - (+) FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); - (+) FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); - (+) uint32_t FLASH_GetWriteProtectionOptionByte(void); - (+) FlagStatus FLASH_GetReadOutProtectionStatus(void); - -@endverbatim - * @{ - */ - -/** - * @brief Erases the FLASH option bytes. - * @note This functions erases all option bytes except the Read protection (RDP). - * @param None - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseOptionBytes(void) -{ - uint16_t rdptmp = RDP_Key; - - FLASH_Status status = FLASH_COMPLETE; - - /* Get the actual read protection Option Byte value */ - if(FLASH_GetReadOutProtectionStatus() != RESET) - { - rdptmp = 0x00; - } - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - /* Authorize the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - - /* if the previous operation is completed, proceed to erase the option bytes */ - FLASH->CR |= CR_OPTER_Set; - FLASH->CR |= CR_STRT_Set; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the erase operation is completed, disable the OPTER Bit */ - FLASH->CR &= CR_OPTER_Reset; - - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= CR_OPTPG_Set; - /* Restore the last read protection Option Byte value */ - OB->RDP = (uint16_t)rdptmp; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - else - { - if (status != FLASH_TIMEOUT) - { - /* Disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - } - /* Return the erase status */ - return status; -} - -/** - * @brief Write protects the desired pages - * @param FLASH_Pages: specifies the address of the pages to be write protected. - * This parameter can be: - * @arg For @b STM32W_Low-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages60to63. - * @arg For @b STM32W_Medium-density_devices: value between FLASH_WRProt_Pages0to3 - * and FLASH_WRProt_Pages124to127. - * @arg For @b STM32W_High-density_devices: value between FLASH_WRProt_Pages0to1 and - * FLASH_WRProt_Pages126to127. - * @arg For @b STM32W_Connectivity_line_devices: value between FLASH_WRProt_Pages0to1 and - * FLASH_WRProt_Pages94to95. - * @arg FLASH_WRProt_AllPages - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages) -{ - uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; - - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages)); - - FLASH_Pages = (uint32_t)(~FLASH_Pages); - WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask); - WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8); - WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16); - WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* Authorizes the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - FLASH->CR |= CR_OPTPG_Set; - if(WRP0_Data != 0xFF) - { - OB->WRP0 = WRP0_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - } - if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF)) - { - OB->WRP1 = WRP1_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - } - if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF)) - { - OB->WRP2 = WRP2_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - } - - if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF)) - { - OB->WRP3 = WRP3_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - } - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - /* Return the write protection operation Status */ - return status; -} - -/** - * @brief Enables or disables the read out protection. - * @param NewState : new state of the ReadOut Protection. - * This parameter can be: ENABLE or DISABLE. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - /* Authorizes the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - FLASH->CR |= CR_OPTER_Set; - FLASH->CR |= CR_STRT_Set; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - /* if the erase operation is completed, disable the OPTER Bit */ - FLASH->CR &= CR_OPTER_Reset; - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= CR_OPTPG_Set; - if(NewState != DISABLE) - { - OB->RDP = 0x00; - } - else - { - OB->RDP = RDP_Key; - } - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - else - { - if(status != FLASH_TIMEOUT) - { - /* Disable the OPTER Bit */ - FLASH->CR &= CR_OPTER_Reset; - } - } - } - /* Return the protection operation Status */ - return status; -} - -/** - * @brief Returns the FLASH Write Protection Option Bytes Register value. - * @param None - * @retval The FLASH Write Protection Option Bytes Register value - */ -uint32_t FLASH_GetWriteProtectionOptionByte(void) -{ - /* Return the Flash write protection Register value */ - return (uint32_t)(FLASH->WRPR); -} - -/** - * @brief Checks whether the FLASH Read Out Protection Status is set or not. - * @param None - * @retval FLASH ReadOut Protection Status(SET or RESET) - */ -FlagStatus FLASH_GetReadOutProtectionStatus(void) -{ - FlagStatus readoutstatus = RESET; - if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) - { - readoutstatus = SET; - } - else - { - readoutstatus = RESET; - } - return readoutstatus; -} - -/** - * @} - */ - -/** @defgroup FLASH_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ -/** - * @brief Enables or disables the specified FLASH interrupts. - * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg FLASH_IT_ERROR: FLASH Error Interrupt - * @arg FLASH_IT_EOP: FLASH end of operation Interrupt - * @param NewState: new state of the specified Flash interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) -{ - - /* Check the parameters */ - assert_param(IS_FLASH_IT(FLASH_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - /* Enable the interrupt sources */ - FLASH->CR |= FLASH_IT; - } - else - { - /* Disable the interrupt sources */ - FLASH->CR &= ~(uint32_t)FLASH_IT; - } -} - -/** - * @brief Checks whether the specified FLASH flag is set or not. - * @param FLASH_FLAG: specifies the FLASH flag to check. - * This parameter can be one of the following values: - * @arg FLASH_FLAG_BSY: FLASH Busy flag - * @arg FLASH_FLAG_PGERR: FLASH Program error flag - * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @arg FLASH_FLAG_OPTERR: FLASH Option Byte error flag - * @retval The new state of FLASH_FLAG (SET or RESET). - */ -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ; - if(FLASH_FLAG == FLASH_FLAG_OPTERR) - { - if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else - { - if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - /* Return the new state of FLASH_FLAG (SET or RESET) */ - return bitstatus; -} - -/** - * @brief Clears the FLASH's pending flags. - * @param FLASH_FLAG: specifies the FLASH flags to clear. - * This parameter can be any combination of the following values: - * @arg FLASH_FLAG_PGERR: FLASH Program error flag - * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @retval None - */ -void FLASH_ClearFlag(uint32_t FLASH_FLAG) -{ - /* Check the parameters */ - assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ; - - /* Clear the flags */ - FLASH->SR = FLASH_FLAG; -} - -/** - * @brief Returns the FLASH Status. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE - */ -FLASH_Status FLASH_GetStatus(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->SR & FLASH_FLAG_PGERR) != 0) - { - flashstatus = FLASH_ERROR_PG; - } - else - { - if((FLASH->SR & FLASH_FLAG_WRPRTERR) != 0 ) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - } - /* Return the Flash Status */ - return flashstatus; -} - -/** - * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. - * @param Timeout: FLASH programming Timeout - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check for the Flash Status */ - status = FLASH_GetStatus(); - /* Wait for a Flash operation to complete or a TIMEOUT to occur */ - while((status == FLASH_BUSY) && (Timeout != 0x00)) - { - status = FLASH_GetStatus(); - Timeout--; - } - if(Timeout == 0x00 ) - { - status = FLASH_TIMEOUT; - } - /* Return the operation status */ - return status; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_gpio.c b/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_gpio.c deleted file mode 100644 index 99f2d38..0000000 --- a/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_gpio.c +++ /dev/null @@ -1,504 +0,0 @@ -/** - ****************************************************************************** - * @file stm32w108xx_gpio.c - * @author MCD Application Team - * @version V1.0.1 - * @date 30-November-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the GPIO peripheral: - * + Initialization and Configuration - * + GPIO Read and Write - * @verbatim - * -================================================================================ - ##### How to use this driver ##### -================================================================================ - [..] - (#) Configure the GPIO pin(s) using GPIO_Init(). - Four possible configuration are available for each pin: - (++) Input: Floating, Pull-up, Pull-down. - (++) Output: Push-Pull (Pull-up, Pull-down or no Pull) - Open Drain (Pull-up, Pull-down or no Pull). - (++) Alternate Function: Push-Pull (PP or SPI mode) - Open Drain (Pull-up, Pull-down or no Pull). - (++) Analog - - (#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit() - (#) To set/reset the level of a pin configured in output mode use - GPIO_SetBits()/GPIO_ResetBits() - (#) During and just after reset, the alternate functions are not active and - the GPIO pins are configured in input floating mode (except JTAG pins). - (#) A full chip reset affects the GPIO configuration as follows: - (++) All pins are configured as floating inputs. - (++) The GPIO_EXTREGEN bit is set which overrides the normal configuration for PA7. - (++) The GPIO_DBGDIS bit is cleared, allowing Serial Wire/JTAG access - to override the normal configuration of PC0, PC2, PC3, and PC4. - - @endverbatim - * - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2012 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32w108xx_gpio.h" - -/** @addtogroup STM32W108xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup GPIO - * @brief GPIO driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - - -/** @defgroup GPIO_Private_Functions - * @{ - */ - -/** @defgroup GPIO_Group1 Initialization and Configuration - * @brief Initialization and Configuration - * -@verbatim - =============================================================================== - Initialization and Configuration - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the GPIOx peripheral registers to their default reset values. - * @param GPIOx: where x can be (A..C) to select the GPIO peripheral. - * @retval None - */ -void GPIO_DeInit(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - GPIOx->CRL = 0x00004444; - GPIOx->CRH = 0x00004444; - GPIOx->IDR = 0x00000000; - GPIOx->ODR = 0x00000000; - GPIOx->BSR = 0x00000000; - GPIOx->BRR = 0x00000000; - - GPIO_DBG->PCTRACECR = 0x00000000; - GPIO_DBG->DBGCR = 0x00000010; -} - -/** - * @brief Initializes the GPIOx peripheral according to the specified - * parameters in the GPIO_InitStruct. - * @param GPIOx: where x can be (A, B or C) to select the GPIO peripheral. - * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that - * contains the configuration information for the specified GPIO - * peripheral. - * GPIO_Pin: selects the pin to be configured: GPIO_Pin_0 -> GPIO_Pin_7 - * GPIO_Mode: selects the mode of the pin: - * - GPIO Analog Mode: GPIO_Mode_AN - * - GPIO Output Mode PP: GPIO_Mode_OUT_PP - * - GPIO Input Mode NOPULL: GPIO_Mode_IN - * - GPIO Output Mode OD: GPIO_Mode_OUT_OD - * - GPIO Input Mode PuPd: GPIO_Mode_IN_PUD - * - GPIO Alternate function Mode PP: GPIO_Mode_AF_PP - * - GPIO Alternate function Mode SPI SCLK PP: GPIO_Mode_AF_PP_SPI - * - GPIO Alternate function Mode OD: GPIO_Mode_AF_OD - * @retval None - */ -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) -{ - uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; - uint32_t tmpreg = 0x00, pinmask = 0x00; - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); - assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); - - /*---------------------------- GPIO Mode Configuration -----------------------*/ - currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); - - /*---------------------------- GPIO CRL Configuration ------------------------*/ - /* Configure the four low port pins */ - if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x0F)) != 0x00) - { - tmpreg = GPIOx->CRL; - for (pinpos = 0x00; pinpos < 0x04; pinpos++) - { - pos = ((uint32_t)0x01) << pinpos; - /* Get the port pins position */ - currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; - if (currentpin == pos) - { - pos = pinpos << 2; - /* Clear the corresponding low control register bits */ - pinmask = ((uint32_t)0x0F) << pos; - tmpreg &= ~pinmask; - /* Write the mode configuration in the corresponding bits */ - tmpreg |= (currentmode << pos); - } - } - GPIOx->CRL = tmpreg; - } - /*---------------------------- GPIO CRH Configuration ------------------------*/ - /* Configure the four high port pins */ - if (GPIO_InitStruct->GPIO_Pin > 0x0F) - { - tmpreg = GPIOx->CRH; - for (pinpos = 0x00; pinpos < 0x04; pinpos++) - { - pos = (((uint32_t)0x01) << (pinpos + 0x04)); - /* Get the port pins position */ - currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); - if (currentpin == pos) - { - pos = pinpos << 2; - /* Clear the corresponding high control register bits */ - pinmask = ((uint32_t)0x0F) << pos; - tmpreg &= ~pinmask; - /* Write the mode configuration in the corresponding bits */ - tmpreg |= (currentmode << pos); - } - } - GPIOx->CRH = tmpreg; - } -} - -/** - * @brief Fills each GPIO_InitStruct member with its default value. - * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) -{ - /* Reset GPIO init structure parameters values */ - GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN; -} - -/** - * @} - */ - -/** @defgroup GPIO_Group2 GPIO Read and Write - * @brief GPIO Read and Write - * -@verbatim - =============================================================================== - GPIO Read and Write - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Reads the specified input port pin. - * @param GPIOx: where x can be (A, B or C) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..7). - * @retval The input port pin value. - */ -uint32_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin) -{ - uint32_t bitstatus = 0x00; - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint32_t)Bit_SET; - } - else - { - bitstatus = (uint32_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified GPIO input data port. - * @param GPIOx: where x can be (A..C) to select the GPIO peripheral. - * @retval GPIO input data port value. - */ -uint32_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint32_t)GPIOx->IDR); -} - -/** - * @brief Reads the specified output data port bit. - * @param GPIOx: where x can be (A, B or C) to select the GPIO peripheral. - * @param GPIO_Pin: Specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..7). - * @retval The output port pin value. - */ -uint32_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin) -{ - uint32_t bitstatus = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint32_t)Bit_SET; - } - else - { - bitstatus = (uint32_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified GPIO output data port. - * @param GPIOx: where x can be (A, B or C) to select the GPIO peripheral. - * @retval GPIO output data port value. - */ -uint32_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint32_t)GPIOx->ODR); -} - -/** - * @brief Sets the selected data port bits. - * @param GPIOx: where x can be (A, B or C) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..7). - * @note This functions uses GPIOx_SET register to allow atomic read/modify - * accesses. In this way, there is no risk of an IRQ occurring between - * the read and the modify access. - * @retval None - */ -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BSR = GPIO_Pin; -} - -/** - * @brief Clears the selected data port bits. - * @param GPIOx: where x can be (A, B or C) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..7). - * @note This functions uses GPIOx_CLR register to allow atomic read/modify - * accesses. In this way, there is no risk of an IRQ occurring between - * the read and the modify access. - * @retval None - */ -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BRR = GPIO_Pin; -} - -/** - * @brief Sets or clears the selected data port bit. - * @param GPIOx: where x can be (A, B or C) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be one of GPIO_Pin_x where x can be (0..7). - * @param BitVal: specifies the value to be written to the selected bit. - * This parameter can be one of the BitAction enum values: - * @arg Bit_RESET: to clear the port pin - * @arg Bit_SET: to set the port pin - * @retval None - */ -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin, BitAction BitVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - assert_param(IS_GPIO_BIT_ACTION(BitVal)); - - if (BitVal != Bit_RESET) - { - GPIOx->BSR = GPIO_Pin; - } - else - { - GPIOx->BRR = GPIO_Pin ; - } -} - -/** - * @brief Writes data to the specified GPIO data port. - * @param GPIOx: where x can be (A, B or C) to select the GPIO peripheral. - * @param PortVal: specifies the value to be written to the port output data - * register. - * @retval None - */ -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - GPIOx->ODR = PortVal; -} -/** - * @} - */ - -/** @defgroup GPIO_Group3 GPIO Wake and Debug Configuration - * @brief GPIO Wake and Debug Configuration - * -@verbatim - =============================================================================== - Debug Configuration - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Selects PC_TRACE source on bb_debug GPIO pins. - * @param PCTRACE_SEL: specifies the PC_TRACE source on bb_debug GPIO pins. - * This parameter can be : - * @arg GPIO_BBDEBUG: bb debug. - * @arg GPIO_PCTRACE: pc trace. - * @retval None. - */ -void GPIO_PCTraceConfig(uint32_t PCTRACE_SEL) -{ - /* Check the parameters */ - assert_param(IS_GPIO_PCTRACE(PCTRACE_SEL)); - - GPIO_DBG->PCTRACECR = PCTRACE_SEL; -} - -/** - * @brief Enables or disables the debug interface. - * @param NewState: new state of the debug interface. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void GPIO_DebugInterfaceCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Clear the DEBUGDIS bit to Enable the debug interface */ - GPIO_DBG->DBGCR &= (uint32_t)~GPIO_DBGCR_DBGDIS; - - } - else - { - /* Set the DEBUGDIS bit to Disable the debug interface */ - GPIO_DBG->DBGCR |= (uint32_t)GPIO_DBGCR_DBGDIS; - } -} - -/** - * @brief Enables or Disable REG_EN override of PA7's normal GPIO configuration. - * @param NewState: new state of the REG_EN. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void GPIO_ExternalOverrideCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Clear the GPIO_EXTREGEN bit to Enable the debug interface */ - GPIO_DBG->DBGCR &= (uint32_t)~GPIO_DBGCR_EXTREGEN; - - } - else - { - /* Set the GPIO_EXTREGEN bit to Disable the debug interface */ - GPIO_DBG->DBGCR |= (uint32_t)GPIO_DBGCR_EXTREGEN; - } -} - -/** - * @brief Checks whether the specified GPIO debug flag is set or not. - * @param GPIO_DBGFLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg GPIO_DBGSR_SWEN: Serial Wire interface flag - * @arg GPIO_DBGSR_FORCEDBG: Debugger interface flag - * @arg GPIO_DBGSR_BOOTMODE: nBOOTMODE signal sampled at the end of reset flag - * @retval The new state of GPIO_DBGFLAG (SET or RESET). - */ -FlagStatus GPIO_GetDebugFlagStatus(uint16_t GPIO_DBGFLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_GPIO_GET_DBGFLAG(GPIO_DBGFLAG)); - - /* Check the status of the specified GPIO debug flag */ - if ((GPIO_DBG->DBGSR & GPIO_DBGFLAG) != (uint32_t)RESET) - { - /* GPIO_DBGFLAG is set */ - bitstatus = SET; - } - else - { - /* GPIO_DBGFLAG is reset */ - bitstatus = RESET; - } - /* Return the GPIO_DBGFLAG status */ - return bitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_misc.c b/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_misc.c deleted file mode 100644 index 3b8c27c..0000000 --- a/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_misc.c +++ /dev/null @@ -1,229 +0,0 @@ -/** - ****************************************************************************** - * @file stm32w108xx_misc.c - * @author MCD Application Team - * @version V1.0.1 - * @date 30-November-2012 - * @brief This file provides all the miscellaneous firmware functions (add-on - * to CMSIS functions). - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2012 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32w108xx_misc.h" - -/** @addtogroup STM32W108xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup MISC - * @brief MISC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup MISC_Private_Functions - * @{ - */ - -/** - * -@verbatim - ******************************************************************************* - ##### Interrupts configuration functions ##### - ******************************************************************************* - [..] This section provide functions allowing to configure the NVIC interrupts - (IRQ).The Cortex-M3 exceptions are managed by CMSIS functions. - (#) Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig() - function according to the following table. - The table below gives the allowed values of the preemption priority - and subpriority according to the Priority Grouping configuration - performed by NVIC_PriorityGroupConfig function. - ============================================================================================================================ - NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description - ============================================================================================================================ - NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for preemption priority - | | | 4 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for preemption priority - | | | 3 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for preemption priority - | | | 2 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for preemption priority - | | | 1 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for preemption priority - | | | 0 bits for subpriority - ============================================================================================================================ - - - (#) Enable and Configure the priority of the selected IRQ Channels. - - -@- When the NVIC_PriorityGroup_0 is selected, it will no any nested interrupt, - the IRQ priority will be managed only by subpriority. - The sub-priority is only used to sort pending exception priorities, - and does not affect active exceptions. - -@- Lower priority values gives higher priority. - -@- Priority Order: - (#@) Lowest Preemption priority. - (#@) Lowest Subpriority. - (#@) Lowest hardware priority (IRQn position). - -@endverbatim -*/ - -/** - * @brief Configures the priority grouping: preemption priority and subpriority. - * @param NVIC_PriorityGroup: specifies the priority grouping bits length. - * This parameter can be one of the following values: - * @arg NVIC_PriorityGroup_0: 0 bits for preemption priority - * 4 bits for subpriority. - * @note When NVIC_PriorityGroup_0 is selected, it will no be any nested - * interrupt. This interrupts priority is managed only with subpriority. - * @arg NVIC_PriorityGroup_1: 1 bits for preemption priority. - * 3 bits for subpriority. - * @arg NVIC_PriorityGroup_2: 2 bits for preemption priority. - * 2 bits for subpriority. - * @arg NVIC_PriorityGroup_3: 3 bits for preemption priority. - * 1 bits for subpriority. - * @arg NVIC_PriorityGroup_4: 4 bits for preemption priority. - * 0 bits for subpriority. - * @retval None - */ -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); - - /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ - SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; -} - -/** - * @brief Initializes the NVIC peripheral according to the specified - * parameters in the NVIC_InitStruct. - * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() - * function should be called before. - * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains - * the configuration information for the specified NVIC peripheral. - * @retval None - */ -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) -{ - uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); - assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); - assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); - - if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) - { - /* Compute the Corresponding IRQ Priority --------------------------------*/ - tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; - tmppre = (0x4 - tmppriority); - tmpsub = tmpsub >> tmppriority; - - tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; - tmppriority |= (uint8_t)((NVIC_InitStruct->NVIC_IRQChannelSubPriority) & tmpsub); - tmppriority = tmppriority << 0x04; - - NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; - - /* Enable the Selected IRQ Channels --------------------------------------*/ - NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = - (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); - } - else - { - /* Disable the Selected IRQ Channels -------------------------------------*/ - NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = - (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); - } -} - -/** - * @brief Sets the vector table location and Offset. - * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. - * This parameter can be one of the following values: - * @arg NVIC_VectTab_RAM: Vector Table in internal SRAM. - * @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH. - * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200. - * @retval None - */ -void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) -{ - /* Check the parameters */ - assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); - assert_param(IS_NVIC_OFFSET(Offset)); - - SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); -} - -/** - * @brief Selects the condition for the system to enter low power mode. - * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. - * This parameter can be one of the following values: - * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend. - * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request. - * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit. - * @param NewState: new state of LP condition. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_NVIC_LP(LowPowerMode)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - SCB->SCR |= LowPowerMode; - } - else - { - SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_pwr.c b/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_pwr.c deleted file mode 100644 index 6be77d7..0000000 --- a/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_pwr.c +++ /dev/null @@ -1,548 +0,0 @@ -/** - ****************************************************************************** - * @file stm32w108xx_pwr.c - * @author MCD Application Team - * @version V1.0.1 - * @date 30-November-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the power management (PWR): - * + Voltage Regulator control - * + WakeUp Pin/Source Configuration - * + DeepSleep mode - * + WakeUp status - * - * @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] This driver provides the Low level functions to manage the low level power - registers. These functions are split in 4 groups - - (#) Voltage Regulator control functions: this group includes the - management of following features using PWR_VREGInit() function: - (++) Configure the regulator Trim values - (++) Enable/Disable VREF, V1.8 and V1.2 voltage regulators - - (#) WakeUp Pin/Source Configuration functions: this group includes all - needed to configure an interrupt as WakeUp source: - (++) To control the GPIO pin to WakeUp the system from low power mode use the - PWR_GPIOWakeUpPinCmd() function. - (++) To configure the WakeUp method to wake the system from low power mode use - the PWR_WakeUpSourceConfig() function. - (++) To command the WakeUp source filter use PWR_WakeUpFilterConfig() function. - - (#) DeepSleep mode functions: this group includes the deep sleep feature - configuration: - (++) To freeze the GPIO state before entering in low power mode use - the PWR_FreezestateLVoutput() function. - (++) To control the deep sleep mode 0 when debugger is attached use - the PWR_DeepSleepMode0Cmd() function. - (++) To Wake the core from deep sleep 0 the WakeUp source filter use - PWR_CoreWake() function. - (++) To Disable the system access to the ACK bit in the CSYSPWRUPACKSR use - PWR_InhibitCSYSPWRUPACK() function. - - (#) WakeUp Status functions: this group includes the required functions to - manage the WakeUp interrupt status: - (++) When the system wake up from low power mode use PWR_GetFlagStatus() - to check witch interrupt is the source for WakeUp. - (++) After check the user should clear the WakeUp source in the low power - status register using PWR_ClearFlag() function. - - @endverbatim - * - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2012 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - - -/* Includes ------------------------------------------------------------------*/ -#include "stm32w108xx_pwr.h" - -/** @addtogroup STM32W108xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup POWER_MANAGEMENT - * @brief PWR driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup PWR_Private_Functions - * @{ - */ - -/** @defgroup PWR_Group1 Voltage Regulator control - * @brief Voltage regulator VREF, V1.8 and V1.2 control - * -@verbatim - =============================================================================== - ##### Voltage Regulator control function ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the PWR peripheral registers to their default reset values. - * @param None - * @retval None - */ -void PWR_DeInit(void) -{ - PWR->DSLEEPCR1 = 0x00000000; - PWR->DSLEEPCR2 = 0x00000001; - PWR->VREGCR = 0x00000207; - PWR->WAKECR1 = 0x00000200; - PWR->WAKECR2 = 0x00000000; - PWR->WAKESR = 0x000003FF; - PWR->CSYSPWRUPACKCR = 0x00000000; - PWR->WAKEPAR = 0x00000000; - PWR->WAKEPBR = 0x00000000; - PWR->WAKEPCR = 0x00000000; - PWR->WAKEFILTR = 0x00000000; -} - -/** - * @brief Fills each VREG_InitStruct member with its default value. - * @param VREG_InitStruct: pointer to a PWR_VREG_InitTypeDef structure - * which will be initialized. - * @retval None - */ -void PWR_VREGStructInit(PWR_VREG_InitTypeDef* VREG_InitStruct) -{ - /* VREG_InitStruct members default value */ - VREG_InitStruct->PWR_VREFCmd = POWER_ENABLE; /* by default enable */ - VREG_InitStruct->PWR_1V8Cmd = POWER_ENABLE; /* by default enable */ - VREG_InitStruct->PWR_1V8TRIM = 4; - VREG_InitStruct->PWR_1V2Cmd = POWER_ENABLE; /* by default enable */ - VREG_InitStruct->PWR_1V2TRIM = 7; -} - -/** - * @brief Initializes the VREG peripheral according to the specified - * parameters in the VREG_InitStruct. - * @param VREG_InitStruct: pointer to a PWR_VREG_InitTypeDef structure - * that contains the configuration information for the specified VREG. - * @retval None - */ -void PWR_VREGInit(PWR_VREG_InitTypeDef* VREG_InitStruct) -{ - uint32_t temp = 0; - - /* Check the parameters */ - assert_param(IS_POWER_FUNCTIONAL_STATE(VREG_InitStruct->PWR_VREFCmd)); - assert_param(IS_POWER_FUNCTIONAL_STATE(VREG_InitStruct->PWR_1V8Cmd)); - assert_param(IS_TRIM_VALUE(VREG_InitStruct->PWR_1V8TRIM)); - assert_param(IS_POWER_FUNCTIONAL_STATE(VREG_InitStruct->PWR_1V2Cmd)); - assert_param(IS_TRIM_VALUE(VREG_InitStruct->PWR_1V2TRIM)); - - temp = (uint32_t)(((VREG_InitStruct->PWR_1V8TRIM) << 7) | (VREG_InitStruct->PWR_1V2TRIM)); - - /* Check the new VREF status */ - if (VREG_InitStruct->PWR_VREFCmd == POWER_DISABLE) - { - /* Disable VREF */ - temp |= PWR_VREGCR_VREFEN; - } - - /* Check the new 1V8 status */ - if (VREG_InitStruct->PWR_1V8Cmd == POWER_DISABLE) - { - /* Disable 1V8 */ - temp |= PWR_VREGCR_1V8EN; - } - - /* Check the new 1V2 status */ - if (VREG_InitStruct->PWR_1V2Cmd == POWER_DISABLE) - { - /* Disable 1V2 */ - temp |= PWR_VREGCR_1V2EN; - } - - /* Set the new VREG configuration */ - PWR->VREGCR = temp; -} - -/** - * @} - */ - -/** @defgroup PWR_Group2 WakeUp Pin/Source Configuration - * @brief Low Power mode source WakeUp and method configuration - * -@verbatim - =============================================================================== - ##### WakeUp Pin-Source Configuration function ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the GPIO WakeUp pin. - * @param GPIOx: where x can be (A, B or C) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be one of GPIO_Pin_x where x can be (0..7). - * @param NewState: new state of the GPIO WakeUp pin source. - * This parameter can be: ENABLE or DISABLE. - * @note The GPIO WakeUp monitoring should be enabled before enabling the GPIO WakeUp pin. - * To enable the GPIO WakeUp monitoring use PWR_WakeUpSourceConfig() function. - * @retval None - */ -void PWR_GPIOWakeUpPinCmd(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (GPIOx == GPIOA) - { - if (NewState != DISABLE) - { - PWR->WAKEPAR |= (uint32_t)GPIO_Pin; - } - else - { - PWR->WAKEPAR &= (uint32_t)~GPIO_Pin; - } - } - else if (GPIOx == GPIOB) - { - if (NewState != DISABLE) - { - PWR->WAKEPBR |= (uint32_t)GPIO_Pin; - } - else - { - PWR->WAKEPBR &= (uint32_t)~GPIO_Pin; - } - } - else - { - if (GPIOx == GPIOC) - { - if (NewState != DISABLE) - { - PWR->WAKEPCR |= (uint32_t)GPIO_Pin; - } - else - { - PWR->WAKEPCR &= (uint32_t)~GPIO_Pin; - } - } - } -} - -/** - * @brief Enables or disables the WakeUp source filter. - * @param PWR_WakeUpSource: specifies the selected PWR WakeUp source. - * This parameter can be one of the following values: - * @arg PWR_WAKEFILTER_GPIO: filter active on GPIO monitoring. - * @arg PWR_WAKEFILTER_SC1: filter active on SC1. - * @arg PWR_WAKEFILTER_SC2: filter active on SC2. - * @arg PWR_WAKEFILTER_IRQD: filter active on IRQD. - * @param NewState: new state of the WakeUp source. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_WakeUpFilterConfig(uint32_t PWR_WakeUpSource, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_PWR_WAKEUPFILTERSOURCE(PWR_WakeUpSource)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the dedicated WakeUp filter by setting the dedicated bit in the - WAKEFILTR register */ - PWR->WAKEFILTR |= PWR_WakeUpSource; - } - else - { - /* Disable the dedicated WakeUp filter by clearing the dedicated bit in the WAKEFILTR register */ - PWR->WAKEFILTR &= (uint32_t)~((uint32_t)PWR_WakeUpSource); - } -} - -/** - * @brief Enables or disables the WakeUp method form low power mode. - * @param PWR_WakeUpSource: specifies the selected PWR wakeup method. - * This parameter can be one of the following values: - * @arg PWR_WAKEUP_CSYSPWRRUPREQ: Wake up active on CSYSPWRUPREQ event. - * @arg PWR_WAKEUP_CPWRRUPREQ: Wake up active on CPWRRUPREQ event. - * @arg PWR_WAKEUP_CORE: Wake up active on COREWAKE event. - * @arg PWR_WAKEUP_WRAP: Wake up active on sleep timer compare wrap/overflow event. - * @arg PWR_WAKEUP_COMPB: Wake up active on sleep timer compare B event. - * @arg PWR_WAKEUP_COMPA: Wake up active on sleep timer compare A event. - * @arg PWR_WAKEUP_IRQD: Wake up active on falling/rising edge of pin PC0. - * @arg PWR_WAKEUP_SC2: Wake up active on falling/rising edge of pin PA2 for SC2. - * @arg PWR_WAKEUP_SC1: Wake up active on falling/rising edge of pin PB2 for SC12. - * @arg PWR_WAKEUP_MON: Wake up active on GPIO monitoring. - * @param NewState: new state of the WakeUp source. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_WakeUpSourceConfig(uint32_t PWR_WakeUpSource, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_PWR_WAKEUPSOURCE(PWR_WakeUpSource)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the WakeUp from low power method by setting the dedicated bit in the WAKECR1 register */ - PWR->WAKECR1 |= PWR_WakeUpSource; - } - else - { - /* Disable the WakeUp from low power method by clearing the dedicated bit in the WAKECR1 register */ - PWR->WAKECR1 &= (uint32_t)~((uint32_t)PWR_WakeUpSource); - } -} - -/** - * @} - */ - -/** @defgroup PWR_Group3 DeepSleep mode - * @brief control the DeepSleep mode features - * -@verbatim - =============================================================================== - ##### DeepSleep mode function ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the freeze GPIO state LV output. - * @param NewState: new freeze state of the GPIO state LV output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_FreezestateLVoutput(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable freeze GPIO state LV output by setting the LVFREEZE bit in the DSLEEPCR1 register */ - PWR->DSLEEPCR1 |= PWR_DSLEEPCR1_LVFREEZE; - } - else - { - /* Disable freeze GPIO state LV output from low power method by clearing the LVFREEZE bit in the DSLEEPCR1 register */ - PWR->DSLEEPCR1 &= (uint32_t)~((uint32_t)PWR_DSLEEPCR1_LVFREEZE); - } -} - -/** - * @brief Enables or disables the deep sleep mode 0 when debugger is attached. - * @param NewState: new freeze state of the GPIO state LV output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_DeepSleepMode0Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable deep sleep mode 0 if debugger attached by setting the MODE bit in the DSLEEPCR2 register */ - PWR->DSLEEPCR2 |= PWR_DSLEEPCR2_MODE; - } - else - { - /* Disable deep sleep mode 0 if debugger by clearing the MODE bit in the DSLEEPCR2 register */ - PWR->DSLEEPCR2 &= (uint32_t)~((uint32_t)PWR_DSLEEPCR2_MODE); - } -} - -/** - * @brief Wake core form a deep sleep 0. - * @param None - * @retval None - */ -void PWR_CoreWake(void) -{ - /* Wake core from deep sleep 0 by setting the COREWAKE bit in the WAKECR2 register */ - PWR->WAKECR2 |= PWR_WAKECR2_COREWAKE; -} - -/** - * @brief Disables the cortex-M3 system access to the ACK bit in the CSYSPWRUPACKSR register. - * @param None - * @retval None - */ -void PWR_InhibitCSYSPWRUPACK(void) -{ - /* Disable the system access to the ACK bit in the CSYSPWRUPACKSR by setting - the INHIBIT bit in the CSYSPWRUPACKCR register */ - PWR->CSYSPWRUPACKCR |= PWR_CSYSPWRUPACKCR_INHIBIT; -} - -/** - * @} - */ - -/** @defgroup PWR_Group4 WakeUp status - * @brief Control the low power WakeUp source status - * -@verbatim - =============================================================================== - ##### WakeUp status function ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the specified PWR flag is set or not. - * @param PWR_FLAG: specifies the low power wake up flag to check. - * This parameter can be one of the following values: - * @arg PWR_FLAG_CSYSPWRRUPREQ: Wake up done using the DAP access to SYS registers flag - * @arg PWR_FLAG_CPWRRUPREQ: Wake up done using the DAP access to DBG registers flag - * @arg PWR_FLAG_CORE: Wake up done using debug port activity flag - * @arg PWR_FLAG_WRAP: Wake up done using sleep timer wrap flag - * @arg PWR_FLAG_COMPB: Wake up done using sleep timer compare B flag - * @arg PWR_FLAG_COMPA: Wake up done using sleep timer compare A flag - * @arg PWR_FLAG_IRQD: Wake up done using external interrupt IRQD flag - * @arg PWR_FLAG_SC2: Wake up done using serial controller 2 (PA2) flag - * @arg PWR_FLAG_SC1: Wake up done using serial controller 1 (PB2) flag - * @arg PWR_FLAG_MON: Wake up done using GPIO monitoring flag - * @arg PWR_FLAG_CPWRUPREQ: REQ flag in the CPWRUPREQSR register - * @arg PWR_FLAG_CSYSPWRUPREQ: REQ flag in the CSYSPWRUPREQSR register - * @arg PWR_FLAG_CSYSPWRUPREQ: ACK flag in the CSYSPWRUPREQSR register - * @retval The new state of PWR_FLAG (SET or RESET). - */ -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); - - /* Check the REQ flag in the CPWRUPREQSR register */ - if (PWR_FLAG == PWR_FLAG_CPWRUPREQ) - { - if ((PWR->CPWRUPREQSR & 0x00000001) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - /* Check the REQ flag in the CSYSPWRUPREQSR register */ - else if (PWR_FLAG == PWR_FLAG_CSYSPWRUPREQ) - { - if ((PWR->CSYSPWRUPREQSR & 0x00000001) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - /* Check the ACK flag in the CSYSPWRUPACKSR register */ - else if (PWR_FLAG == PWR_FLAG_CSYSPWRUPREQ) - { - if ((PWR->CSYSPWRUPACKSR & 0x00000001) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - /* Check the Wake up flag in the WAKESR register */ - else - { - if ((PWR->WAKESR & PWR_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - return bitstatus; -} - -/** - * @brief Clears the PWR pending flags. - * @param PWR_FLAG: specifies the low power wake up flag to clear. - * This parameter can be one of the following values: - * @arg PWR_FLAG_CSYSPWRRUPREQ: Wake up done using the DAP access to SYS registers flag - * @arg PWR_FLAG_CPWRRUPREQ: Wake up done using the DAP access to DBG registers flag - * @arg PWR_FLAG_CORE: Wake up done using debug port activity flag - * @arg PWR_FLAG_WRAP: Wake up done using sleep timer wrap flag - * @arg PWR_FLAG_COMPB: Wake up done using sleep timer compare B flag - * @arg PWR_FLAG_COMPA: Wake up done using sleep timer compare A flag - * @arg PWR_FLAG_IRQD: Wake up done using external interrupt IRQD flag - * @arg PWR_FLAG_SC2: Wake up done using serial controller 2 (PA2) flag - * @arg PWR_FLAG_SC1: Wake up done using serial controller 1 (PB2) flag - * @arg PWR_FLAG_MON: Wake up done using GPIO monitoring flag - * @retval The new state of PWR_FLAG (SET or RESET). - */ -void PWR_ClearFlag(uint32_t PWR_FLAG) -{ - /* Check the parameters */ - assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); - - PWR->WAKESR = PWR_FLAG; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_rst.c b/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_rst.c deleted file mode 100644 index 10713b0..0000000 --- a/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_rst.c +++ /dev/null @@ -1,134 +0,0 @@ -/** - ****************************************************************************** - * @file stm32w108xx_rst.c - * @author MCD Application Team - * @version V1.0.1 - * @date 30-November-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the RST peripheral - * - * @verbatim - * - =============================================================================== - ##### RST specific features ##### - =============================================================================== - [..] This driver provide the information about reset source - - [..] The reset can be due to: - (#) Core lockup - (#) Option byte load failure (may be set with other bits - (#) Wake-up from Deep Sleep - (#) Software reset - (#) Watchdog expiration - (#) External reset pin signal - (#) The application of a Core power supply (or previously failed) - (#) Normal power applied - - - @endverbatim - * - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2012 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32w108xx_rst.h" - -/** @addtogroup STM32W108xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup RESET - * @brief RST driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RST_Private_Functions - * @{ - */ - -/** @defgroup RST_Group1 - * @brief Reset event sources - * -@verbatim - =============================================================================== - ##### RST EVENT SOURCES ##### - =============================================================================== - [..] This section provides function allowing to get reset event source - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the specified RST flag is set or not. - * @param RST_FLAG: specifies the RST_FLAG flag to check. - * This parameter can be one of the following values: - * @arg RST_FLAG_PWRHV: Normal power applied - * @arg RST_FLAG_PWRLV: The application of a Core power supply (or previously failed) - * @arg RST_FLAG_PIN: External reset pin signal. - * @arg RST_FLAG_WDG: Watchdog expiration - * @arg RST_FLAG_SWRST: Software reset. - * @arg RST_FLAG_WKUP: Wake-up from Deep Sleep - * @arg RST_FLAG_OBFAIL: Option byte load failure (may be set with other bits) - * @arg RST_FLAG_LKUP: Core lockup - * - * @retval The new state of RST_FLAG (SET or RESET) - */ -FlagStatus RST_GetFlagStatus(uint32_t RST_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_RST_FLAG(RST_FLAG)); - - if ((RST->SR & RST_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_sc.c b/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_sc.c deleted file mode 100644 index 25b2acd..0000000 --- a/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_sc.c +++ /dev/null @@ -1,1844 +0,0 @@ -/** - ****************************************************************************** - * @file stm32w108xx_sc.c - * @author MCD Application Team - * @version V1.0.1 - * @date 30-November-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the Serial Controller (SC): - * + Universal Asynchronous Receiver/Transmitter communication - * + Serial Peripheral Interface communication - * + Inter-Integrated Circuit communication - * + DMA transfers management in UART and SPI modes - * - * @verbatim - * - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - (#) Peripherals GPIO Configuration: - (++) Select the desired pin GPIO_InitStruct->GPIO_Pin according to the - defined Initialization and Configuration Tables for each serial control - modes (UART, SPI master, SPI Salve and I2C). - (++) Refer to the Initialization and Configuration Tables to configure - the GPIO_InitStruct->GPIO_Mode - (++) Call GPIO_Init() function. - (#) For the I2C mode Program the clock rate using the I2C_Init() function. - (#) For the SPI mode Program the Polarity, Phase, First Data, Clcok rate - and the Peripheral Mode rate using the SPI_Init() function. - (#) For the UART mode Program the Baud Rate, Word Length , Stop Bit, Parity and Hardware - flow control using the UART_Init() function. - (#) Enable the PPP using the PPP_Cmd() function. - (#) For UART Mode set pull-up resistors on Tx and Rx pins using GPIO_SetBits() function. - (#) Enable the NVIC and the corresponding interrupt using the function. - PPP_ITConfig() if you need to use interrupt mode. - (#) When using the DMA mode - (++) Configure the DMA using SC_DMA_Init() function. - (++) Active the needed channel Request using SC_DMA_ChannelLoadEnable() function. - - [..] - (@) PPP can be UART, SPI or I2C. - (@) The DMA is not support for I2C mode. - - @endverbatim - * - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2012 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - - -/* Includes ------------------------------------------------------------------*/ -#include "stm32w108xx_sc.h" - -/** @addtogroup STM32W108xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup SERIAL_CONTROLLER - * @brief SC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* I2C ADD0 mask */ -#define OAR1_ADD0_Set ((uint8_t)0x01) -#define OAR1_ADD0_Reset ((uint8_t)0xFE) -#define SPICR_CLEAR_MASK ((uint32_t)0xFFFFFFE8) - -/* Private macro -------------------------------------------------------------*/ -#define ABS(x) ((x) > 0) ? (x) : (-(x)) -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SC_Private_Functions - * @{ - */ - -/** @defgroup SC_Group1 Universal Asynchronous Receiver/Transmitter communication - * @brief universal asynchronous receiver transmitter functions - * -@verbatim - =============================================================================== - ##### Universal Asynchronous Receiver-Transmitter functions ##### - =============================================================================== - [..] This section provides a set of functions allowing to handles the Universal - Asynchronous Receiver Transmitter communication. - - (@) Only SC1 include an universal asynchronous receiver transmitter (UART) controller. - -*** Initialization and Configuration *** - ======================================= - [..] The GPIO pins that can be assigned to UART interface are listed in the following table: - +------------------------------------------------------+ - |Parameter | Direction | GPIO configuration | SC1 pin | - |----------|-----------|--------------------|----------| - | TXD | Out | Alternate Output | PB1 | - | | | (push-pull) | | - |----------|-----------|-------------------------------| - | RXD | In | Input | PB2 | - |----------|-----------|--------------------|----------| - | nCTS | In | Input | PB3 | - |----------|-----------|-------------------------------| - | nRTS | Out | Alternate Output | PB4 | - | | | (push-pull) | | - +------------------------------------------------------+ - - [..] For the asynchronous mode these parameters can be configured: - (+) Baud Rate. - (+) Word Length. - (+) Stop Bit. - (+) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (7-bits or 8-bits), - the possible UART frame formats are as listed in the following table: - - +-------------------------------------------------------------+ - | M bit | PCE bit | UART frame | - |---------------------|---------------------------------------| - | 0 | 0 | | SB | 7 bit data | STB | | - |---------|-----------|---------------------------------------| - | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|-----------|---------------------------------------| - | 1 | 0 | | SB | 8 bit data | STB | | - |---------|-----------|---------------------------------------| - | 1 | 1 | | SB | 8 bit data | PB | STB | | - +-------------------------------------------------------------+ - - (+) Hardware flow control. - [..] The UART_Init() function follows the UART asynchronous configuration - procedure (details for the procedure is available in datasheet. - -*** Data transfers *** - ===================== - [..] In reception, data are received and then stored into an internal Rx buffer while - In transmission, data are first stored into an internal Tx buffer before being - transmitted. - - [..] The read access of the SCx_DR register can be done using - UART_ReceiveData() function and returns the Rx buffered value. Whereas a write - access to the SCx_DR can be done using UART_SendData() function and stores - the written data into Tx buffer. - - *** Interrupts and flags management *** - ======================================= - [..] This subsection provides also a set of functions allowing to configure the - UART Interrupts sources, Requests and check or clear the flags or pending bits status. - The user should identify which mode will be used in his application to - manage the communication: Polling mode, Interrupt mode or DMA mode(refer SC_Group4). - - [..] In Polling Mode, the UART communication can be managed by these flags: - (#) UART_FLAG_TXE: to indicate the status of the transmit buffer register. - (#) UART_FLAG_RXNE: to indicate the status of the receive buffer register. - (#) UART_FLAG_IDLE: to indicate the status of the Idle Line. - (#) UART_FLAG_CTS: to indicate the status of the nCTS line. - (#) UART_FLAG_FE: to indicate if a frame error occur. - (#) UART_FLAG_PE: to indicate if a parity error occur. - (#) UART_FLAG_OVR: to indicate if an Overrun error occur. - [..] In this mode it is advised to use the following functions: - (+) FlagStatus UART_GetFlagStatus(SC_UART_TypeDef* SCx_UART, uint32_t UART_FLAG). - [..] In this mode all the UART flags are cleared by hardware. - - [..] In Interrupt Mode, the UART communication can be managed by 7 interrupt - sources and 7 pending bits: - (+) Pending Bits: - (##) UART_IT_PE: to indicate the status of Parity Error interrupt. - (##) UART_IT_FE: to indicate the status of Framing Error interrupt. - (##) UART_IT_UND: to indicate the status of UnderRun Error interrupt. - (##) UART_IT_OVR: to indicate the status of OverRun Error interrupt. - (##) UART_IT_IDLE: to indicate the status of IDLE line detected interrupt. - (##) UART_IT_TXE: to indicate the status of the Transmit data register empty interrupt. - (##) UART_IT_RXNE: to indicate the status of the Data Register not empty interrupt. - - (+) Interrupt Source: - (##) UART_IT_PE: specifies the interrupt source forParity Error pending interrupt. - (##) UART_IT_FE: specifies the interrupt source for Framing Error pending interrupt. - (##) UART_IT_UND: specifies the interrupt source for UnderRun Error pending interrupt. - (##) UART_IT_OVR: specifies the interrupt source for OverRun Error pending interrupt. - (##) UART_IT_IDLE: specifies the interrupt source for IDLE line detected pending interrupt. - (##) UART_IT_TXE: specifies the interrupt source for the Transmit data register empty pending interrupt. - (##) UART_IT_RXNE: specifies the interrupt source for the Data Register not empty pending interrupt. - -@@- These parameters are coded in order to use them as interrupt source - or as pending bits. - [..] In this Mode it is advised to use the following functions: - (+) void UART_ITConfig(SC_IT_TypeDef* SCx_IT, uint32_t UART_IT, FunctionalState NewState). - (+) ITStatus UART_GetITStatus(SC_IT_TypeDef* SCx_IT, uint32_t UART_IT). - (+) void UART_ClearITPendingBit(SC_IT_TypeDef* SCx_IT, uint32_t UART_IT). - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the SCx_UART peripheral registers to their default reset values. - * @param SCx_UART: where x can be 1 to select the Serial controller peripheral. - * @retval None - */ -void UART_DeInit(SC_UART_TypeDef* SCx_UART) -{ - /* Check the parameters */ - assert_param(IS_UART_PERIPH(SCx_UART)); - - SCx_UART->CR = 0; - SCx_UART->UARTCR = 0; - SCx_UART->UARTBRR1 = 0; - SCx_UART->UARTBRR2 = 0; -} - -/** - * @brief Initializes the SC1_UART peripheral according to the specified - * parameters in the UART_InitStruct . - * @param SCx_UART: where x can be 1 to select the Serial controller peripheral. - * @param UART_InitStruct: pointer to a UART_InitTypeDef structure - * that contains the configuration information for the specified SC1_UART peripheral. - * @retval None - */ -void UART_Init(SC_UART_TypeDef* SCx_UART, UART_InitTypeDef* UART_InitStruct) -{ - int32_t temp1, temp2 = 0; - uint32_t clockfrequency = 0; - uint32_t N = 0; - - /* Check the parameters */ - assert_param(IS_UART_PERIPH(SCx_UART)); - assert_param(IS_UART_BAUDRATE(UART_InitStruct->UART_BaudRate)); - assert_param(IS_UART_WORD_LENGTH(UART_InitStruct->UART_WordLength)); - assert_param(IS_UART_STOPBITS(UART_InitStruct->UART_StopBits)); - assert_param(IS_UART_PARITY(UART_InitStruct->UART_Parity)); - assert_param(IS_UART_HARDWARE_FLOW_CONTROL(UART_InitStruct->UART_HardwareFlowControl)); - - /* Disable the selected UART by clearing the MODE bits in the CR register */ - SCx_UART->CR &= (uint16_t)~((uint16_t)SC_CR_MODE); - - /*---------------------------- UARTCR Configuration ------------------------*/ - /* Configure the USART Word Length, Parity and mode ------------------------*/ - /* Set STOP bit according to USART_StopBits value */ - /* Set the M bits according to UART_WordLength value */ - /* Set PCE and PS bits according to USART_Parity value */ - /* Set HFCE and AHFCE bits according to UART_HardwareFlowControl value */ - SCx_UART->UARTCR = (uint32_t)(UART_InitStruct->UART_WordLength | UART_InitStruct->UART_Parity | - UART_InitStruct->UART_StopBits | UART_InitStruct->UART_HardwareFlowControl); - /*---------------------------- UART BRR Configuration ----------------------*/ - /* Configure the UART Baud Rate --------------------------------------------*/ - clockfrequency = CLK_GetClocksFreq(); - N = (uint16_t)(clockfrequency/(2*(UART_InitStruct->UART_BaudRate))); - - /* Write to UART BRR1 */ - SCx_UART->UARTBRR1 &= (uint32_t)~SC_UARTBRR1_N; - SCx_UART->UARTBRR1 |= (uint32_t)N; - - temp1 = (int32_t)(clockfrequency/(2*N)); - temp2 = (int32_t)(clockfrequency/(2*N +1)); - - temp1 = ABS((int32_t)((int32_t)temp1 - (int32_t)UART_InitStruct->UART_BaudRate)); - temp2 = ABS((int32_t)((int32_t)temp2 - (int32_t)UART_InitStruct->UART_BaudRate)); - - /* Check the baud rate error and write to UART BRR2 */ - if(temp1 > temp2) - { - SCx_UART->UARTBRR2 |= (uint32_t)SC_UARTBRR1_F; - } - else - { - SCx_UART->UARTBRR2 &=(uint32_t)~SC_UARTBRR1_F; - } -} - -/** - * @brief Fills each UART_InitStruct member with its default value. - * @param UART_InitStruct: pointer to a UART_InitTypeDef structure - * which will be initialized. - * @retval None - */ -void UART_StructInit(UART_InitTypeDef* UART_InitStruct) -{ - /* UART_InitStruct members default value */ - UART_InitStruct->UART_BaudRate = 115200; - UART_InitStruct->UART_WordLength = UART_WordLength_8b; - UART_InitStruct->UART_StopBits = UART_StopBits_1; - UART_InitStruct->UART_Parity = UART_Parity_No; - UART_InitStruct->UART_HardwareFlowControl = UART_HardwareFlowControl_Disable; -} - -/** - * @brief Enables or disables the RTS assertion for the specified SC1_UART peripheral. - * @param SCx_UART: where x can be 1 to select the Serial controller peripheral. - * @param NewState: new state of the SC1_UART peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void UART_RTSAssertionCmd(SC_UART_TypeDef* SCx_UART, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_UART_PERIPH(SCx_UART)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* The RTS signal is asserted by setting the nRTS bit in the UARTCR register */ - SCx_UART->UARTCR |= SC_UARTCR_nRTS; - } - else - { - /* The RTS signal is deasserted by clearing the nRTS bit in the UARTCR register */ - SCx_UART->UARTCR &= (uint16_t)~((uint16_t)SC_UARTCR_nRTS); - } -} - -/** - * @brief Enables or disables the specified SC1_UART peripheral. - * @param SCx_UART: where x can be 1 to select the Serial controller peripheral. - * @param NewState: new state of the SC1_UART peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void UART_Cmd(SC_UART_TypeDef* SCx_UART, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_UART_PERIPH(SCx_UART)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected UART by setting the MODE bit 0 in the CR register */ - SCx_UART->CR &= (uint16_t)~((uint16_t)SC_CR_MODE); - SCx_UART->CR |= SC_CR_MODE_0; - } - else - { - /* Disable the selected UART by clearing the MODE bits in the CR register */ - SCx_UART->CR &= (uint16_t)~((uint16_t)SC_CR_MODE); - } -} - -/** - * @brief Enables or disables the specified SCx_UART interrupts. - * @param SCx_IT: where x can be 1 or 2 to select the Serial controller peripheral. - * @param UART_IT: specifies the SCx_UART interrupt source to be enabled or disabled. - * This parameter can be one of the following values: - * @arg UART_IT_PE: Parity error interrupt mask - * @arg UART_IT_FE: Frame error interrupt mask - * @arg UART_IT_UND: Underrun interrupt mask (to be checked) - * @arg UART_IT_OVR: Overrun interrupt mask - * @arg UART_IT_IDLE: Idle line detected interrupt mask - * @arg UART_IT_TXE: Transmit data register empty interrupt mask - * @arg UART_IT_RXNE: Data Register not empty interrupt mask - * @param NewState: new state of the specified SCx_UART interrupt source. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void UART_ITConfig(SC_IT_TypeDef* SCx_IT, uint32_t UART_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_UART_IT_PERIPH(SCx_IT)); - assert_param(IS_UART_IT(UART_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected UART interrupt */ - SCx_IT->IER |= UART_IT; - } - else - { - /* Disable the selected UART interrupt */ - SCx_IT->IER &= (uint16_t)~((uint16_t)UART_IT); - } -} - -/** - * @brief Trigger event configuration to handle the specified SCx_UART interrupt. - * @param SCx_IT: where x can be 1 or 2 to select the Serial controller peripheral. - * @param UART_IT: specifies the SCx_UART interrupt to be configured. - * This parameter can be one of the following values: - * @arg UART_IT_IDLE: Idle line detected interrupt - * @arg UART_IT_TXE: Transmit data register empty interrupt - * @arg UART_IT_RXNE: Data Register not empty interrupt - * @param TriggerEvent: Trigger event configuration of the specified SCx_UART interrupt. - * This parameter can be one of the following values: - * @arg SC_TriggerEvent_Edge: The specified SCx_UART interrupt will be generated on edge - * @arg SC_TriggerEvent_Level: The specified SCx_UART interrupt will be generated on level - * @retval None - */ -void UART_TriggerEventConfig(SC_IT_TypeDef* SCx_IT, uint32_t UART_IT, uint32_t TriggerEvent) -{ - /* Check the parameters */ - assert_param(IS_UART_IT_PERIPH(SCx_IT)); - assert_param(IS_UART_TRIGGEREVENT_IT(UART_IT)); - assert_param(IS_SC_TRIGGEREVENT(TriggerEvent)); - - if (TriggerEvent != SC_TriggerEvent_Edge) - { - /* The UART_IT interrupt will be handled on level */ - SCx_IT->ICR |= UART_IT; - } - else - { - /* The UART_IT interrupt will be handled on edge */ - SCx_IT->ICR &= (uint16_t)~((uint16_t)UART_IT); - } -} - -/** - * @brief Transmits a Data through the SC1_UART peripheral. - * @param SCx_UART: where x can be 1 to select the Serial controller peripheral. - * @param Data: Data to be transmitted. - * @retval None - */ -void UART_SendData(SC_UART_TypeDef* SCx_UART, uint8_t Data) -{ - uint32_t scxbase = 0x00; - - /* Check the parameters */ - assert_param(IS_UART_PERIPH(SCx_UART)); - - scxbase = (uint32_t)SCx_UART; - - *(__IO uint32_t *) scxbase = Data; -} - -/** - * @brief Returns the most recent received data by the SC1_UART peripheral. - * @param SCx_UART: where x can be 1 to select the Serial controller peripheral. - * @retval The value of the received data. - */ -uint8_t UART_ReceiveData(SC_UART_TypeDef* SCx_UART) -{ - uint32_t scxbase = 0x00; - - /* Check the parameters */ - assert_param(IS_UART_PERIPH(SCx_UART)); - - scxbase = (uint32_t)SCx_UART; - - return *(__IO uint32_t *) scxbase; -} - -/** - * @brief Checks whether the specified SC1_UART flag is set or not. - * @param SCx_UART: where x can be 1 to select the Serial controller peripheral. - * @param UART_FLAG: specifies the SCx_UART flag to check. - * This parameter can be one of the following values: - * @arg UART_FLAG_CTS: Clear to send flag. - * @arg UART_FLAG_RXNE: Receive data register not empty flag. - * @arg UART_FLAG_TXE: Transmit data register empty flag. - * @arg UART_FLAG_ORE: OverRun Error flag. - * @arg UART_FLAG_FE: Framing Error flag. - * @arg UART_FLAG_PE: Parity Error flag. - * @arg UART_FLAG_IDLE: Idle Line detection flag. - * @retval The new state of UART_FLAG (SET or RESET). - */ -FlagStatus UART_GetFlagStatus(SC_UART_TypeDef* SCx_UART, uint32_t UART_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_UART_PERIPH(SCx_UART)); - assert_param(IS_UART_GET_FLAG(UART_FLAG)); - - if ((SCx_UART->UARTSR & UART_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Checks whether the specified SC1_UART pending interrupt is set or not. - * @param SCx_IT: where x can be 1 to select the Serial controller peripheral. - * @param UART_IT: specifies the pending interrupt to check. - * This parameter can be one of the following values: - * @arg UART_IT_PE: Parity error interrupt pending - * @arg UART_IT_FE: Frame error interrupt pending - * @arg UART_IT_UND: Underrun interrupt pending (to be checked) - * @arg UART_IT_OVR: Overrun interrupt pending - * @arg UART_IT_IDLE: Idle line detected interrupt pending - * @arg UART_IT_TXE: Transmit data register empty interrupt pending - * @arg UART_IT_RXNE: Data Register not empty interrupt pending - * @retval The new state of UART_IT (SET or RESET). - */ -ITStatus UART_GetITStatus(SC_IT_TypeDef* SCx_IT, uint32_t UART_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - /* Check the parameters */ - assert_param(IS_UART_IT_PERIPH(SCx_IT)); - assert_param(IS_UART_IT(UART_IT)); - - enablestatus = (uint32_t)(SCx_IT->IER & UART_IT); - if (((SCx_IT->ISR & UART_IT) != (uint32_t)RESET) && enablestatus) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the SC1_UART interrupt pending bits. - * @param SCx_IT: where x can be 1 to select the Serial controller peripheral. - * @param UART_IT: specifies the pending interrupt to check. - * This parameter can be one of the following values: - * @arg UART_IT_PE: Parity error interrupt pending - * @arg UART_IT_FE: Frame error interrupt pending - * @arg UART_IT_UND: Underrun interrupt pending (to be checked) - * @arg UART_IT_OVR: Overrun interrupt pending - * @arg UART_IT_IDLE: Idle line detected interrupt pending - * @arg UART_IT_TXE: Transmit data register empty interrupt pending - * @arg UART_IT_RXNE: Data Register not empty interrupt pending - * @retval None - */ -void UART_ClearITPendingBit(SC_IT_TypeDef* SCx_IT, uint32_t UART_IT) -{ - /* Check the parameters */ - assert_param(IS_UART_IT_PERIPH(SCx_IT)); - assert_param(IS_UART_IT(UART_IT)); - - SCx_IT->ISR = UART_IT; -} - -/** - * @} - */ - -/** @defgroup SC_Group2 Serial peripheral interface communication - * @brief serial peripheral interface functions - * -@verbatim - =============================================================================== - ##### Serial Peripheral Interface functions ##### - =============================================================================== - [..] This section provides a set of functions allowing to handles the serial peripheral - interface communication. - - (@) The SC1 and SC2 include an Serial Peripheral Interface (SPI) master/slave controller. - -*** Initialization and Configuration *** - ======================================= - [..] The GPIO pins that can be assigned to SPI interface are listed in the following tables: - (##) SPI Master Mode: - +-----------------------------------------------------------------+ - |Parameter | Direction | GPIO configuration | SC1 pin | SC2 pin | - |----------|-----------|--------------------|----------|----------| - | MOSI | Out | Alternate Output | PB1 | PA0 | - | | | (push-pull) | | | - |----------|-----------|-------------------------------|----------| - | MISO | In | Input | PB2 | PA1 | - |----------|-----------|--------------------|----------|----------| - | SCLK | Out | Alternate Output | PB3 | PA2 | - | | | (push-pull) | | | - | | | Special SCLK mode | | | - +-----------------------------------------------------------------+ - (##) SPI Slave Mode: - +-----------------------------------------------------------------+ - |Parameter | Direction | GPIO configuration | SC1 pin | SC2 pin | - |----------|-----------|--------------------|----------|----------| - | MOSI | In | Input | PB2 | PA0 | - |----------|-----------|-------------------------------|----------| - | MISO | Out | Alternate Output | PB1 | PA1 | - | | | (push-pull) | | | - |----------|-----------|--------------------|----------|----------| - | SCLK | In | Input | PB3 | PA2 | - |----------|-----------|--------------------|----------|----------| - | nSSEL | In | Input | PB4 | PA3 | - +-----------------------------------------------------------------+ - [..] For the Serial Peripheral Interface mode these parameters can be configured: - (+) Mode. - (+) Data Size. - (+) Polarity. - (+) Phase. - (+) Baud Rate - (+) First Bit Transmission - [..] The SPI_Init() function follows the SPI configuration procedures for Master mode - and Slave mode (details for these procedures are available in datasheet). - -*** Data transfers *** - ===================== - - [..] In reception, data are received and then stored into an internal Rx buffer while - In transmission, data are first stored into an internal Tx buffer before being - transmitted. - - [..] The read access of the SCx_DR register can be done using SPI_ReceiveData() - function and returns the Rx buffered value. Whereas a write access to the SCx_DR - can be done using SPI_SendData() function and stores the written data into - Tx buffer. - - *** Interrupts and flags management *** - ======================================= - [..] This subsection provides also a set of functions allowing to configure the - SPI Interrupts sources, Requests and check or clear the flags or pending bits status. - The user should identify which mode will be used in his application to - manage the communication: Polling mode, Interrupt mode or DMA mode(refer SC_Group4). - - [..] In Polling Mode, the SPI communication can be managed by these flags: - (#) SPI_FLAG_TXE: to indicate the status of the transmit buffer register. - (#) SPI_FLAG_RXNE: to indicate the status of the receive buffer register. - (#) SPI_FLAG_IDLE: to indicate the status of the Idle Line. - (#) SPI_FLAG_OVR: to indicate if an Overrun error occur. - [..] In this Mode it is advised to use the following functions: - (+) FlagStatus SPI_GetFlagStatus(SC_SPI_TypeDef* SCx_SPI, uint32_t SPI_FLAG). - [..] In this mode all the SPI flags are cleared by hardware. - - [..] In Interrupt Mode, the SPI communication can be managed by 5 interrupt - sources and 5 pending bits: - (+) Pending Bits: - (##) SPI_IT_UND: to indicate the status of UnderRun Error interrupt. - (##) SPI_IT_OVR: to indicate the status of OverRun Error interrupt. - (##) SPI_IT_IDLE: to indicate the status of IDLE line detected interrupt. - (##) SPI_IT_TXE: to indicate the status of the Transmit data register empty interrupt. - (##) SPI_IT_RXNE: to indicate the status of the Data Register not empty interrupt. - - (+) Interrupt Source: - (##) SPI_IT_UND: specifies the interrupt source for UnderRun Error pending interrupt. - (##) SPI_IT_OVR: specifies the interrupt source for OverRun Error pending interrupt. - (##) SPI_IT_IDLE: specifies the interrupt source for IDLE line detected pending interrupt. - (##) SPI_IT_TXE: specifies the interrupt source for the Transmit data register empty pending interrupt. - (##) SPI_IT_RXNE: specifies the interrupt source for the Data Register not empty pending interrupt. - -@@- These parameters are coded in order to use them as interrupt - source or as pending bits. - [..] In this mode it is advised to use the following functions: - (+) void SPI_ITConfig(SC_IT_TypeDef* SCx_IT, uint32_t SPI_IT, FunctionalState NewState). - (+) ITStatus SPI_GetITStatus(SC_IT_TypeDef* SCx_IT, uint32_t SPI_IT). - (+) void SPI_ClearITPendingBit(SC_IT_TypeDef* SCx_IT, uint32_t SPI_IT). - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the SCx_SPI peripheral registers to their default reset values. - * @param SCx_SPI: where x can be 1 or 2 to select the Serial controller peripheral. - * @retval None - */ -void SPI_DeInit(SC_SPI_TypeDef* SCx_SPI) -{ - /* Check the parameters */ - assert_param(IS_SPI_PERIPH(SCx_SPI)); - - SCx_SPI->CR = 0; - SCx_SPI->SPICR = 0; - SCx_SPI->CRR1 = 0; - SCx_SPI->CRR2 = 0; -} - -/** - * @brief Initializes the SCx_SPI peripheral according to the specified - * parameters in the SPI_InitStruct. - * @param SCx_SPI: where x can be 1 or 2 to select the Serial controller peripheral. - * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral. - * @retval None - */ -void SPI_Init(SC_SPI_TypeDef* SCx_SPI, SPI_InitTypeDef* SPI_InitStruct) -{ - uint32_t tmpreg = 0; - uint8_t expvalue = 0, linvalue = 0, tmpexp = 0, tmplin = 0, idx = 0; - uint32_t tempclockrate = 0, clockrate = 0, power = 0; - - /* Check the SPI parameters */ - assert_param(IS_SPI_PERIPH(SCx_SPI)); - assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); - assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); - assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); - assert_param(IS_SPI_CLOCK_RATE(SPI_InitStruct->SPI_ClockRate)); - assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); - - /* Get the SCx SPICR register value */ - tmpreg = SCx_SPI->SPICR; - - /* Clear Mode, LSBFirst, CPOL and CPHA bits */ - tmpreg &= SPICR_CLEAR_MASK; - /*---------------------------- SCx_SPICR Configuration ---------------------*/ - /* Set MSTR bits according to SPI_Mode values */ - /* Set LSBFirst bit according to SPI_FirstBit value */ - /* Set CPOL bit according to SPI_CPOL value */ - /* Set CPHA bit according to SPI_CPHA value */ - tmpreg |= (uint32_t)((uint32_t)SPI_InitStruct->SPI_Mode | (uint32_t)SPI_InitStruct->SPI_CPOL | - (uint32_t)SPI_InitStruct->SPI_CPHA | (uint32_t)SPI_InitStruct->SPI_FirstBit); - /* Write to SCx SPICR register */ - SCx_SPI->SPICR = tmpreg; - - /*---------------------------- SCx_CRRx Configuration ----------------------*/ - for(linvalue = 0x00; linvalue < 16; linvalue++) - { - for(expvalue = 0x00; expvalue < 16; expvalue++) - { - power = 0x01; - for (idx=1; idx <= expvalue; idx++) - { - power*=2; - } - tempclockrate = power * (uint32_t)(linvalue + 1); - - if (tempclockrate == ((uint32_t)((uint32_t)CLK_GetClocksFreq()/(uint32_t)(2*(SPI_InitStruct->SPI_ClockRate))))) - { - SCx_SPI->CRR1 = (uint32_t)linvalue; - SCx_SPI->CRR2 = (uint32_t)expvalue; - } - else - { - /* Check the clock rate error and write to CRRx */ - if((ABS((int32_t)tempclockrate - (int32_t)(CLK_GetClocksFreq()/(2*(SPI_InitStruct->SPI_ClockRate))))) < (ABS((int32_t)clockrate - (int32_t)(CLK_GetClocksFreq()/(2*(SPI_InitStruct->SPI_ClockRate)))))) - { - clockrate = tempclockrate; - tmplin = linvalue; - tmpexp = expvalue; - } - } - } - } - - SCx_SPI->CRR1 = (uint32_t)tmplin; - SCx_SPI->CRR2 = (uint32_t)tmpexp; -} - -/** - * @brief Fills each SPI_InitStruct member with its default value. - * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized. - * @retval None - */ -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) -{ - /*--------------- Reset SPI init structure parameters values ---------------*/ - /* Initialize the SPI_Mode member */ - SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; - /* Initialize the SPI_CPOL member */ - SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; - /* Initialize the SPI_CPHA member */ - SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; - /* Initialize the SPI_ClockRate member */ - SPI_InitStruct->SPI_ClockRate = 3000000; - /* Initialize the SPI_FirstBit member */ - SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; -} - -/** - * @brief Configures the Receiver driven mode for the selected SCx_SPI (Master mode only). - * @param SCx_SPI: where x can be 1 or 2 to select the Serial controller peripheral. - * @param SPI_ReceiverMode: specifies the Receiver driven mode to be configured. - * This parameter can be one of the following values: - * @arg SPI_ReceiverMode_TxDataReady: Initiate transactions when transmit data is available - * @arg SPI_ReceiverMode_RxFIFOFree: Initiate transactions when receive buffer has space - * @retval None - */ -void SPI_ReceiverModeConfig(SC_SPI_TypeDef* SCx_SPI, uint32_t SPI_ReceiverMode) -{ - /* Check the parameters */ - assert_param(IS_SPI_PERIPH(SCx_SPI)); - assert_param(IS_SPI_RECEIVER_DRIVEN_MODE(SPI_ReceiverMode)); - - /* Clear RXMODE bit */ - SCx_SPI->SPICR &= (uint16_t)~((uint16_t)SC_SPICR_RXMODE); - - /* Set new RXMODE bit value */ - SCx_SPI->SPICR |= SPI_ReceiverMode; -} - -/** - * @brief Enables or disables the last byte repeat transmission feature - * for the specified SCx_SPI peripheral (Slave mode only). - * @param SCx_SPI: where x can be 1 or 2 to select the Serial controller peripheral. - * @param NewState: new state of the SCx_SPI peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_LastByteRepeatCmd(SC_SPI_TypeDef* SCx_SPI, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_PERIPH(SCx_SPI)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the last byte repeat feature for the selected SPI by setting - the RPTEN bit 0 in the SPICR register */ - SCx_SPI->SPICR |= SC_SPICR_RPTEN; - } - else - { - /* Disable the last byte repeat feature for the selected SPI by clearing - the RPTEN bit in the SPICR register */ - SCx_SPI->SPICR &= (uint16_t)~((uint16_t)SC_SPICR_RPTEN); - } -} - -/** - * @brief Enables or disables the specified SCx_SPI peripheral. - * @param SCx_SPI: where x can be 1 or 2 to select the Serial controller peripheral. - * @param NewState: new state of the SCx_SPI peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_Cmd(SC_SPI_TypeDef* SCx_SPI, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_PERIPH(SCx_SPI)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected SPI by setting the MODE bit 0 in the CR register */ - SCx_SPI->CR &= (uint16_t)~((uint16_t)SC_CR_MODE); - SCx_SPI->CR |= SC_CR_MODE_1; - } - else - { - /* Disable the selected SPI by clearing the MODE bits in the CR register */ - SCx_SPI->CR &= (uint16_t)~((uint16_t)SC_CR_MODE); - } -} - -/** - * @brief Enables or disables the specified SCx_SPI interrupts. - * @param SCx_IT: where x can be 1 or 2 to select the Serial controller peripheral. - * @param SPI_IT: specifies the SCx_SPI interrupt source to be enabled or disabled. - * This parameter can be one of the following values: - * @arg SPI_IT_UND: Underrun interrupt mask - * @arg SPI_IT_OVR: Overrun interrupt mask - * @arg SPI_IT_IDLE: Idle line detected interrupt mask - * @arg SPI_IT_TXE: Transmit data register empty interrupt mask - * @arg SPI_IT_RXNE: Data Register not empty interrupt mask - * @param NewState: new state of the specified SCx_SPI interrupt source. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_ITConfig(SC_IT_TypeDef* SCx_IT, uint32_t SPI_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_SPI_DMA_IT_PERIPH(SCx_IT)); - assert_param(IS_SPI_IT(SPI_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected SPI interrupt */ - SCx_IT->IER |= SPI_IT; - } - else - { - /* Disable the selected SPI interrupt */ - SCx_IT->IER &= (uint16_t)~((uint16_t)SPI_IT); - } -} - -/** - * @brief Trigger event configuration to handle the specified SCx_SPI interrupt. - * @param SCx_IT: where x can be 1 or 2 to select the Serial controller peripheral. - * @param SPI_IT: specifies the SCx_SPI interrupt to be configured. - * This parameter can be one of the following values: - * @arg SPI_IT_IDLE: Idle line detected interrupt - * @arg SPI_IT_TXE: Transmit data register empty interrupt - * @arg SPI_IT_RXNE: Data Register not empty interrupt - * @param TriggerEvent: Trigger event configuration of the specified SCx_SPI interrupt. - * This parameter can be one of the following values: - * @arg SC_TriggerEvent_Edge: The specified SCx_SPI interrupt will be generated on edge - * @arg SC_TriggerEvent_Level: The specified SCx_SPI interrupt will be generated on level - * @retval None - */ -void SPI_TriggerEventConfig(SC_IT_TypeDef* SCx_IT, uint32_t SPI_IT, uint32_t TriggerEvent) -{ - /* Check the parameters */ - assert_param(IS_I2C_SPI_DMA_IT_PERIPH(SCx_IT)); - assert_param(IS_SPI_TRIGGEREVENT_IT(SPI_IT)); - assert_param(IS_SC_TRIGGEREVENT(TriggerEvent)); - - if (TriggerEvent != SC_TriggerEvent_Edge) - { - /* The SPI_IT interrupt will be handled on level */ - SCx_IT->ICR |= SPI_IT; - } - else - { - /* The SPI_IT interrupt will be handled on edge */ - SCx_IT->ICR &= (uint16_t)~((uint16_t)SPI_IT); - } -} - -/** - * @brief Transmits a Data through the SCx_SPI peripheral. - * @param SCx_SPI: where x can be 1 or 2 to select the Serial controller peripheral. - * @param Data: Data to be transmitted. - * @retval None - */ -void SPI_SendData(SC_SPI_TypeDef* SCx_SPI, uint8_t Data) -{ - uint32_t scxbase = 0x00; - - /* Check the parameters */ - assert_param(IS_SPI_PERIPH(SCx_SPI)); - - scxbase = (uint32_t)SCx_SPI; - - *(__IO uint32_t *) scxbase = Data; -} - -/** - * @brief Returns the most recent received data by the SCx_SPI peripheral. - * @param SCx_SPI: where x can be 1 or 2 to select the Serial controller peripheral. - * @retval The value of the received data. - */ -uint8_t SPI_ReceiveData(SC_SPI_TypeDef* SCx_SPI) -{ - uint32_t scxbase = 0x00; - - /* Check the parameters */ - assert_param(IS_SPI_PERIPH(SCx_SPI)); - - scxbase = (uint32_t)SCx_SPI; - - return *(__IO uint32_t *) scxbase; -} - -/** - * @brief Checks whether the specified SCx_SPI flag is set or not. - * @param SCx_SPI: where x can be 1 or 2 to select the Serial controller peripheral. - * @param SPI_FLAG: specifies the SCx_SPI flag to check. - * This parameter can be one of the following values: - * @arg SPI_FLAG_OVR: OverRun Error flag. - * @arg SPI_FLAG_TXE: Transmit data register empty flag. - * @arg SPI_FLAG_RXNE: Receive data register not empty flag. - * @arg SPI_FLAG_IDLE: IDLE line flag. - * @retval The new state of SPI_FLAG (SET or RESET). - */ -FlagStatus SPI_GetFlagStatus(SC_SPI_TypeDef* SCx_SPI, uint32_t SPI_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_SPI_PERIPH(SCx_SPI)); - assert_param(IS_SPI_GET_FLAG(SPI_FLAG)); - - if ((SCx_SPI->SPISR & SPI_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Checks whether the specified SCx_SPI pending interrupt is set or not. - * @param SCx_IT: where x can be 1 or 2 to select the Serial controller peripheral. - * @param SPI_IT: specifies the SCx_SPI pending interrupt to check. - * This parameter can be one of the following values: - * @arg SPI_IT_UND: Underrun interrupt pending - * @arg SPI_IT_OVR: Overrun interrupt pending - * @arg SPI_IT_IDLE: Idle line detected interrupt pending - * @arg SPI_IT_TXE: Transmit data register empty interrupt pending - * @arg SPI_IT_RXNE: Data Register not empty interrupt pending - * @retval The new state of SPI_IT (SET or RESET). - */ -ITStatus SPI_GetITStatus(SC_IT_TypeDef* SCx_IT, uint32_t SPI_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_I2C_SPI_DMA_IT_PERIPH(SCx_IT)); - assert_param(IS_SPI_IT(SPI_IT)); - - enablestatus = (uint32_t)(SCx_IT->IER & SPI_IT); - if (((SCx_IT->ISR & SPI_IT) != (uint32_t)RESET) && enablestatus) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the SCx_SPI interrupt pending bits. - * @param SCx_IT: where x can be 1 to select the Serial controller peripheral. - * @param SPI_IT: specifies the SCx_SPI pending interrupt to check. - * This parameter can be one of the following values: - * @arg SPI_IT_UND: Underrun interrupt pending - * @arg SPI_IT_OVR: Overrun interrupt pending - * @arg SPI_IT_IDLE: Idle line detected interrupt pending - * @arg SPI_IT_TXE: Transmit data register empty interrupt pending - * @arg SPI_IT_RXNE: Data Register not empty interrupt pending - * @retval None - */ -void SPI_ClearITPendingBit(SC_IT_TypeDef* SCx_IT, uint32_t SPI_IT) -{ - /* Check the parameters */ - assert_param(IS_I2C_SPI_DMA_IT_PERIPH(SCx_IT)); - assert_param(IS_SPI_IT(SPI_IT)); - - SCx_IT->ISR = SPI_IT; -} - -/** - * @} - */ - -/** @defgroup SC_Group3 Inter-Integrated Circuit communication - * @brief inter-integrated circuit functions - * -@verbatim - =============================================================================== - ##### Inter-Integrated Circuit functions ##### - =============================================================================== - [..] This section provides a set of functions allowing to handles the Inter-Integrated - Circuit communication. - - (@) The SC1 and SC2 include an Inter-integrated circuit interface (I2C) master controller. - -*** Initialization and Configuration *** - ======================================= - - [..] The GPIO pins that can be assigned to I2C interface are listed in the following table: - +------------------------------------------------------------------+ - |Parameter | Direction | GPIO configuration | SC1 pin | SC2 pin | - |----------|-----------|--------------------|----------|-----------| - | SDA | In/Out | Alternate Output | PB1 | PA1 | - | | | (open drain) | | | - |----------|-----------|-------------------------------------------| - | SCL | In/Out | Alternate Output | PB2 | PA2 | - | | | (open drain) | | | - +------------------------------------------------------------------+ - - [..] For the Inter-Integrated Circuit mode only the Baud Rate parameter can be configured: - - [..] The I2C_Init() function follows the I2C configuration procedure (this procedure - is available in datasheet). - - [..] The generate START and STOP can be done respectively using I2C_GenerateSTART() and - I2C_GenerateSTOP() functions. - - [..] The command for the ACK generation can be done I2C_AcknowledgeConfig() function. - -*** Data transfers *** - ===================== - [..] To initiate a transmit segment, write the data to the SCx_DR data register, - then set the BTE bit in the SCx_I2CCR1 register, and finally wait until - the BTE bit is clear and the BTF bit in the SCx_I2CSR register, these steps - can be done using I2C_SendData() function. Alternatively to initiate the reception - set the BRE bit in the SCx_I2CCR1 register and keep waiting until the BRE bit - is clear and the BTF bit in the SCx_I2CSR register is set then read the - Rx buffered value, these steps can be done using I2C_ReceiveData() function. - - [..] The Master transmit address byte to select the slave device in transmitter - or in receiver mode can be done using the I2C_Send7bitAddress() function - - *** Interrupts and flags management *** - ======================================= - [..] This subsection provides also a set of functions allowing to configure the - I2C Interrupts sources, Requests and check or clear the flags or pending bits status. - The user should identify which mode will be used in his application to - manage the communication: Polling mode, Interrupt mode. - - [..] In Polling Mode, the I2C communication can be managed by 4 flags: - (#) I2C_FLAG_NACK: to indicate the status of the not acknowledge flag. - (#) I2C_FLAG_BTF: to indicate the status of the byte transfer finished flag. - (#) I2C_FLAG_BRF: to indicate the status of the byte receive finished flag. - (#) I2C_FLAG_CMDFIN: to indicate the status of the command finished flag. - - [..] In this Mode it is advised to use the following functions: - (+) FlagStatus I2C_GetFlagStatus(SC_I2C_TypeDef* SCx_I2C, uint32_t I2C_FLAG). - [..] In this mode all the I2C flags are cleared by hardware. - - *** Interrupt Mode *** - ====================== - [..] In Interrupt Mode, the I2C communication can be managed by 4 interrupt sources - and 4 pending bits: - - [..] Interrupt Source: - (#) I2C_IT_NACK: specifies the interrupt source for the not acknowledge interrupt. - (#) I2C_IT_CMDFIN: specifies the interrupt source for the command finished interrupt. - (#) I2C_IT_BTF: specifies the interrupt source for the byte transfer finished interrupt. - (#) I2C_IT_BRF: specifies the interrupt source for the byte receive finished interrupt. - - [..] Pending Bits: - (#) I2C_IT_NACK: to indicate the status of not acknowledge pending interrupt. - (#) I2C_IT_CMDFIN: to indicate the status of command finished pending interrupt. - (#) I2C_IT_BTF: to indicate the status of byte transfer finished pending interrupt. - (#) I2C_IT_BRF: to indicate the status of byte receive finished pending interrupt. - - [..] In this Mode it is advised to use the following functions: - (+) void I2C_ClearITPendingBit(SC_IT_TypeDef* SCx_IT, uint32_t I2C_IT). - (+) ITStatus I2C_GetITStatus(SC_IT_TypeDef* SCx_IT, uint32_t I2C_IT). - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the SCx_I2C peripheral registers to their default reset values. - * @param SCx_I2C: where x can be 1 or 2 to select the Serial controller peripheral. - * @retval None - */ -void I2C_DeInit(SC_I2C_TypeDef* SCx_I2C) -{ - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(SCx_I2C)); - - SCx_I2C->CR = 0; - SCx_I2C->I2CCR1 = 0; - SCx_I2C->I2CCR2 = 0; - SCx_I2C->CRR1 = 0; - SCx_I2C->CRR2 = 0; -} - -/** - * @brief Initializes the SCx_I2C peripheral according to the specified - * parameters in the I2C_InitStruct. - * @param SCx_I2C: where x can be 1 or 2 to select the Serial controller peripheral. - * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that - * contains the configuration information for the specified SCx_I2C peripheral. - * @retval None - */ -void I2C_Init(SC_I2C_TypeDef* SCx_I2C, I2C_InitTypeDef* I2C_InitStruct) -{ - uint8_t expvalue = 0, lin = 0, tmpexp = 0, tmplin = 0, idx = 0; - uint32_t tempclockrate = 0, clockrate = 0, power = 0; - - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(SCx_I2C)); - assert_param(IS_I2C_CLOCK_RATE(I2C_InitStruct->I2C_ClockRate)); - - /*---------------------------- SCx_CRRx Configuration ----------------------*/ - /*---------------------------- SCx_CRRx Configuration ----------------------*/ - for(lin = 0x00; lin < 16; lin++) - { - for(expvalue = 0x00; expvalue < 16; expvalue++) - { - power = 0x01; - for (idx=1; idx <= expvalue; idx++) - { - power*=2; - } - tempclockrate = power * (uint32_t)(lin + 1); - - if (tempclockrate == ((uint32_t)((uint32_t)CLK_GetClocksFreq()/(uint32_t)(2*(I2C_InitStruct->I2C_ClockRate))))) - { - SCx_I2C->CRR1 = (uint32_t)lin; - SCx_I2C->CRR2 = (uint32_t)expvalue; - } - else - { - /* Check the clock rate error and write to CRRx */ - if((ABS((int32_t)tempclockrate - (int32_t)(CLK_GetClocksFreq()/(2*(I2C_InitStruct->I2C_ClockRate))))) < (ABS((int32_t)clockrate - (int32_t)(CLK_GetClocksFreq()/(2*(I2C_InitStruct->I2C_ClockRate)))))) - { - clockrate = tempclockrate; - tmplin = lin; - tmpexp = expvalue; - } - } - } - } - - SCx_I2C->CRR1 = (uint32_t)tmplin; - SCx_I2C->CRR2 = (uint32_t)tmpexp; -} - -/** - * @brief Fills each I2C_InitStruct member with its default value. - * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure which will be initialized. - * @retval None - */ -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) -{ - /*--------------- Reset I2C init structure parameters values ---------------*/ - - /* Initialize the I2C_ClockRate member */ - I2C_InitStruct->I2C_ClockRate = 400000; -} - -/** - * @brief Generates SCx_I2C communication START condition. - * @param SCx_I2C: where x can be 1 or 2 to select the Serial controller peripheral. - * @retval None - */ -void I2C_GenerateSTART(SC_I2C_TypeDef* SCx_I2C) -{ - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(SCx_I2C)); - - /* Generate a START condition */ - SCx_I2C->I2CCR1 |= SC_I2CCR1_START; -} - -/** - * @brief Generates SCx_I2C communication STOP condition. - * @param SCx_I2C: where x can be 1 or 2 to select the Serial controller peripheral. - * @retval None - */ -void I2C_GenerateSTOP(SC_I2C_TypeDef* SCx_I2C) -{ - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(SCx_I2C)); - - /* Generate a STOP condition */ - SCx_I2C->I2CCR1 |= SC_I2CCR1_STOP; -} - -/** - * @brief Generates SCx_I2C communication Acknowledge. - * @param SCx_I2C: where x can be 1 or 2 to select the Serial controller peripheral. - * @param NewState: new state of the Acknowledge. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_AcknowledgeConfig(SC_I2C_TypeDef* SCx_I2C, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(SCx_I2C)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable ACK generation */ - SCx_I2C->I2CCR2 |= SC_I2CCR2_ACK; - } - else - { - /* Enable NACK generation */ - SCx_I2C->I2CCR2 &= (uint32_t)~((uint32_t)SC_I2CCR2_ACK); - } -} - -/** - * @brief Transmits the address byte to select the slave device. - * @param SCx_I2C: where x can be 1 or 2 to select the Serial controller peripheral. - * @param Address: specifies the slave address which will be transmitted - * @param I2C_Direction: specifies whether the SCx_I2C device will be a - * Transmitter or a Receiver. This parameter can be one of the following values - * @arg I2C_Direction_Transmitter: Transmitter mode - * @arg I2C_Direction_Receiver: Receiver mode - * @retval None. - */ -void I2C_Send7bitAddress(SC_I2C_TypeDef* SCx_I2C, uint8_t Address, uint8_t I2C_Direction) -{ - uint32_t scxbase = 0x00; - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(SCx_I2C)); - assert_param(IS_I2C_DIRECTION(I2C_Direction)); - /* Test on the direction to set/reset the read/write bit */ - if (I2C_Direction != I2C_Direction_Transmitter) - { - /* Set the address bit0 for read */ - Address |= OAR1_ADD0_Set; - } - else - { - /* Reset the address bit0 for write */ - Address &= OAR1_ADD0_Reset; - } - - scxbase = (uint32_t)SCx_I2C; - /* Send the address */ - *(__IO uint32_t *) scxbase = Address; - - /* Enable the byte Send */ - SCx_I2C->I2CCR1 |= SC_I2CCR1_BTE; - - while ((SCx_I2C->I2CCR1 & SC_I2CCR1_BTE) != 0x00) - {} -} - -/** - * @brief Transmits a Data through the SCx_I2C peripheral. - * @param SCx_I2C: where x can be 1 or 2 to select the Serial controller peripheral. - * @param Data: Data to be transmitted. - * @retval None - */ -void I2C_SendData(SC_I2C_TypeDef* SCx_I2C, uint8_t Data) -{ - uint32_t scxbase = 0x00; - - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(SCx_I2C)); - - scxbase = (uint32_t)SCx_I2C; - - *(__IO uint32_t *) scxbase = Data; - - /* Enable the byte Send */ - SCx_I2C->I2CCR1 |= SC_I2CCR1_BTE; - - while ((SCx_I2C->I2CCR1 & SC_I2CCR1_BTE) != 0x00) - {} - while ((SCx_I2C->I2CSR & SC_I2CSR_BTF) == 0x00) - {} -} - -/** - * @brief Returns the most recent received data by the SCx_I2C peripheral. - * @param SCx_I2C: where x can be 1 or 2 to select the Serial controller peripheral. - * @retval The value of the received data. - */ -uint8_t I2C_ReceiveData(SC_I2C_TypeDef* SCx_I2C) -{ - uint32_t scxbase = 0x00; - - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(SCx_I2C)); - - scxbase = (uint32_t)SCx_I2C; - - /* Enable the byte Receive */ - SCx_I2C->I2CCR1 |= SC_I2CCR1_BRE; - - while ((SCx_I2C->I2CCR1 & SC_I2CCR1_BRE) != 0x00) - {} - while ((SCx_I2C->I2CSR & SC_I2CSR_BRF) == 0x00) - {} - - return *(__IO uint32_t *) scxbase; -} - -/** - * @brief Enables or disables the specified SCx_I2C peripheral. - * @param SCx_I2C: where x can be 1 or 2 to select the Serial controller peripheral. - * @param NewState: new state of the SCx_I2C peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_Cmd(SC_I2C_TypeDef* SCx_I2C, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(SCx_I2C)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected I2C by setting the MODE bits in the CR register */ - SCx_I2C->CR |= SC_CR_MODE; - } - else - { - /* Disable the selected I2C by clearing the MODE bits in the CR register */ - SCx_I2C->CR &= (uint16_t)~((uint16_t)SC_CR_MODE); - } -} - -/** - * @brief Enables or disables the specified SCx_I2C interrupts. - * @param SCx_IT: where x can be 1 or 2 to select the Serial controller peripheral. - * @param I2C_IT: specifies the SCx_I2C interrupt source to be enabled or disabled. - * This parameter can be one of the following values: - * @arg I2C_IT_NACK: Not acknowledge interrupt mask - * @arg I2C_IT_CMDFIN: Command finished interrupt mask - * @arg I2C_IT_BTF: Byte transfer finished interrupt mask - * @arg I2C_IT_BRF: Byte receive finished interrupt mask - * @param NewState: new state of the specified SCx_I2C interrupt source. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ITConfig(SC_IT_TypeDef* SCx_IT, uint32_t I2C_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_SPI_DMA_IT_PERIPH(SCx_IT)); - assert_param(IS_I2C_IT(I2C_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected I2C interrupt */ - SCx_IT->IER |= I2C_IT; - } - else - { - /* Disable the selected I2C interrupt */ - SCx_IT->IER &= (uint16_t)~((uint16_t)I2C_IT); - } -} - -/** - * @brief Checks whether the specified I2C flag is set or not. - * @param SCx_I2C: where x can be 1 or 2 to select the Serial controller peripheral. - * @param I2C_FLAG: specifies the SCx_I2C flag to check. - * This parameter can be one of the following values: - * @arg I2C_FLAG_NACK: Not acknowledge flag - * @arg I2C_FLAG_BTF: Byte transfer finished flag - * @arg I2C_FLAG_BRF: Byte receive finished flag - * @arg I2C_FLAG_CMDFIN: Command finished flag - * @retval The new state of I2C_FLAG (SET or RESET). - */ -FlagStatus I2C_GetFlagStatus(SC_I2C_TypeDef* SCx_I2C, uint32_t I2C_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_I2C_PERIPH(SCx_I2C)); - assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); - - if ((SCx_I2C->I2CSR & I2C_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Checks whether the specified SCx_I2C pending interrupt is set or not. - * @param SCx_IT: where x can be 1 or 2 to select the Serial controller peripheral. - * @param I2C_IT: specifies the SCx_I2C interrupt pending to check. - * This parameter can be one of the following values: - * @arg I2C_IT_NACK: Not acknowledge interrupt pending - * @arg I2C_IT_CMDFIN: Command finished interrupt pending - * @arg I2C_IT_BTF: Byte transfer finished interrupt pending - * @arg I2C_IT_BRF: Byte receive finished interrupt pending - * @retval The new state of I2C_IT (SET or RESET). - */ -ITStatus I2C_GetITStatus(SC_IT_TypeDef* SCx_IT, uint32_t I2C_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_I2C_SPI_DMA_IT_PERIPH(SCx_IT)); - assert_param(IS_I2C_IT(I2C_IT)); - - enablestatus = (uint32_t)(SCx_IT->IER & I2C_IT); - if (((SCx_IT->ISR & I2C_IT) != (uint32_t)RESET) && enablestatus) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the SCx_I2C interrupt pending bits. - * @param SCx_IT: where x can be 1 to select the Serial controller peripheral. - * @param I2C_IT: specifies the SCx_I2C interrupt pending to check. - * This parameter can be one of the following values: - * @arg I2C_IT_NACK: Not acknowledge interrupt pending - * @arg I2C_IT_CMDFIN: Command finished interrupt pending - * @arg I2C_IT_BTF: Byte transfer finished interrupt pending - * @arg I2C_IT_BRF: Byte receive finished interrupt pending - * @retval None - */ -void I2C_ClearITPendingBit(SC_IT_TypeDef* SCx_IT, uint32_t I2C_IT) -{ - /* Check the parameters */ - assert_param(IS_I2C_SPI_DMA_IT_PERIPH(SCx_IT)); - assert_param(IS_I2C_IT(I2C_IT)); - - SCx_IT->ISR = I2C_IT; -} - -/** - * @} - */ - -/** @defgroup SC_Group4 DMA transfers management - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - ##### DMA transfers management functions ##### - =============================================================================== - [..] This section provides a set of functions that can be used only in DMA mode. - - (@) The SC1 and SC2 include a DMA controller that can be used to manage the UART - and SPI communications. - -*** Initialization and Configuration *** - ======================================= - [..] For the DMA mode these parameters can be configured: - (+) Begin address buffer A. - (+) End address buffer A. - (+) Begin address buffer B. - (+) End address buffer B. - - [..] The DMA_Init() function follows the DMA configuration procedure. - -*** Data transfers *** - ===================== - [..] In DMA Mode, the UART and SPI communications can be managed by 4 DMA Channel - requests: - (#) DMA_ChannelLoad_BTx: specifies the DMA transmit channel buffer B transfer request. - (#) DMA_ChannelLoad_ATx: specifies the DMA transmit channel buffer A transfer request. - (#) DMA_ChannelLoad_BRx: specifies the DMA receive channel buffer B transfer request. - (#) DMA_ChannelLoad_ARx: specifies the DMA receive channel buffer A transfer request. - [..] In this Mode it is advised to use the following function to load and enables the specified DMA channel: - (+) void SC_DMA_ChannelLoadEnable(SC_DMA_TypeDef* SCx_DMA, uint32_t Channelxy). - -*** Interrupts and flags management *** - ======================================= - [..] This subsection provides also a set of functions allowing to configure the - DMA Interrupts sources, Requests and check or clear the flags or pending bits status. - The user should identify which mode will be used in his application to - manage the communication: Polling mode, Interrupt mode. - - [..] In Polling Mode, the DMA communication can be managed by 4 flags: - (#) DMA_FLAG_RXAACK: to indicate the status of the DMA receive buffer A acknowledge flag. - (#) DMA_FLAG_RXBACK: to indicate the status of the DMA receive buffer B acknowledge flag. - (#) DMA_FLAG_TXAACK: to indicate the status of the DMA transmit buffer A acknowledge flag. - (#) DMA_FLAG_TXBACK: to indicate the status of the DMA transmit buffer B acknowledge flag. - (#) DMA_FLAG_OVRA: to indicate the status of the DMA buffer B overrun flag. - (#) DMA_FLAG_OVRB: to indicate the status of the DMA buffer B overrun flag. - (#) DMA_FLAG_PEA: to indicate the status of the DMA Parity error A flag. - (#) DMA_FLAG_PEB: to indicate the status of the DMA Parity error B flag. - (#) DMA_FLAG_FEA: to indicate the status of the DMA Frame error A flag. - (#) DMA_FLAG_FEB: to indicate the status of the DMA Frame error B flag. - (#) DMA_FLAG_NSSS: to indicate the status of the status of the receive count flag. - [..] In this Mode it is advised to use the following functions: - (+) FlagStatus SC_DMA_GetFlagStatus(SC_DMA_TypeDef* SCx_DMA, uint32_t DMA_FLAG). - [..] In this mode all the DMA flags are cleared by hardware. - - *** Interrupt Mode *** - ====================== - [..] In Interrupt Mode, the DMA communication can be managed by 4 interrupt sources - and 4 pending bits: - - [..] Interrupt Source: - (#) DMA_IT_TXULODB: specifies the interrupt source for the transmit buffer B unloaded interrupt. - (#) DMA_IT_TXULODA: specifies the interrupt source for the transmit buffer A unloaded interrupt. - (#) DMA_IT_RXULODB: specifies the interrupt source for the receive buffer B unloaded interrupt. - (#) DMA_IT_RXULODA: specifies the interrupt source for the receive buffer A unloaded interrupt. - - [..] Pending Bits: - (#) DMA_IT_TXULODB: to indicate the status of transmit buffer B unloaded pending interrupt. - (#) DMA_IT_TXULODA: to indicate the status of transmit buffer A unloaded pending interrupt. - (#) DMA_IT_RXULODB: to indicate the status of receive buffer B unloaded pending interrupt. - (#) DMA_IT_RXULODA: to indicate the status of receive buffer A unloaded pending interrupt. - - [..] In this Mode it is advised to use the following functions: - (+) ITStatus SC_DMA_GetITStatus(SC_IT_TypeDef* SCx_IT, uint32_t DMA_IT). - (+) SC_DMA_ClearITPendingBit(SC_IT_TypeDef* SCx_IT, uint32_t DMA_IT). - -@endverbatim - * @{ - */ - -/** - * @brief Reset the specified SCx_DMA Channely buffer addresses. - * @param SCx_DMA: where x can be 1 or 2 to select the Serial controller peripheral. - * @param Channely: specifies the SCx_DMA channel to be enabled. - * This parameter can be one of the following values: - * @arg DMA_ChannelReset_Tx: DMA reset transmit channels mask - * @arg DMA_ChannelReset_Rx: DMA reset receive channels mask - * @retval None - */ -void SC_DMA_ChannelReset(SC_DMA_TypeDef* SCx_DMA, uint32_t Channely) -{ - /* Check the parameters */ - assert_param(IS_DMA_PERIPH(SCx_DMA)); - assert_param(IS_DMA_CHANNEL_RESET(Channely)); - - /* Reset the selected SCx_DMA Channelx */ - SCx_DMA->DMACR |= Channely; -} - -/** - * @brief Initializes the SCx_DMA Channely according to the specified - * parameters in the DMA_InitStruct. - * @param SCx_DMA_Channely: where x can be 1 or 2 to select the SCx_DMA and - * y can be Tx or Rx to select the SCx_DMA Channel. - * @param SC_DMA_InitStruct: pointer to a DMA_InitTypeDef structure that - * contains the configuration information for the specified DMA Channel. - * @retval None - */ -void SC_DMA_Init(SC_DMA_Channel_TypeDef* SCx_DMA_Channely, SC_DMA_InitTypeDef* SC_DMA_InitStruct) -{ - /* Check the parameters */ - assert_param(IS_DMA_CHANNEL_PERIPH(SCx_DMA_Channely)); - assert_param(IS_DMA_VALID_ADDRESS(SC_DMA_InitStruct->DMA_BeginAddrA)); - assert_param(IS_DMA_VALID_ADDRESS(SC_DMA_InitStruct->DMA_EndAddrA)); - assert_param(IS_DMA_VALID_ADDRESS(SC_DMA_InitStruct->DMA_BeginAddrB)); - assert_param(IS_DMA_VALID_ADDRESS(SC_DMA_InitStruct->DMA_EndAddrB)); - -/*---------------------- SCx_DMA Channely DMABEGADDAR Configuration ----------*/ - /* Write to SCx_DMA Channely Begin address A register */ - SCx_DMA_Channely->DMABEGADDAR = SC_DMA_InitStruct->DMA_BeginAddrA; - - /*---------------------- SCx_DMA Channely DMAENDADDAR Configuration --------*/ - /* Write to SCx_DMA Channely end address A register */ - SCx_DMA_Channely->DMAENDADDAR = SC_DMA_InitStruct->DMA_EndAddrA; - - /*---------------------- SCx_DMA Channely DMABEGADDBR Configuration --------*/ - /* Write to SCx_DMA Channely Begin address B register */ - SCx_DMA_Channely->DMABEGADDBR = SC_DMA_InitStruct->DMA_BeginAddrB; - - /*---------------------- SCx_DMA Channely DMAENDADDBR Configuration --------*/ - /* Write to SCx_DMA Channely end address B register */ - SCx_DMA_Channely->DMAENDADDBR = SC_DMA_InitStruct->DMA_EndAddrB; -} - -/** - * @brief Fills each DMA_InitStruct member with its default value. - * @param SC_DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will be initialized. - * @retval None - */ -void SC_DMA_StructInit(SC_DMA_InitTypeDef* SC_DMA_InitStruct) -{ - /*--------------- Reset DMA init structure parameters values ---------------*/ - /* Initialize the SCx_DMA_Channely begin address A member */ - SC_DMA_InitStruct->DMA_BeginAddrA = 0x20000000; - /* Initialize the SCx_DMA_Channely end address A member */ - SC_DMA_InitStruct->DMA_EndAddrA = 0x20000000; - /* Initialize the SCx_DMA_Channely begin address B member */ - SC_DMA_InitStruct->DMA_BeginAddrB = 0x20000000; - /* Initialize the SCx_DMA_Channely end address B member */ - SC_DMA_InitStruct->DMA_EndAddrB = 0x20000000; -} - -/** - * @brief Enables or disables the specified SCx_DMA interrupts. - * @param SCx_IT: where x can be 1 or 2 to select the Serial controller peripheral. - * @param DMA_IT: specifies the SCx_DMA interrupt source to be enabled or disabled. - * This parameter can be one of the following values: - * @arg DMA_IT_TXULODB: DMA transmit buffer B unloaded interrupt mask - * @arg DMA_IT_TXULODA: DMA transmit buffer A unloaded interrupt mask - * @arg DMA_IT_RXULODB: DMA receive buffer B unloaded interrupt mask - * @arg DMA_IT_RXULODA: DMA receive buffer A unloaded interrupt mask - * @param NewState: new state of the specified SCx_DMA interrupt source. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SC_DMA_ITConfig(SC_IT_TypeDef* SCx_IT, uint32_t DMA_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_SPI_DMA_IT_PERIPH(SCx_IT)); - assert_param(IS_DMA_IT(DMA_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DMA interrupt */ - SCx_IT->IER |= DMA_IT; - } - else - { - /* Disable the selected DMA interrupt */ - SCx_IT->IER &= (uint16_t)~((uint16_t)DMA_IT); - } -} - -/** - * @brief Load and Enables the specified SCx_DMA Channelxy buffers addresses. - * @param SCx_DMA: where x can be 1 or 2 to select the Serial controller peripheral. - * @param Channelxy: specifies the SCx_DMA channel to be enabled. - * This parameter can be one of the following values: - * @arg DMA_ChannelLoad_BTx: DMA transmit channel buffer B mask - * @arg DMA_ChannelLoad_ATx: DMA transmit channel buffer A mask - * @arg DMA_ChannelLoad_BRx: DMA receive channel buffer B mask - * @arg DMA_ChannelLoad_ARx: DMA receive channel buffer A mask - * @retval None - */ -void SC_DMA_ChannelLoadEnable(SC_DMA_TypeDef* SCx_DMA, uint32_t Channelxy) -{ - /* Check the parameters */ - assert_param(IS_DMA_PERIPH(SCx_DMA)); - assert_param(IS_DMA_CHANNEL_LOAD(Channelxy)); - - /* Load the selected SCx_DMA Channelxy buffer addresses and allow the DMA controller - to start processing */ - SCx_DMA->DMACR |= Channelxy; -} - -/** - * @brief Returns the most recent value for the specific SCx_DMA counter register. - * @param SCx_DMA: where x can be 1 or 2 to select the Serial controller peripheral. - * @param Counter: specifies the SCx_DMA counter register to be read. - * This parameter can be one of the following values: - * @arg DMA_Counter_RXCNTA: DMA receive counter A register - * @arg DMA_Counter_RXCNTB: DMA receive counter B register - * @arg DMA_Counter_TXCNT: DMA transmit counter register - * @arg DMA_Counter_RXCNTSAVED: DMA receive counter saved register - * @retval The DMA register counter value. - */ -uint32_t SC_DMA_GetCounter(SC_DMA_TypeDef* SCx_DMA, uint32_t Counter) -{ - uint32_t scxbase = 0x00; - - /* Check the parameters */ - assert_param(IS_DMA_PERIPH(SCx_DMA)); - assert_param(IS_DMA_COUNTER(Counter)); - - scxbase = (uint32_t)SCx_DMA; - scxbase += Counter; - - return *(__IO uint32_t *) scxbase; -} - -/** - * @brief Returns the specified SCx_DMA receive error register. - * @param SCx_DMA: where x can be 1 or 2 to select the Serial controller peripheral. - * @param RegisterError: specifies the SCx_DMA receiver error register to be read. - * This parameter can be one of the following values: - * @arg DMA_ReceiverError_CNTA: DMA receive error register A - * @arg DMA_ReceiverError_CNTB: DMA receive error register B - * @retval The DMA receive error register value. - */ -uint32_t SC_DMA_GetReceiverErrorOffset(SC_DMA_TypeDef* SCx_DMA, uint32_t RegisterError) -{ - uint32_t scxbase = 0x00; - - /* Check the parameters */ - assert_param(IS_DMA_PERIPH(SCx_DMA)); - assert_param(IS_DMA_RECEIVER_ERROR(RegisterError)); - - scxbase = (uint32_t)SCx_DMA; - scxbase += RegisterError; - - return *(__IO uint32_t *) scxbase; -} - -/** - * @brief Checks whether the specified DMA flag is set or not. - * @param SCx_DMA: where x can be 1 or 2 to select the Serial controller peripheral. - * @param DMA_FLAG: specifies the SCx_DMA flag to check. - * This parameter can be one of the following values: - * @arg DMA_FLAG_RXAACK: DMA receive buffer A acknowledge flag - * @arg DMA_FLAG_RXBACK: DMA receive buffer B acknowledge flag - * @arg DMA_FLAG_TXAACK: DMA transmit buffer A acknowledge flag - * @arg DMA_FLAG_TXBACK: DMA transmit buffer B acknowledge flag - * @arg DMA_FLAG_OVRA: DMA buffer B overrun flag - * @arg DMA_FLAG_OVRB: DMA buffer B overrun flag - * @arg DMA_FLAG_PEA: DMA Parity error A flag - * @arg DMA_FLAG_PEB: DMA Parity error B flag - * @arg DMA_FLAG_FEA: DMA Frame error A flag - * @arg DMA_FLAG_FEB: DMA Frame error B flag - * @arg DMA_FLAG_NSSS: DMA Status of the receive count flag - * @retval The new state of DMA_FLAG (SET or RESET). - */ -FlagStatus SC_DMA_GetFlagStatus(SC_DMA_TypeDef* SCx_DMA, uint32_t DMA_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_DMA_PERIPH(SCx_DMA)); - assert_param(IS_DMA_FLAG(DMA_FLAG)); - - if ((SCx_DMA->DMASR & DMA_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Checks whether the specified SCx_DMA pending interrupt is set or not. - * @param SCx_IT: where x can be 1 or 2 to select the Serial controller peripheral. - * @param DMA_IT: specifies the SCx_DMA interrupt pending to check. - * This parameter can be one of the following values: - * @arg DMA_IT_TXULODB: DMA transmit buffer B unloaded interrupt pending - * @arg DMA_IT_TXULODA: DMA transmit buffer A unloaded interrupt pending - * @arg DMA_IT_RXULODB: DMA receive buffer B unloaded interrupt pending - * @arg DMA_IT_RXULODA: DMA receive buffer A unloaded interrupt pending - * @retval The new state of DMA_IT (SET or RESET). - */ -ITStatus SC_DMA_GetITStatus(SC_IT_TypeDef* SCx_IT, uint32_t DMA_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_I2C_SPI_DMA_IT_PERIPH(SCx_IT)); - assert_param(IS_DMA_IT(DMA_IT)); - - enablestatus = (uint32_t)(SCx_IT->IER & DMA_IT); - if (((SCx_IT->ISR & DMA_IT) != (uint32_t)RESET) && enablestatus) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the SCx_DMA interrupt pending bits. - * @param SCx_IT: where x can be 1 to select the Serial controller peripheral. - * @param DMA_IT: specifies the SCx_DMA interrupt pending to check. - * This parameter can be one of the following values: - * @arg DMA_IT_TXULODB: DMA transmit buffer B unloaded interrupt pending - * @arg DMA_IT_TXULODA: DMA transmit buffer A unloaded interrupt pending - * @arg DMA_IT_RXULODB: DMA receive buffer B unloaded interrupt pending - * @arg DMA_IT_RXULODA: DMA receive buffer A unloaded interrupt pending - * @retval None - */ -void SC_DMA_ClearITPendingBit(SC_IT_TypeDef* SCx_IT, uint32_t DMA_IT) -{ - /* Check the parameters */ - assert_param(IS_I2C_SPI_DMA_IT_PERIPH(SCx_IT)); - assert_param(IS_DMA_IT(DMA_IT)); - - SCx_IT->ISR = DMA_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_slptim.c b/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_slptim.c deleted file mode 100644 index 299a062..0000000 --- a/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_slptim.c +++ /dev/null @@ -1,445 +0,0 @@ -/** - ****************************************************************************** - * @file stm32w108xx_slptim.c - * @author MCD Application Team - * @version V1.0.1 - * @date 30-November-2012 - * @brief This file provides firmware functions to manage the Sleep Timer - * peripheral. - * - * @verbatim - * - =============================================================================== - ##### SLPTIM features ##### - =============================================================================== - [..] The sleep timer is dedicated to system timing and waking from sleep at - specific times. - [..] The sleep timer can use either the calibrated 1 kHz reference(CLK1K), - or the 32 kHz crystal clock (CLK32K). The default clock source is - the internal 1 kHz clock. - [..] The sleep timer has a prescaler that allows for very long periods of - sleep to be timed. - [..] The timer provides two compare outputs and wrap detection, all of which - can be used to generate an interrupt or a wake up event. - [..] The sleep timer is paused when the debugger halts the ARM Cortex-M3. - - - ##### How to use this driver ##### - =============================================================================== - [..] This driver provides functions to configure and program the Sleep Timer - These functions are split in 2 groups: - (#) SLPTIM management functions: this group includes all needed functions - to configure the Sleep Timer. - (++) Enable/Disable the counter. - (++) Get counter. - (++) Select clock to be used as reference. - (++) Set/Get compare (A or B) values. - (#) Interrupts and flags management functions: this group includes all needed - functions to manage interrupts: - (++) Enables or disables the specified SLPTIM interrupts. - (++) Checks whether the specified SLPTIM flag is set or not. - (++) Clears the specified SLPTIM flag. - - @endverbatim - * - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2012 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32w108xx_slptim.h" - -/** @addtogroup STM32W108xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup SLPTIM - * @brief SLPTIM driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SLPTIM_Private_Functions - * @{ - */ - -/** @defgroup SLPTIM_Group1 SLPTIM management functions - * @brief SLPTIM management functions - * -@verbatim - =============================================================================== - ##### SLPTIM management functions ##### - =============================================================================== - [..] To use the Sleep Timer: - (#) Fill the SLPTIM_InitStruct with the desired parameters. - This must be done while the sleep timer is disabled. - (#) Call the SLPTIM_Cmd(ENABLE) function to enable the TIM counter. - (#) Enable the clock to be used as reference by calling SLPTIM_ClockConfig() - function. - - [..] - (@) All other functions can be used seperatly to set compareA or compareB value, - to get counter value... - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the SLPTIM peripheral registers to their default reset values. - * @retval None - * - */ -void SLPTIM_DeInit(void) -{ - SLPTMR->CR = 0x00000400; - SLPTMR->CMPAL = 0x0000FFFF; - SLPTMR->CMPAH = 0x0000FFFF; - SLPTMR->CMPBL = 0x0000FFFF; - SLPTMR->CMPBH = 0x0000FFFF; - SLPTMR->ISR = 0x00000007; - SLPTMR->IER = 0x00000000; -} - -/** - * @brief Initializes the SLPTIM Time peripheral according to - * the specified parameters in the SLPTIM_InitStruct. - * @param SLPTIM_InitStruct: pointer to a SLPTIM_InitTypeDef - * structure that contains the configuration information for - * the specified TIM peripheral. - * @retval None - */ -void SLPTIM_Init(SLPTIM_InitTypeDef* SLPTIM_InitStruct) -{ - uint32_t tmpcr = 0; - - /* Check the parameters */ - assert_param(IS_SLPTIM_COUNTER_MODE(SLPTIM_InitStruct->SLPTIM_CounterMode)); - assert_param(IS_SLPTIM_GET_CLKSEL(SLPTIM_InitStruct->SLPTIM_Clock)); - assert_param(IS_SLPTIM_CLKDIV(SLPTIM_InitStruct->SLPTIM_Prescaler)); - assert_param(IS_SLPTIM_DBGMODE(SLPTIM_InitStruct->SLPTIM_DebugMode)); - - tmpcr = SLPTMR->CR; - - /* Set the Sleep Timer Clock */ - tmpcr &= (uint32_t)~SLPTMR_CR_CLKSEL; - tmpcr |= (uint32_t)SLPTIM_InitStruct->SLPTIM_Clock; - - /* Set the Prescaler value */ - tmpcr &= (uint32_t)~SLPTMR_CR_PSC; - tmpcr |= (uint32_t)SLPTIM_InitStruct->SLPTIM_Prescaler; - - /* Selects the timer's mode during debug */ - tmpcr &= (uint32_t)~SLPTMR_CR_DBGP; - tmpcr |= (uint32_t)SLPTIM_InitStruct->SLPTIM_DebugMode; - - /* Selects the Counter Mode */ - tmpcr &= (uint32_t)~SLPTMR_CR_REVERSE; - tmpcr |= (uint32_t)SLPTIM_InitStruct->SLPTIM_CounterMode; - - SLPTMR->CR = tmpcr; -} - -/** - * @brief Fills each SLPTIM_InitStruct member with its default value. - * @param SLPTIM_InitStruct : pointer to a SLPTIM_InitTypeDef - * structure which will be initialized. - * @retval None - */ -void SLPTIM_StructInit(SLPTIM_InitTypeDef* SLPTIM_InitStruct) -{ - /* Set the default configuration */ - SLPTIM_InitStruct->SLPTIM_Clock = SLPTIM_CLK_1KHZ; - SLPTIM_InitStruct->SLPTIM_Prescaler = SLPTIM_CLK_DIV0; - SLPTIM_InitStruct->SLPTIM_DebugMode = SLPTIM_DBGRUN; - SLPTIM_InitStruct->SLPTIM_CounterMode = SLPTIM_CountForward; -} - -/** - * @brief Enables or disables the Sleep Timer. - * @param NewState: new state of the Sleep Timer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SLPTIM_Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Sleep Timer */ - SLPTMR->CR |= (uint32_t)SLPTMR_CR_EN; - } - else - { - /* Disable the clock */ - SLPTMR->CR &= (uint32_t)~SLPTMR_CR_EN; - } -} - -/** - * @brief Sets the SLPTIM Compare A Register value - * @param CompareA: specifies the Compare A register new value. - * @retval None - */ -void SLPTIM_SetCompareA(uint32_t CompareA) -{ - /* Set the Compare A Register value */ - SLPTMR->CMPAL = (uint32_t)(CompareA & 0x0000FFFF); - SLPTMR->CMPAH = (uint32_t)((CompareA >> 16) & 0x0000FFFF); -} - -/** - * @brief Sets the SLPTIM Compare B Register value - * @param CompareB: specifies the Compare B register new value. - * @retval None - */ -void SLPTIM_SetCompareB(uint32_t CompareB) -{ - /* Set the Compare B Register value */ - SLPTMR->CMPBL = (uint32_t)(CompareB & 0x0000FFFF); - SLPTMR->CMPBH = (uint32_t)((CompareB >> 16) & 0x0000FFFF); -} - -/** - * @brief Gets the SLPTIM Counter value. - * @retval Counter Register value. - */ -uint32_t SLPTIM_GetCounter(void) -{ - uint32_t counter = 0; - - /* Get the Counter Register value */ - counter = (uint32_t)(SLPTMR->CNTH << 16); - counter |= (uint32_t)SLPTMR->CNTL; - - return counter; -} - -/** - * @brief Gets the SLPTIM Counter high value. - * @retval Counter Register high value. - */ -uint32_t SLPTIM_GetCounterHigh(void) -{ - __IO uint32_t counter = 0; - - /* Get the Counter Register value */ - counter = (uint32_t)SLPTMR->CNTH; - - return counter; -} - -/** - * @brief Gets the SLPTIM Counter low value. - * @retval Counter Register low value. - */ -uint32_t SLPTIM_GetCounterLow(void) -{ - __IO uint32_t counter = 0; - - /* Get the Counter Register value */ - counter = (uint32_t)SLPTMR->CNTH; - counter = (uint32_t)SLPTMR->CNTL; - - return counter; -} - -/** - * @} - */ - -/** @defgroup SLPTIM_Group2 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Forces the specified SLPTIM interrupts. - * @param SLPTIM_IT: specifies the SLPTIM interrupts sources to be generated. - * This parameter can be any combination of the following values: - * @arg SLPTIM_IT_WRAP: Sleep timer overflow - * @arg SLPTIM_IT_CMPA: Sleep timer compare A - * @arg SLPTIM_IT_CMPB: Sleep timer compare B - * @retval None - */ -void SLPTIM_ForceIT(uint32_t SLPTIM_IT) -{ - /* Check the parameters */ - assert_param(IS_SLPTIM_IT(SLPTIM_IT)); - - /* Force the Interrupt by setting the dedicated interrupt in the IFR register */ - SLPTMR->IFR |= SLPTIM_IT; -} - -/** - * @brief Enables or disables the specified SLPTIM interrupts. - * @param SLPTIM_IT: specifies the SLPTIM interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg SLPTIM_IT_WRAP: Sleep timer overflow - * @arg SLPTIM_IT_CMPA: Sleep timer compare A - * @arg SLPTIM_IT_CMPB: Sleep timer compare B - * @param NewState: new state of the SLPTIM interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SLPTIM_ITConfig(uint32_t SLPTIM_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SLPTIM_IT(SLPTIM_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Interrupt sources */ - SLPTMR->IER |= SLPTIM_IT; - } - else - { - /* Disable the Interrupt sources */ - SLPTMR->IER &= (uint32_t)~SLPTIM_IT; - } -} - -/** - * @brief Checks whether the specified SLPTIM flag is set or not. - * @param SLPTIM_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg SLPTIM_FLAG_WRAP: Sleep timer overflow - * @arg SLPTIM_FLAG_CMPA: Sleep timer compare A - * @arg SLPTIM_FLAG_CMPB: Sleep timer compare B - * @note - * @retval The new state of SLPTIM_FLAG (SET or RESET). - */ -FlagStatus SLPTIM_GetFlagStatus(uint32_t SLPTIM_FLAG) -{ - ITStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_SLPTIM_FLAG(SLPTIM_FLAG)); - - if ((SLPTMR->ISR & SLPTIM_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; - } - -/** - * @brief Clears the specified SLPTIM flag. - * @param SLPTIM_FLAG: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg SLPTIM_FLAG_WRAP: Sleep timer overflow - * @arg SLPTIM_FLAG_CMPA: Sleep timer compare A - * @arg SLPTIM_FLAG_CMPB: Sleep timer compare B - * @note - * @retval The new state of SLPTIM_FLAG (SET or RESET). - */ -void SLPTIM_ClearFlag(uint32_t SLPTIM_FLAG) -{ - /* Check the parameters */ - assert_param(IS_SLPTIM_FLAG(SLPTIM_FLAG)); - - /* Clear the flags */ - SLPTMR->ISR |= (uint32_t)SLPTIM_FLAG; -} - -/** - * @brief Checks whether the specified SLPTMR pending interrupt has occurred or not - * @param SLPTIM_IT: specifies the flag to check. - * This parameter can be one of the following values: - * This parameter can be one of the following values: - * @arg SLPTIM_FLAG_WRAP: Sleep timer overflow - * @arg SLPTIM_FLAG_CMPA: Sleep timer compare A - * @arg SLPTIM_FLAG_CMPB: Sleep timer compare B - * @retval The new state of SLPTIM_IT (SET or RESET). - */ -ITStatus SLPTIM_GetITStatus(uint32_t SLPTIM_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - /* Check the parameters */ - assert_param(IS_SLPTIM_IT(SLPTIM_IT)); - - enablestatus = (uint32_t)(SLPTMR->IER & SLPTIM_IT); - if (((SLPTMR->ISR & SLPTIM_IT) != (uint32_t)RESET) && enablestatus) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the specified SLPTIM flag. - * @param SLPTIM_IT: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg SLPTIM_FLAG_WRAP: Sleep timer overflow - * @arg SLPTIM_FLAG_CMPA: Sleep timer compare A - * @arg SLPTIM_FLAG_CMPB: Sleep timer compare B - * @note - * @retval The new state of SLPTIM_FLAG (SET or RESET). - */ -void SLPTIM_ClearITPendingBit(uint32_t SLPTIM_IT) -{ - /* Check the parameters */ - assert_param(IS_SLPTIM_IT(SLPTIM_IT)); - - /* Clear the pending interrupt */ - SLPTMR->ISR |= (uint32_t)SLPTIM_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_tim.c b/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_tim.c deleted file mode 100644 index 05faa14..0000000 --- a/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_tim.c +++ /dev/null @@ -1,2518 +0,0 @@ -/** - ****************************************************************************** - * @file stm32w108xx_tim.c - * @author MCD Application Team - * @version V1.0.1 - * @date 30-November-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the TIM peripheral: - * + TimeBase management - * + Output Compare management - * + Input Capture management - * + Interrupts management - * + Clocks management - * + Synchronization management - * + Specific interface management - * + Specific remapping management - * - * @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] This driver provides functions to configure and program the TIM - of all STM32W108xx devices These functions are split in 8 groups: - (#) TIM TimeBase management: this group includes all needed functions - to configure the TM Timebase unit: - (++) Set/Get Prescaler. - (++) Set/Get Autoreload. - (++) Counter modes configuration. - (++) Set Clock division. - (++) Select the One Pulse mode. - (++) Update Request Configuration. - (++) Update Disable Configuration. - (++) Auto-Preload Configuration. - (++) Enable/Disable the counter. - - (#) TIM Output Compare management: this group includes all needed - functions to configure the Capture/Compare unit used in Output - compare mode: - (++) Configure each channel, independently, in Output Compare mode. - (++) Select the output compare modes. - (++) Select the Polarities of each channel. - (++) Set/Get the Capture/Compare register values. - (++) Select the Output Compare Fast mode. - (++) Select the Output Compare Forced mode. - (++) Output Compare-Preload Configuration. - (++) Clear Output Compare Reference. - (++) Select the OCREF Clear signal. - (++) Enable/Disable the Capture/Compare Channels. - - (#) TIM Input Capture management: this group includes all needed - functions to configure the Capture/Compare unit used in - Input Capture mode: - (++) Configure each channel in input capture mode. - (++) Configure Channel1/2 in PWM Input mode. - (++) Set the Input Capture Prescaler. - (++) Get the Capture/Compare values. - - (#) Interrupts and flags management functions: this group includes - all needed - functions to manage interrupts: - (++) Enables or disables the specified TIM interrupts. - (++) Configures the TIMx event to be generate by software. - (++) Checks whether the TIM interrupt has occurred or not. - (++) Clears the TIMx's interrupt pending bits. - - (#) TIM clocks management: this group includes all needed functions - to configure the clock controller unit: - (++) Select internal/External clock. - (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx. - - (#) TIM synchronization management: this group includes all needed. - functions to configure the Synchronization unit: - (++) Select Input Trigger. - (++) Select Output Trigger. - (++) Select Master Slave Mode. - (++) ETR Configuration when used as external trigger. - - (#) TIM specific interface management, this group includes all - needed functions to use the specific TIM interface: - (++) Encoder Interface Configuration. - (++) Select Hall Sensor. - - (#) TIM specific remapping management includes the Remapping - configuration of specific timers - - @endverbatim - * - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2012 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32w108xx_tim.h" - -/** @addtogroup STM32W108xx_StdPeriph_Driver - * @{ - */ -/** @defgroup TIM - * @brief TIM driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* ---------------------- TIM registers bit mask ------------------------ */ -#define SMCR_ETR_MASK ((uint32_t)0x00FF) -#define CCMR_OFFSET ((uint32_t)0x0018) -#define CCER_CCE_SET ((uint32_t)0x0001) -#define TIM_ClockMask_Disable ((uint32_t)0x0000) -#define TIM_ClockMask_Enable ((uint32_t)0x0004) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ - -static void TI1_Config(TIM_TypeDef* TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TI2_Config(TIM_TypeDef* TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TI3_Config(TIM_TypeDef* TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TI4_Config(TIM_TypeDef* TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup TIM_Private_Functions - * @{ - */ - -/** @defgroup TIM_Group1 TimeBase management functions - * @brief TimeBase management functions - * - @verbatim - =============================================================================== - ##### TimeBase management functions ##### - =============================================================================== - *** TIM Driver: how to use it in Timing(Time base) Mode *** - =============================================================================== - [..] To use the Timer in Timing(Time base) mode, the following steps are - mandatory: - (#) Fill the TIM_TimeBaseInitStruct with the desired parameters. - (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure - the Time Base unit with the corresponding configuration. - (#) Enable the NVIC if you need to generate the update interrupt. - (#) Enable the corresponding interrupt using the function - TIM_ITConfig(TIMx, TIM_IT_Update). - (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. - [..] - (@) All other functions can be used seperatly to modify, if needed, - a specific feature of the Timer. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the TIMx peripheral registers to their default reset values. - * @param TIMx: where x can be 1 and 2 to select the TIM peripheral. - * @retval None - * - */ -void TIM_DeInit(TIM_TypeDef* TIMx) -{ - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - TIMx->CR1 = 0x00000000; - TIMx->CR2 = 0x00000000; - TIMx->SMCR = 0x00000000; - TIMx->EGR = 0x00000000; - TIMx->CCMR2 = 0x00000000; - TIMx->CCER = 0x00000000; - TIMx->CNT = 0x00000000; - TIMx->PSC = 0x00000000; - TIMx->ARR = 0x0000FFFF; - TIMx->CCMR1 = 0x00000000; - TIMx->CCR3 = 0x00000000; - TIMx->CCR4 = 0x00000000; - TIMx->CCR1 = 0x00000000; - TIMx->CCR2 = 0x00000000; - TIMx->OR = 0x00000000; - - if (TIMx == TIM1) - { - TIM1_IT->IER = 0x00000000; - TIM1_IT->ISR |= 0x0000005F; - TIM1_IT->IMR |= 0x00001E00; - } - else - { - if (TIMx == TIM2) - { - TIM2_IT->IER = 0x00000000; - TIM2_IT->ISR |= 0x0000005F; - TIM2_IT->IMR |= 0x00001E00; - } - } -} - -/** - * @brief Initializes the TIMx Time Base Unit peripheral according to - * the specified parameters in the TIM_TimeBaseInitStruct. - * @param TIMx: where x can be 1 and 2 to select the TIM - * peripheral. - * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef - * structure that contains the configuration information for - * the specified TIM peripheral. - * @retval None - */ -void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) -{ - uint32_t tmpcr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); - - tmpcr1 = TIMx->CR1; - - /* Select the Counter Mode */ - tmpcr1 &= (uint32_t)(~((uint32_t)(TIM_CR1_DIR | TIM_CR1_CMS))); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; - - - - TIMx->CR1 = tmpcr1; - - /* Set the Autoreload value */ - TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; - - /* Set the Prescaler value */ - TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; - - /* Generate an update event to reload the Prescaler and the Repetition counter - values immediately */ - TIMx->EGR = TIM_PSCReloadMode_Immediate; -} - -/** - * @brief Fills each TIM_TimeBaseInitStruct member with its default value. - * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef - * structure which will be initialized. - * @retval None - */ -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) -{ - /* Set the default configuration */ - TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; - TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; - TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; -} - -/** - * @brief Configures the TIMx Prescaler. - * @param TIMx: where x can be 1 and 2 to select the TIM peripheral. - * @param Prescaler: specifies the Prescaler Register value - * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode - * This parameter can be one of the following values: - * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. - * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly. - * @retval None - */ -void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint32_t Prescaler, uint32_t TIM_PSCReloadMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); - - /* Set the Prescaler value */ - TIMx->PSC = Prescaler; - /* Set or reset the UG Bit */ - TIMx->EGR = TIM_PSCReloadMode; -} - -/** - * @brief Specifies the TIMx Counter Mode to be used. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_CounterMode: specifies the Counter Mode to be used - * This parameter can be one of the following values: - * @arg TIM_CounterMode_Up: TIM Up Counting Mode - * @arg TIM_CounterMode_Down: TIM Down Counting Mode - * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 - * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 - * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 - * @retval None - */ -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint32_t TIM_CounterMode) -{ - uint32_t tmpcr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); - - tmpcr1 = TIMx->CR1; - /* Reset the CMS and DIR Bits */ - tmpcr1 &= (uint32_t)(~((uint32_t)(TIM_CR1_DIR | TIM_CR1_CMS))); - /* Set the Counter Mode */ - tmpcr1 |= TIM_CounterMode; - /* Write to TIMx CR1 register */ - TIMx->CR1 = tmpcr1; -} - -/** - * @brief Sets the TIMx Counter Register value - * @param TIMx: where x can be 1 and 2 to select the TIM - * peripheral. - * @param Counter: specifies the Counter register new value. - * @retval None - */ -void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Set the Counter Register value */ - TIMx->CNT = Counter; -} - -/** - * @brief Sets the TIMx Autoreload Register value - * @param TIMx: where x can be 1 and 2 to select the TIM peripheral. - * @param Autoreload: specifies the Autoreload register new value. - * @retval None - */ -void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Set the Autoreload Register value */ - TIMx->ARR = Autoreload; -} - -/** - * @brief Gets the TIMx Counter value. - * @param TIMx: where x can be 1 and 2 to select the TIM - * peripheral. - * @retval Counter Register value. - */ -uint32_t TIM_GetCounter(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Get the Counter Register value */ - return TIMx->CNT; -} - -/** - * @brief Gets the TIMx Prescaler value. - * @param TIMx: where x can be 1 and 2 to select the TIM - * peripheral. - * @retval Prescaler Register value. - */ -uint32_t TIM_GetPrescaler(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Get the Prescaler Register value */ - return TIMx->PSC; -} - -/** - * @brief Enables or Disables the TIMx Update event. - * @param TIMx: where x can be 1 and 2 to select the TIM - * peripheral. - * @param NewState: new state of the TIMx UDIS bit - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the Update Disable Bit */ - TIMx->CR1 |= TIM_CR1_UDIS; - } - else - { - /* Reset the Update Disable Bit */ - TIMx->CR1 &= (uint32_t)~((uint32_t)TIM_CR1_UDIS); - } -} - -/** - * @brief Configures the TIMx Update Request Interrupt source. - * @param TIMx: where x can be 1 and 2 to select the TIM - * peripheral. - * @param TIM_UpdateSource: specifies the Update source. - * This parameter can be one of the following values: - * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow - or the setting of UG bit, or an update generation - through the slave mode controller. - * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow. - * @retval None - */ -void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint32_t TIM_UpdateSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); - - if (TIM_UpdateSource != TIM_UpdateSource_Global) - { - /* Set the URS Bit */ - TIMx->CR1 |= TIM_CR1_URS; - } - else - { - /* Reset the URS Bit */ - TIMx->CR1 &= (uint32_t)~((uint32_t)TIM_CR1_URS); - } -} - -/** - * @brief Enables or disables TIMx peripheral Preload register on ARR. - * @param TIMx: where x can be 1 and 2 to select the TIM - * peripheral. - * @param NewState: new state of the TIMx peripheral Preload register - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the ARR Preload Bit */ - TIMx->CR1 |= TIM_CR1_ARPE; - } - else - { - /* Reset the ARR Preload Bit */ - TIMx->CR1 &= (uint32_t)~((uint32_t)TIM_CR1_ARPE); - } -} - -/** - * @brief Selects the TIMx's One Pulse Mode. - * @param TIMx: where x can be 1 and 2 to select the TIM - * peripheral. - * @param TIM_OPMode: specifies the OPM Mode to be used. - * This parameter can be one of the following values: - * @arg TIM_OPMode_Single - * @arg TIM_OPMode_Repetitive - * @retval None - */ -void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint32_t TIM_OPMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); - - /* Reset the OPM Bit */ - TIMx->CR1 &= (uint32_t)~((uint32_t)TIM_CR1_OPM); - /* Configure the OPM Mode */ - TIMx->CR1 |= TIM_OPMode; -} - - -/** - * @brief Enables or disables the specified TIM peripheral. - * @param TIMx: where x can be 1 and 2 and 17to select the TIMx - * peripheral. - * @param NewState: new state of the TIMx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TIM Counter */ - TIMx->CR1 |= TIM_CR1_CEN; - } - else - { - /* Disable the TIM Counter */ - TIMx->CR1 &= (uint32_t)(~((uint32_t)TIM_CR1_CEN)); - } -} - -/** - * @} - */ - -/** @defgroup TIM_Group2 Output Compare management functions - * @brief Output Compare management functions - * -@verbatim - =============================================================================== - ##### Output Compare management functions ##### - =============================================================================== - *** TIM Driver: how to use it in Output Compare Mode *** - =============================================================================== - [..] To use the Timer in Output Compare mode, the following steps are mandatory: - (#) Configure the TIM pins by configuring the corresponding GPIO pins - (#) Configure the Time base unit as described in the first part of this - driver, if needed, else the Timer will run with the default - configuration: - (++) Autoreload value = 0xFFFF. - (++) Prescaler value = 0x0000. - (++) Counter mode = Up counting. - (#) Fill the TIM_OCInitStruct with the desired parameters including: - (++) The TIM Output Compare mode: TIM_OCMode. - (++) TIM Output State: TIM_OutputState. - (++) TIM Pulse value: TIM_Pulse. - (++) TIM Output Compare Polarity : TIM_OCPolarity. - (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired - channel with the corresponding configuration. - (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. - [..] - (@) All other functions can be used separately to modify, if needed, - a specific feature of the Timer. - (@) In case of PWM mode, this function is mandatory: - TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE). - (@) If the corresponding interrupt are needed, the user should: - (#@) Enable the NVIC to use the TIM interrupts. - (#@) Enable the corresponding interrupt using the function - TIM_ITConfig(TIMx, TIM_IT_CCx). - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the TIMx Channel1 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 1 and 2 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM - * peripheral. - * @retval None - */ -void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= (uint32_t)(~(uint32_t)TIM_CCER_CC1E); - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= (uint32_t)(~((uint32_t)TIM_CCMR1_OC1M)); - tmpccmrx &= (uint32_t)(~((uint32_t)TIM_CCMR1_CC1S)); - - /* Select the Output Compare Mode */ - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= (uint32_t)(~((uint32_t)TIM_CCER_CC1P)); - /* Set the Output Compare Polarity */ - tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; - - /* Set the Output State */ - tmpccer |= TIM_OCInitStruct->TIM_OutputState; - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel2 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM - * peripheral. - * @retval None - */ -void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint32_t)(~((uint32_t)TIM_CCER_CC2E)); - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint32_t)(~((uint32_t)TIM_CCMR1_OC2M)); - tmpccmrx &= (uint32_t)(~((uint32_t)TIM_CCMR1_CC2S)); - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint32_t)(~((uint32_t)TIM_CCER_CC2P)); - /* Set the Output Compare Polarity */ - tmpccer |= (uint32_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); - - /* Set the Output State */ - tmpccer |= (uint32_t)(TIM_OCInitStruct->TIM_OutputState << 4); - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel3 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM - * peripheral. - * @retval None - */ -void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint32_t)(~((uint32_t)TIM_CCER_CC3E)); - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint32_t)(~((uint32_t)TIM_CCMR2_OC3M)); - tmpccmrx &= (uint32_t)(~((uint32_t)TIM_CCMR2_CC3S)); - /* Select the Output Compare Mode */ - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= (uint32_t)(~((uint32_t)TIM_CCER_CC3P)); - /* Set the Output Compare Polarity */ - tmpccer |= (uint32_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); - - /* Set the Output State */ - tmpccer |= (uint32_t)(TIM_OCInitStruct->TIM_OutputState << 8); - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel4 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM - * peripheral. - * @retval None - */ -void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 2: Reset the CC4E Bit */ - TIMx->CCER &= (uint32_t)(~((uint32_t)TIM_CCER_CC4E)); - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint32_t)(~((uint32_t)TIM_CCMR2_OC4M)); - tmpccmrx &= (uint32_t)(~((uint32_t)TIM_CCMR2_CC4S)); - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint32_t)(~((uint32_t)TIM_CCER_CC4P)); - /* Set the Output Compare Polarity */ - tmpccer |= (uint32_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); - - /* Set the Output State */ - tmpccer |= (uint32_t)(TIM_OCInitStruct->TIM_OutputState << 12); - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Fills each TIM_OCInitStruct member with its default value. - * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will - * be initialized. - * @retval None - */ -void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - /* Set the default configuration */ - TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; - TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; - TIM_OCInitStruct->TIM_Pulse = 0x0000000; - TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; -} - -/** - * @brief Selects the TIM Output Compare Mode. - * @note This function disables the selected channel before changing the Output - * Compare Mode. - * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @param TIM_OCMode: specifies the TIM Output Compare Mode. - * This parameter can be one of the following values: - * @arg TIM_OCMode_Timing - * @arg TIM_OCMode_Active - * @arg TIM_OCMode_Toggle - * @arg TIM_OCMode_PWM1 - * @arg TIM_OCMode_PWM2 - * @arg TIM_ForcedAction_Active - * @arg TIM_ForcedAction_InActive - * @retval None - */ -void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint32_t TIM_Channel, uint32_t TIM_OCMode) -{ - uint32_t tmp = 0; - uint32_t tmp1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_OCM(TIM_OCMode)); - - tmp = (uint32_t) TIMx; - tmp += CCMR_OFFSET; - - tmp1 = CCER_CCE_SET << (uint32_t)TIM_Channel; - - /* Disable the Channel: Reset the CCxE Bit */ - TIMx->CCER &= (uint32_t) ~tmp1; - - if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) - { - tmp += (TIM_Channel>>1); - - /* Reset the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M); - - /* Configure the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp |= TIM_OCMode; - } - else - { - tmp += (uint32_t)(TIM_Channel - (uint32_t)4)>> (uint32_t)1; - - /* Reset the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M); - - /* Configure the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp |= (uint32_t)(TIM_OCMode << 8); - } -} - -/** - * @brief Sets the TIMx Capture Compare1 Register value - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param Compare1: specifies the Capture Compare1 register new value. - * @retval None - */ -void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Set the Capture Compare1 Register value */ - TIMx->CCR1 = Compare1; -} - -/** - * @brief Sets the TIMx Capture Compare2 Register value - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param Compare2: specifies the Capture Compare2 register new value. - * @retval None - */ -void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Set the Capture Compare2 Register value */ - TIMx->CCR2 = Compare2; -} - -/** - * @brief Sets the TIMx Capture Compare3 Register value - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param Compare3: specifies the Capture Compare3 register new value. - * @retval None - */ -void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Set the Capture Compare3 Register value */ - TIMx->CCR3 = Compare3; -} - -/** - * @brief Sets the TIMx Capture Compare4 Register value - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param Compare4: specifies the Capture Compare4 register new value. - * @retval None - */ -void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Set the Capture Compare4 Register value */ - TIMx->CCR4 = Compare4; -} - -/** - * @brief Forces the TIMx output 1 waveform to active or inactive level. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC1REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. - * @retval None - */ -void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint32_t TIM_ForcedAction) -{ - uint32_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC1M Bits */ - tmpccmr1 &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M); - /* Configure The Forced output Mode */ - tmpccmr1 |= TIM_ForcedAction; - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Forces the TIMx output 2 waveform to active or inactive level. - * @param TIMx: where x can be 1 or 2 to select the TIM - * peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC2REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. - * @retval None - */ -void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint32_t TIM_ForcedAction) -{ - uint32_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2M Bits */ - tmpccmr1 &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M); - /* Configure The Forced output Mode */ - tmpccmr1 |= (uint32_t)(TIM_ForcedAction << 8); - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Forces the TIMx output 3 waveform to active or inactive level. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC3REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. - * @retval None - */ -void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint32_t TIM_ForcedAction) -{ - uint32_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC1M Bits */ - tmpccmr2 &= (uint32_t)~((uint32_t)TIM_CCMR2_OC3M); - /* Configure The Forced output Mode */ - tmpccmr2 |= TIM_ForcedAction; - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Forces the TIMx output 4 waveform to active or inactive level. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC4REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. - * @retval None - */ -void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint32_t TIM_ForcedAction) -{ - uint32_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC2M Bits */ - tmpccmr2 &= (uint32_t)~((uint32_t)TIM_CCMR2_OC4M); - /* Configure The Forced output Mode */ - tmpccmr2 |= (uint32_t)(TIM_ForcedAction << 8); - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR1. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPreload) -{ - uint32_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC1PE Bit */ - tmpccmr1 &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1PE); - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr1 |= TIM_OCPreload; - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR2. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPreload) -{ - uint32_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2PE Bit */ - tmpccmr1 &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2PE); - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr1 |= (uint32_t)(TIM_OCPreload << 8); - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR3. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPreload) -{ - uint32_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC3PE Bit */ - tmpccmr2 &= (uint32_t)~((uint32_t)TIM_CCMR2_OC3PE); - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr2 |= TIM_OCPreload; - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR4. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPreload) -{ - uint32_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC4PE Bit */ - tmpccmr2 &= (uint32_t)~((uint32_t)TIM_CCMR2_OC4PE); - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr2 |= (uint32_t)(TIM_OCPreload << 8); - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx Output Compare 1 Fast feature. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCFast) -{ - uint32_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC1FE Bit */ - tmpccmr1 &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1FE); - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr1 |= TIM_OCFast; - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Configures the TIMx Output Compare 2 Fast feature. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCFast) -{ - uint32_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2FE Bit */ - tmpccmr1 &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2FE); - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr1 |= (uint32_t)(TIM_OCFast << 8); - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Configures the TIMx Output Compare 3 Fast feature. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCFast) -{ - uint32_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC3FE Bit */ - tmpccmr2 &= (uint32_t)~((uint32_t)TIM_CCMR2_OC3FE); - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr2 |= TIM_OCFast; - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx Output Compare 4 Fast feature. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCFast) -{ - uint32_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC4FE Bit */ - tmpccmr2 &= (uint32_t)~((uint32_t)TIM_CCMR2_OC4FE); - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr2 |= (uint32_t)(TIM_OCFast << 8); - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx channel 1 polarity. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC1 Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPolarity) -{ - uint32_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC1P Bit */ - tmpccer &= (uint32_t)~((uint32_t)TIM_CCER_CC1P); - tmpccer |= TIM_OCPolarity; - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 2 polarity. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC2 Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPolarity) -{ - uint32_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC2P Bit */ - tmpccer &= (uint32_t)~((uint32_t)TIM_CCER_CC2P); - tmpccer |= (uint32_t)(TIM_OCPolarity << 4); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 3 polarity. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC3 Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPolarity) -{ - uint32_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC3P Bit */ - tmpccer &= (uint32_t)~((uint32_t)TIM_CCER_CC3P); - tmpccer |= (uint32_t)(TIM_OCPolarity << 8); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 4 polarity. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC4 Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPolarity) -{ - uint32_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC4P Bit */ - tmpccer &= (uint32_t)~((uint32_t)TIM_CCER_CC4P); - tmpccer |= (uint32_t)(TIM_OCPolarity << 12); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel x. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. - * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. - * @retval None - */ -void TIM_CCxCmd(TIM_TypeDef* TIMx, uint32_t TIM_Channel, uint32_t TIM_CCx) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_CCX(TIM_CCx)); - - tmp = CCER_CCE_SET << TIM_Channel; - - /* Reset the CCxE Bit */ - TIMx->CCER &= (uint32_t)~ tmp; - - /* Set or reset the CCxE Bit */ - TIMx->CCER |= (uint32_t)(TIM_CCx << TIM_Channel); -} - -/** - * @} - */ - -/** @defgroup TIM_Group3 Input Capture management functions - * @brief Input Capture management functions - * -@verbatim - =============================================================================== - ##### Input Capture management functions ##### - =============================================================================== - - *** TIM Driver: how to use it in Input Capture Mode *** - =============================================================================== - [..] To use the Timer in Input Capture mode, the following steps are mandatory: - (#) Configure the TIM pins by configuring the corresponding GPIO pins. - (#) Configure the Time base unit as described in the first part of this - driver, if needed, else the Timer will run with the default configuration: - (++) Autoreload value = 0xFFFF. - (++) Prescaler value = 0x0000. - (++) Counter mode = Up counting. - (#) Fill the TIM_ICInitStruct with the desired parameters including: - (++) TIM Channel: TIM_Channel. - (++) TIM Input Capture polarity: TIM_ICPolarity. - (++) TIM Input Capture selection: TIM_ICSelection. - (++) TIM Input Capture Prescaler: TIM_ICPrescaler. - (++) TIM Input CApture filter value: TIM_ICFilter. - (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired - channel with the corresponding configuration and to measure only - frequency or duty cycle of the input signal,or, Call - TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired - channels with the corresponding configuration and to measure the - frequency and the duty cycle of the input signal. - (#) Enable the NVIC to read the measured frequency. - (#) Enable the corresponding interrupt to read - the Captured value, using the function TIM_ITConfig(TIMx, TIM_IT_CCx). - (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. - (#) Use TIM_GetCapturex(TIMx); to read the captured value. - [..] - (@) All other functions can be used separately to modify, if needed, - a specific feature of the Timer. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure - * that contains the configuration information for the specified TIM - * peripheral. - * @retval None - */ -void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel)); - assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); - assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); - assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); - - if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - /* TI1 Configuration */ - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) - { - /* TI2 Configuration */ - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) - { - /* TI3 Configuration */ - TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - /* TI4 Configuration */ - TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/** - * @brief Fills each TIM_ICInitStruct member with its default value. - * @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will - * be initialized. - * @retval None - */ -void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - /* Set the default configuration */ - TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; - TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; - TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; - TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; - TIM_ICInitStruct->TIM_ICFilter = 0x00; -} - -/** - * @brief Configures the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct to measure an external PWM signal. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure - * that contains the configuration information for the specified TIM - * peripheral. - * @retval None - */ -void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - uint32_t icoppositepolarity = TIM_ICPolarity_Rising; - uint32_t icoppositeselection = TIM_ICSelection_DirectTI; - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - /* Select the Opposite Input Polarity */ - if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) - { - icoppositepolarity = TIM_ICPolarity_Falling; - } - else - { - icoppositepolarity = TIM_ICPolarity_Rising; - } - /* Select the Opposite Input */ - if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) - { - icoppositeselection = TIM_ICSelection_IndirectTI; - } - else - { - icoppositeselection = TIM_ICSelection_DirectTI; - } - if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - /* TI1 Configuration */ - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - /* TI2 Configuration */ - TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - /* TI2 Configuration */ - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - /* TI1 Configuration */ - TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/** - * @brief Gets the TIMx Input Capture 1 value. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @retval Capture Compare 1 Register value. - */ -uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Get the Capture 1 Register value */ - return TIMx->CCR1; -} - -/** - * @brief Gets the TIMx Input Capture 2 value. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @retval Capture Compare 2 Register value. - */ -uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Get the Capture 2 Register value */ - return TIMx->CCR2; -} - -/** - * @brief Gets the TIMx Input Capture 3 value. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @retval Capture Compare 3 Register value. - */ -uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Get the Capture 3 Register value */ - return TIMx->CCR3; -} - -/** - * @brief Gets the TIMx Input Capture 4 value. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @retval Capture Compare 4 Register value. - */ -uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Get the Capture 4 Register value */ - return TIMx->CCR4; -} - -/** - * @brief Sets the TIMx Input Capture 1 prescaler. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint32_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC1PSC Bits */ - TIMx->CCMR1 &= (uint32_t)~((uint32_t)TIM_CCMR1_IC1PSC); - /* Set the IC1PSC value */ - TIMx->CCMR1 |= TIM_ICPSC; -} - -/** - * @brief Sets the TIMx Input Capture 2 prescaler. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint32_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC2PSC Bits */ - TIMx->CCMR1 &= (uint32_t)~((uint32_t)TIM_CCMR1_IC2PSC); - /* Set the IC2PSC value */ - TIMx->CCMR1 |= (uint32_t)(TIM_ICPSC << 8); -} - -/** - * @brief Sets the TIMx Input Capture 3 prescaler. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint32_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC3PSC Bits */ - TIMx->CCMR2 &= (uint32_t)~((uint32_t)TIM_CCMR2_IC3PSC); - /* Set the IC3PSC value */ - TIMx->CCMR2 |= TIM_ICPSC; -} - -/** - * @brief Sets the TIMx Input Capture 4 prescaler. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint32_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC4PSC Bits */ - TIMx->CCMR2 &= (uint32_t)~((uint32_t)TIM_CCMR2_IC4PSC); - /* Set the IC4PSC value */ - TIMx->CCMR2 |= (uint32_t)(TIM_ICPSC << 8); -} - -/** - * @} - */ - -/** @defgroup TIM_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified TIM interrupts. - * @param TIMx_IT: where x can be 1 or 2 to select the TIMx peripheral. - * @param TIM_ITRPT: specifies the TIM interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg TIM_IT_Update: TIM update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @param NewState: new state of the TIM interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_ITConfig(TIM_IT_TypeDef* TIMx_IT, uint32_t TIM_ITRPT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_IT_ALL_PERIPH(TIMx_IT)); - assert_param(IS_TIM_ITRPT(TIM_ITRPT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Interrupt sources */ - TIMx_IT->IER |= TIM_ITRPT; - } - else - { - /* Disable the Interrupt sources */ - TIMx_IT->IER &= (uint32_t)~TIM_ITRPT; - } -} - -/** - * @brief Configures the TIMx event to be generate by software. - * @param TIMx: where x can be 1 or 2 to select the - * TIM peripheral. - * @param TIM_EventSource: specifies the event source. - * This parameter can be one or more of the following values: - * @arg TIM_EventSource_Update: Timer update Event source - * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source - * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source - * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source - * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source - * @arg TIM_EventSource_Trigger: Timer Trigger Event source - * @retval None - */ -void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint32_t TIM_EventSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); - /* Set the event sources */ - TIMx->EGR = TIM_EventSource; -} - -/** - * @brief Checks whether the TIM interrupt has occurred or not. - * @param TIMx_IT: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_ITRPT: specifies the TIM interrupt source to check. - * This parameter can be one of the following values: - * @arg TIM_IT_Update: TIM update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @retval The new state of the TIM_IT(SET or RESET). - */ -ITStatus TIM_GetITStatus(TIM_IT_TypeDef* TIMx_IT, uint32_t TIM_ITRPT) -{ - ITStatus bitstatus = RESET; - uint32_t itstatus = 0x0, itenable = 0x0; - - /* Check the parameters */ - assert_param(IS_TIM_IT_ALL_PERIPH(TIMx_IT)); - assert_param(IS_TIM_GET_IT(TIM_ITRPT)); - - - itstatus = TIMx_IT->ISR & TIM_ITRPT; - itenable = TIMx_IT->IER & TIM_ITRPT; - - if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the TIMx's interrupt pending bits. - * @param TIMx_IT: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_ITRPT: specifies the pending bit to clear. - * This parameter can be any combination of the following values: - * @arg TIM_IT_Update: TIM1 update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @retval None - */ -void TIM_ClearITPendingBit(TIM_IT_TypeDef* TIMx_IT, uint32_t TIM_ITRPT) -{ - /* Check the parameters */ - assert_param(IS_TIM_IT_ALL_PERIPH(TIMx_IT)); - assert_param(IS_TIM_ITRPT(TIM_ITRPT)); - - /* Clear the IT pending Bit */ - - TIMx_IT->ISR = TIM_ITRPT; -} - -/** - * @} - */ - -/** @defgroup TIM_Group5 Clocks management functions - * @brief Clocks management functions - * -@verbatim - =============================================================================== - ##### Clocks management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the TIMx internal Clock - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @retval None - */ -void TIM_InternalClockConfig(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - /* Disable slave mode to clock the prescaler directly with the internal clock */ - TIMx->SMCR &= (uint32_t)(~((uint32_t)TIM_SMCR_SMS)); -} - -/** - * @brief Configures the TIMx Internal Trigger as External Clock - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_InputTriggerSource: Trigger source. - * This parameter can only be: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @retval None - */ -void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint32_t TIM_InputTriggerSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); - /* Select the Internal Trigger */ - TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); - /* Select the External clock mode1 */ - TIMx->SMCR |= TIM_SlaveMode_External1; -} - -/** - * @brief Configures the TIMx Trigger as External Clock - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_TIxExternalCLKSource: Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector - * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 - * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 - * @param TIM_ICPolarity: specifies the TIx Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param ICFilter : specifies the filter value. - * This parameter must be a value between 0x0 and 0xF. - * @retval None - */ -void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint32_t TIM_TIxExternalCLKSource, - uint32_t TIM_ICPolarity, uint32_t ICFilter) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); - assert_param(IS_TIM_IC_FILTER(ICFilter)); - - /* Configure the Timer Input Clock Source */ - if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) - { - TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - else - { - TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - /* Select the Trigger source */ - TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); - /* Select the External clock mode1 */ - TIMx->SMCR |= TIM_SlaveMode_External1; -} - -/** - * @brief Configures the External clock Mode1 - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, - uint32_t ExtTRGFilter) -{ - uint32_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - - /* Configure the ETR Clock source */ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Reset the SMS Bits */ - tmpsmcr &= (uint32_t)(~((uint32_t)TIM_SMCR_SMS)); - /* Select the External clock mode1 */ - tmpsmcr |= TIM_SlaveMode_External1; - /* Select the Trigger selection : ETRF */ - tmpsmcr &= (uint32_t)(~((uint32_t)TIM_SMCR_TS)); - tmpsmcr |= TIM_TS_ETRF; - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Configures the External clock Mode2 - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, - uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - - /* Configure the ETR Clock source */ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - /* Enable the External clock mode2 */ - TIMx->SMCR |= TIM_SMCR_ECE; -} - -/** - * @} - */ - -/** @defgroup TIM_Group6 Synchronization management functions - * @brief Synchronization management functions - * -@verbatim - =============================================================================== - ##### Synchronization management functions ##### - =============================================================================== - *** TIM Driver: how to use it in synchronization Mode *** - =============================================================================== - [..] Case of two/several Timers - (#) Configure the Master Timers using the following functions: - (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, - uint32_t TIM_TRGOSource). - (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, - uint32_t TIM_MasterSlaveMode); - (#) Configure the Slave Timers using the following functions: - (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, - uint32_t TIM_InputTriggerSource); - (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint32_t TIM_SlaveMode); - [..] Case of Timers and external trigger(ETR pin) - (#) Configure the Etrenal trigger using this function: - (++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, - uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); - (#) Configure the Slave Timers using the following functions: - (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, - uint32_t TIM_InputTriggerSource); - (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint32_t TIM_SlaveMode); - -@endverbatim - * @{ - */ -/** - * @brief Selects the Input Trigger source - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_InputTriggerSource: The Input Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_TI1F_ED: TI1 Edge Detector - * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 - * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 - * @arg TIM_TS_ETRF: External Trigger input - * @retval None - */ -void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint32_t TIM_InputTriggerSource) -{ - uint32_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Reset the TS Bits */ - tmpsmcr &= (uint32_t)(~((uint32_t)TIM_SMCR_TS)); - /* Set the Input Trigger source */ - tmpsmcr |= TIM_InputTriggerSource; - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Selects the TIMx Trigger Output Mode. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_TRGOSource: specifies the Trigger Output source. - * This paramter can be one of the following values: - * - * For all TIMx - * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO). - * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag - * is to be set, as soon as a capture or compare match occurs (TRGO). - * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO). - * - * @retval None - */ -void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint32_t TIM_TRGOSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); - - /* Reset the MMS Bits */ - TIMx->CR2 &= (uint32_t)~((uint32_t)TIM_CR2_MMS); - /* Select the TRGO source */ - TIMx->CR2 |= TIM_TRGOSource; -} - -/** - * @brief Selects the TIMx Slave Mode. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_SlaveMode: specifies the Timer Slave Mode. - * This paramter can be one of the following values: - * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes - * the counter and triggers an update of the registers. - * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high. - * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI. - * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter. - * @retval None - */ -void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint32_t TIM_SlaveMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); - - /* Reset the SMS Bits */ - TIMx->SMCR &= (uint32_t)~((uint32_t)TIM_SMCR_SMS); - /* Select the Slave Mode */ - TIMx->SMCR |= TIM_SlaveMode; -} - -/** - * @brief Sets or Resets the TIMx Master/Slave Mode. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. - * This paramter can be one of the following values: - * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer - * and its slaves (through TRGO). - * @arg TIM_MasterSlaveMode_Disable: No action - * @retval None - */ -void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint32_t TIM_MasterSlaveMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); - - /* Reset the MSM Bit */ - TIMx->SMCR &= (uint32_t)~((uint32_t)TIM_SMCR_MSM); - - /* Set or Reset the MSM Bit */ - TIMx->SMCR |= TIM_MasterSlaveMode; -} - -/** - * @brief Configures the TIMx External Trigger (ETR). - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, - uint32_t ExtTRGFilter) -{ - uint32_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - - tmpsmcr = TIMx->SMCR; - /* Reset the ETR Bits */ - tmpsmcr &= SMCR_ETR_MASK; - /* Set the Prescaler, the Filter value and the Polarity */ - tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (uint32_t)(TIM_ExtTRGPolarity | (uint32_t)(ExtTRGFilter << (uint32_t)8))); - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @} - */ - -/** @defgroup TIM_Group7 Specific interface management functions - * @brief Specific interface management functions - * -@verbatim - =============================================================================== - ##### Specific interface management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the TIMx Encoder Interface. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. - * This parameter can be one of the following values: - * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. - * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. - * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending - * on the level of the other input. - * @param TIM_IC1Polarity: specifies the IC1 Polarity - * This parmeter can be one of the following values: - * @arg TIM_ICPolarity_Falling: IC Falling edge. - * @arg TIM_ICPolarity_Rising: IC Rising edge. - * @param TIM_IC2Polarity: specifies the IC2 Polarity - * This parmeter can be one of the following values: - * @arg TIM_ICPolarity_Falling: IC Falling edge. - * @arg TIM_ICPolarity_Rising: IC Rising edge. - * @retval None - */ -void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint32_t TIM_EncoderMode, - uint32_t TIM_IC1Polarity, uint32_t TIM_IC2Polarity) -{ - uint32_t tmpsmcr = 0; - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); - assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); - assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Set the encoder Mode */ - tmpsmcr &= (uint32_t)(~((uint32_t)TIM_SMCR_SMS)); - tmpsmcr |= TIM_EncoderMode; - /* Select the Capture Compare 1 and the Capture Compare 2 as input */ - tmpccmr1 &= (uint32_t)(((uint32_t)~((uint32_t)TIM_CCMR1_CC1S)) & (uint32_t)(~((uint32_t)TIM_CCMR1_CC2S))); - tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; - /* Set the TI1 and the TI2 Polarities */ - tmpccer &= (uint32_t)(((uint32_t)~((uint32_t)TIM_CCER_CC1P)) & ((uint32_t)~((uint32_t)TIM_CCER_CC2P))); - tmpccer |= (uint32_t)(TIM_IC1Polarity | (uint32_t)(TIM_IC2Polarity << (uint32_t)4)); - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Enables or disables the TIMx's Hall sensor interface. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @param NewState: new state of the TIMx Hall sensor interface. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the TI1S Bit */ - TIMx->CR2 |= TIM_CR2_TI1S; - } - else - { - /* Reset the TI1S Bit */ - TIMx->CR2 &= (uint32_t)~((uint32_t)TIM_CR2_TI1S); - } -} - -/** - * @} - */ - -/** @defgroup TIM_Group8 Specific remapping management function - * @brief Specific remapping management function - * -@verbatim - =============================================================================== - ##### Specific remapping management function ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Selects the TIMx Extenal trigger used in external clock mode 2. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param NewState: new state of the TIMx CLKMSKEN bit - * This parameter can be: ENABLE or DISABLE. - * @retval : None - */ -void TIM_ClockMaskConfig(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the clock mask */ - TIMx->OR |= TIM_ClockMask_Enable; - } - else - { - /* Disable the clock mask */ - TIMx->OR &= TIM_ClockMask_Disable; - } -} - -/** - * @brief Selects the TIMx Extenal trigger used in external clock mode 2. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_EXTRIGCLK: specifies the TIM input reampping source. - * This parameter can be one of the following values: - * @arg TIM_EXTRIGPCLK: PCLK. - * @arg TIM_EXTRIG1KHCLK: calibrated 1 kHz clock. - * @arg TIM_EXTRIG32KHCLK: 32 kHz reference clock (if available). - * @arg TIM_EXTRIGTIMxCLK: TIMxCLK pin. - * @retval : None - */ -void TIM_SelectExternalTriggerClock(TIM_TypeDef* TIMx, uint32_t TIM_EXTRIGCLK) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_EXTRIGCLK(TIM_EXTRIGCLK)); - - /* Set the Timer remapping configuration */ - TIMx->OR |= TIM_EXTRIGCLK; -} - -/** - * @brief Configures the TIM2 Remapping input Capabilities. - * @param TIMx: where x can be 2 to select the TIM peripheral. - * @param TIM_Remap: specifies the TIM input reampping source. - * This parameter can be one of the following values: - * @arg TIM_REMAPC1: TIM2 Channel 1 is connected to GPIOA (PA0) or to GPIOB (PB1). - * @arg TIM_REMAPC2: TIM2 Channel 2 is connected to GPIOA (PA3) or to GPIOB (PB2). - * @arg TIM_REMAPC3: TIM2 Channel 3 is connected to GPIOA (PA1) or to GPIOB (PB3). - * @arg TIM_REMAPC4: TIM2 Channel 4 is connected to GPIOA (PA2) or to GPIOB (PB4). - * @param NewState: new state of the TIMx TIM2_OR_REMAPCy bit (y can be 1..4). - * This parameter can be: ENABLE or DISABLE. - * @retval : None - */ -void TIM_RemapCmd(TIM_TypeDef* TIMx, uint32_t TIM_Remap, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_REMAP(TIM_Remap)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the Timer remapping configuration */ - TIMx->OR |= TIM_Remap; - } - else - { - TIMx->OR &= (uint32_t)~TIM_Remap; - } -} - -/** - * @} - */ - -/** - * @brief Configure the TI1 as Input. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising: - * @arg TIM_ICPolarity_Falling: - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. - * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. - * @arg TIM_ICSelection_TRGI: TIM Input 1 is selected to be connected to TRGI. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI1_Config(TIM_TypeDef* TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - - uint32_t tmpccmr1 = 0, tmpccer = 0; - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= (uint32_t)~((uint32_t)TIM_CCER_CC1E); - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - /* Select the Input and set the filter */ - tmpccmr1 &= (uint32_t)(((uint32_t)~((uint32_t)TIM_CCMR1_CC1S)) & ((uint32_t)~((uint32_t)TIM_CCMR1_IC1F))); - tmpccmr1 |= (uint32_t)(TIM_ICSelection | (uint32_t)(TIM_ICFilter << (uint32_t)4)); - - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= (uint32_t)~((uint32_t)(TIM_CCER_CC1P)); - tmpccer |= (uint32_t)(TIM_ICPolarity | (uint32_t)TIM_CCER_CC1E); - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI2 as Input. - * @param TIMx: where x can be 1 or 2 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. - * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. - * @arg TIM_ICSelection_TRGI: TIM Input 2 is selected to be connected to TRGI. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI2_Config(TIM_TypeDef* TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint32_t)~((uint32_t)TIM_CCER_CC2E); - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - tmp = (uint32_t)(TIM_ICPolarity << 4); - /* Select the Input and set the filter */ - tmpccmr1 &= (uint32_t)(((uint32_t)~((uint32_t)TIM_CCMR1_CC2S)) & ((uint32_t)~((uint32_t)TIM_CCMR1_IC2F))); - tmpccmr1 |= (uint32_t)(TIM_ICFilter << 12); - tmpccmr1 |= (uint32_t)(TIM_ICSelection << 8); - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= (uint32_t)~((uint32_t)(TIM_CCER_CC2P)); - tmpccer |= (uint32_t)(tmp | (uint32_t)TIM_CCER_CC2E); - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI3 as Input. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. - * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. - * @arg TIM_ICSelection_TRGI: TIM Input 3 is selected to be connected to TRGI. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI3_Config(TIM_TypeDef* TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - /* Disable the Channel 3: Reset the CC3E Bit */ - TIMx->CCER &= (uint32_t)~((uint32_t)TIM_CCER_CC3E); - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - tmp = (uint32_t)(TIM_ICPolarity << 8); - /* Select the Input and set the filter */ - tmpccmr2 &= (uint32_t)(((uint32_t)~((uint32_t)TIM_CCMR2_CC3S)) & ((uint32_t)~((uint32_t)TIM_CCMR2_IC3F))); - tmpccmr2 |= (uint32_t)(TIM_ICSelection | (uint32_t)(TIM_ICFilter << (uint32_t)4)); - /* Select the Polarity and set the CC3E Bit */ - tmpccer &= (uint32_t)~((uint32_t)(TIM_CCER_CC3P)); - tmpccer |= (uint32_t)(tmp | (uint32_t)TIM_CCER_CC3E); - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI4 as Input. - * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. - * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. - * @arg TIM_ICSelection_TRGI: TIM Input 4 is selected to be connected to TRGI. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI4_Config(TIM_TypeDef* TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= (uint32_t)~((uint32_t)TIM_CCER_CC4E); - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - tmp = (uint32_t)(TIM_ICPolarity << 12); - /* Select the Input and set the filter */ - tmpccmr2 &= (uint32_t)((uint32_t)(~(uint32_t)TIM_CCMR2_CC4S) & ((uint32_t)~((uint32_t)TIM_CCMR2_IC4F))); - tmpccmr2 |= (uint32_t)(TIM_ICSelection << 8); - tmpccmr2 |= (uint32_t)(TIM_ICFilter << 12); - /* Select the Polarity and set the CC4E Bit */ - tmpccer &= (uint32_t)~((uint32_t)(TIM_CCER_CC3P)); - tmpccer |= (uint32_t)(tmp | (uint32_t)TIM_CCER_CC4E); - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_wdg.c b/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_wdg.c deleted file mode 100644 index 037f5a6..0000000 --- a/libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_wdg.c +++ /dev/null @@ -1,191 +0,0 @@ -/** - ****************************************************************************** - * @file stm32w108xx_wdg.c - * @author MCD Application Team - * @version V1.0.1 - * @date 30-November-2012 - * @brief This file provides firmware functions to use the watchdog (WDG) peripheral - * - * @verbatim - * -================================================================================ - ##### WDG features ##### -================================================================================ - [..] The watchdog timer uses the calibrated 1 kHz clock (CLK1K) as its reference - and provides a nominal 2.048 s timeout. A low water mark interrupt occurs - at 1.760 s and triggers an NMI to the Cortex-M3 NVIC as an early warning. - When enabled, periodically reset the watchdog timer before it expires. - - [..] By default, the WDG is disabled at power up of the always-on power domain. - - [..] The watchdog timer can be paused when the debugger halts the core. - - ##### How to use this driver ##### -================================================================================ - [..] This driver allows to use WDG peripheral. - [..] Start the WDG using WDG_Cmd() function. - [..] Restart the WDG timer using WDG_ReloadCounter() function. - [..] Specifies the staus of WDG timer during debug mode using WDG_DebugConfig() function. - - - @endverbatim - * - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2012 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32w108xx_wdg.h" - -/** @addtogroup STM32W108xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup WDG - * @brief WDG driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* ---------------------- WDG registers bit mask -----------------------------*/ -#define KICKSR_KEY_RELOAD ((uint32_t)0xAAAAAAAA) -#define KR_KEY_ENABLE ((uint32_t)0x0000EABE) -#define KR_KEY_DISABLE ((uint32_t)0x0000DEAD) -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup WDG_Private_Functions - * @{ - */ - -/** @defgroup WDG_Group1 WDG activation function - * @brief WDG activation function - * -@verbatim - ============================================================================== - ##### WDG activation function ##### - ============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the WDG peripheral registers to their default reset values. - * @param None - * @retval None - */ -void WDG_DeInit(void) -{ - WDG->CR = 0x00000002; - WDG->KR = 0x00000000; - WDG->KICKSR = 0x00000000; -} - -/** - * @brief Reloads WDG counter with value defined in the restart register - * @param None - * @retval None - */ -void WDG_ReloadCounter(void) -{ - WDG->KICKSR = KICKSR_KEY_RELOAD; -} - -/** - * @brief Enables/Disables WDG. - * @param NewState: new state of the WDG timer. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void WDG_Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - WDG->KR = 0x00000000; - WDG->KR |= KR_KEY_ENABLE; - WDG->CR = WDG_CR_WDGEN; - } - else - { - WDG->KR = 0x00000000; - WDG->KR |= KR_KEY_DISABLE; - WDG->CR = WDG_CR_WDGDIS; - } -} - -/** - * @brief Status of WDG timer while in debug mode. - * @param DBG_STATUS: specifies the staus of WDG timer during debug mode. - * This parameter can be one of the following values: - * @arg WDG_DBG_RUN: The timer continues working in Debug mode. - * @arg WDG_DBG_PAUSE: The timer is paused in Debug mode when the CPU is halted. - * @retval None. - */ -void WDG_DebugConfig(uint32_t DBG_STATUS) -{ - /* Check the parameters */ - assert_param(IS_WDG_DEBUG_STATUS(DBG_STATUS)); - - SLPTMR->CR = DBG_STATUS; -} - -/** - * @brief Returns the status of WDG timer. - * @param None - * @retval None - */ -FunctionalState WDG_GetStatus(void) -{ - FunctionalState wdgstatus = DISABLE; - - if ((WDG->CR & WDG_CR_WDGEN) == WDG_CR_WDGEN) - { - wdgstatus = ENABLE; - } - else - { - wdgstatus = DISABLE; - } - return wdgstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libs/stm32w108xx.ld.in b/libs/stm32w108xx.ld.in deleted file mode 120000 index fa64894..0000000 --- a/libs/stm32w108xx.ld.in +++ /dev/null @@ -1 +0,0 @@ -stm32f10x.ld.in \ No newline at end of file diff --git a/libs/stm32w108xx.mk b/libs/stm32w108xx.mk deleted file mode 100644 index 9d6f5ed..0000000 --- a/libs/stm32w108xx.mk +++ /dev/null @@ -1,29 +0,0 @@ -# The processor! -MCU_CORE=cm3 -# Set up include paths -MCU_INCLUDE += -I$(LIBDIR)/CMSIS/Device/ST/STM32W108xx/Include -MCU_INCLUDE += -I$(LIBDIR)/STM32W108xx_StdPeriph_Driver/inc - -# Set up CFLAGS -MCU_CPPFLAGS += -D$(shell echo -n $(MCU_SUBTYPE) | tr a-z A-Z ) -MCU_CPPFLAGS += -D"assert_param(expr)=((void)0)" -MCU_CFLAGS += -mcpu=cortex-m3 -mthumb -Wa,-mthumb -MCU_CXXFLAGS += -mcpu=cortex-m3 -mthumb -Wa,-mthumb - -# CMSIS -STM32W108xx_OBJS = $(LIBDIR)/CMSIS/Device/ST/STM32W108xx/Source/Templates/system_stm32w108xx.o -# Standard Peripheral Library -STM32W108xx_OBJSR = stm32w108xx_adc.o stm32w108xx_gpio.o stm32w108xx_sc.o \ - stm32w108xx_clk.o stm32w108xx_misc.o stm32w108xx_slptim.o \ - stm32w108xx_exti.o stm32w108xx_pwr.o stm32w108xx_tim.o \ - stm32w108xx_flash.o stm32w108xx_rst.o stm32w108xx_wdg.o - -STM32W108xx_OBJS += $(addprefix $(LIBDIR)/STM32W108xx_StdPeriph_Driver/src/,$(STM32W108xx_OBJSR)) - -# Bookkeeping -MCU_LIBS_OBJS += $(STM32W108xx_OBJS) $(LIBDIR)/startup_$(MCU).o - -# Build Rules -$(LIBDIR)/startup_$(MCU).o: $(LIBDIR)/CMSIS/Device/ST/STM32W108xx/Source/Templates/gcc_ride7/startup_$(MCU).s - @$(E) " AS " $@ - $(Q)$(AS) -c -o $@ $<