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Nuke support for stm32w family (EOL'd in 2017 by ST)

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Solomon Peachy 2019-12-15 00:25:02 -05:00
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7
Makefile.opts.sample
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@ -29,13 +29,6 @@ MCU_SUBTYPE=stm32f446xx
#MCU_SUBTYPE=stm32l1xx_mdp
#MCU_SUBTYPE=stm32l1xx_hd
#MCU=stm32w108xx
#MCU_SUBTYPE=stm32w108c8
#MCU_SUBTYPE=stm32w108cc
#MCU_SUBTYPE=stm32w108cz
#MCU_SUBTYPE=stm32w108db
#MCU_SUBTYPE=stm32w108hz
#MCU=stm32f30x
#MCU=stm32f37x

1967
libs/CMSIS/Device/ST/STM32W108xx/Include/stm32w108xx.h
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libs/CMSIS/Device/ST/STM32W108xx/Include/system_stm32w108xx.h
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@ -1,104 +0,0 @@
/**
******************************************************************************
* @file system_stm32w108xx.h
* @author MCD Application Team
* @version V1.0.1
* @date 30-November-2012
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32w108xx_system
* @{
*/
/**
* @brief Define to prevent recursive inclusion
*/
#ifndef __SYSTEM_STM32W108XX_H
#define __SYSTEM_STM32W108XX_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup STM32W108xx_System_Includes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32W108xx_System_Exported_types
* @{
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* @}
*/
/** @addtogroup STM32W108xx_System_Exported_Constants
* @{
*/
/**
* @}
*/
/** @addtogroup STM32W108xx_System_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32W108xx_System_Exported_Functions
* @{
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__SYSTEM_STM32W108XX_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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libs/CMSIS/Device/ST/STM32W108xx/Release_Notes.html
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@ -1,333 +0,0 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns="http://www.w3.org/TR/REC-html40"><head>
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
<link rel="File-List" href="Release_Notes%20%28package%29_files/filelist.xml">
<link rel="Edit-Time-Data" href="Release_Notes%20%28package%29_files/editdata.mso"><!--[if !mso]> <style> v\:* {behavior:url(#default#VML);} o\:* {behavior:url(#default#VML);} w\:* {behavior:url(#default#VML);} .shape {behavior:url(#default#VML);} </style> <![endif]--><title>Release Notes for STM32W108xx CMSIS</title><!--[if gte mso 9]><xml> <o:DocumentProperties> <o:Author>STMicroelectronics</o:Author> <o:LastAuthor>tguilhot</o:LastAuthor> <o:Revision>145</o:Revision> <o:TotalTime>461</o:TotalTime> <o:Created>2009-02-27T19:26:00Z</o:Created> <o:LastSaved>2010-12-13T14:14:00Z</o:LastSaved> <o:Pages>1</o:Pages> <o:Words>358</o:Words> <o:Characters>2045</o:Characters> <o:Company>STMicroelectronics</o:Company> <o:Lines>17</o:Lines> <o:Paragraphs>4</o:Paragraphs> <o:CharactersWithSpaces>2399</o:CharactersWithSpaces> <o:Version>11.9999</o:Version> </o:DocumentProperties> </xml><![endif]--><!--[if gte mso 9]><xml> <w:WordDocument> <w:View>Normal</w:View> <w:SpellingState>Clean</w:SpellingState> <w:GrammarState>Clean</w:GrammarState> <w:ValidateAgainstSchemas/> <w:SaveIfXMLInvalid>false</w:SaveIfXMLInvalid> <w:IgnoreMixedContent>false</w:IgnoreMixedContent> <w:AlwaysShowPlaceholderText>false</w:AlwaysShowPlaceholderText> <w:Compatibility> <w:UseFELayout/> </w:Compatibility> <w:BrowserLevel>MicrosoftInternetExplorer4</w:BrowserLevel> </w:WordDocument> </xml><![endif]--><!--[if gte mso 9]><xml> <w:LatentStyles DefLockedState="false" LatentStyleCount="156"> </w:LatentStyles> </xml><![endif]-->
<style>
<!--
/* Font Definitions */
@font-face
{font-family:Wingdings;
panose-1:5 0 0 0 0 0 0 0 0 0;
mso-font-charset:2;
mso-generic-font-family:auto;
mso-font-pitch:variable;
mso-font-signature:0 268435456 0 0 -2147483648 0;}
@font-face
{font-family:"MS Mincho";
panose-1:2 2 6 9 4 2 5 8 3 4;
mso-font-alt:"Arial Unicode MS";
mso-font-charset:128;
mso-generic-font-family:roman;
mso-font-format:other;
mso-font-pitch:fixed;
mso-font-signature:1 134676480 16 0 131072 0;}
@font-face
{font-family:Verdana;
panose-1:2 11 6 4 3 5 4 4 2 4;
mso-font-charset:0;
mso-generic-font-family:swiss;
mso-font-pitch:variable;
mso-font-signature:536871559 0 0 0 415 0;}
@font-face
{font-family:"\@MS Mincho";
panose-1:0 0 0 0 0 0 0 0 0 0;
mso-font-charset:128;
mso-generic-font-family:roman;
mso-font-format:other;
mso-font-pitch:fixed;
mso-font-signature:1 134676480 16 0 131072 0;}
/* Style Definitions */
p.MsoNormal, li.MsoNormal, div.MsoNormal
{mso-style-parent:"";
margin:0cm;
margin-bottom:.0001pt;
mso-pagination:widow-orphan;
font-size:12.0pt;
font-family:"Times New Roman";
mso-fareast-font-family:"Times New Roman";}
h1
{mso-margin-top-alt:auto;
margin-right:0cm;
mso-margin-bottom-alt:auto;
margin-left:0cm;
mso-pagination:widow-orphan;
mso-outline-level:1;
font-size:24.0pt;
font-family:"Times New Roman";
mso-fareast-font-family:"MS Mincho";
font-weight:bold;}
h2
{mso-style-next:Normal;
margin-top:12.0pt;
margin-right:0cm;
margin-bottom:3.0pt;
margin-left:0cm;
mso-pagination:widow-orphan;
page-break-after:avoid;
mso-outline-level:2;
font-size:14.0pt;
font-family:Arial;
mso-fareast-font-family:"MS Mincho";
font-weight:bold;
font-style:italic;}
h3
{mso-margin-top-alt:auto;
margin-right:0cm;
mso-margin-bottom-alt:auto;
margin-left:0cm;
mso-pagination:widow-orphan;
mso-outline-level:3;
font-size:13.5pt;
font-family:"Times New Roman";
mso-fareast-font-family:"MS Mincho";
font-weight:bold;}
a:link, span.MsoHyperlink
{color:blue;
text-decoration:underline;
text-underline:single;}
a:visited, span.MsoHyperlinkFollowed
{color:blue;
text-decoration:underline;
text-underline:single;}
p
{mso-margin-top-alt:auto;
margin-right:0cm;
mso-margin-bottom-alt:auto;
margin-left:0cm;
mso-pagination:widow-orphan;
font-size:12.0pt;
font-family:"Times New Roman";
mso-fareast-font-family:"Times New Roman";}
@page Section1
{size:612.0pt 792.0pt;
margin:72.0pt 90.0pt 72.0pt 90.0pt;
mso-header-margin:36.0pt;
mso-footer-margin:36.0pt;
mso-paper-source:0;}
div.Section1
{page:Section1;}
/* List Definitions */
@list l0
{mso-list-id:1315182333;
mso-list-template-ids:555131286;}
@list l0:level1
{mso-level-tab-stop:36.0pt;
mso-level-number-position:left;
text-indent:-18.0pt;}
@list l0:level2
{mso-level-tab-stop:72.0pt;
mso-level-number-position:left;
text-indent:-18.0pt;}
@list l0:level3
{mso-level-tab-stop:108.0pt;
mso-level-number-position:left;
text-indent:-18.0pt;}
@list l0:level4
{mso-level-tab-stop:144.0pt;
mso-level-number-position:left;
text-indent:-18.0pt;}
@list l0:level5
{mso-level-tab-stop:180.0pt;
mso-level-number-position:left;
text-indent:-18.0pt;}
@list l0:level6
{mso-level-tab-stop:216.0pt;
mso-level-number-position:left;
text-indent:-18.0pt;}
@list l0:level7
{mso-level-tab-stop:252.0pt;
mso-level-number-position:left;
text-indent:-18.0pt;}
@list l0:level8
{mso-level-tab-stop:288.0pt;
mso-level-number-position:left;
text-indent:-18.0pt;}
@list l0:level9
{mso-level-tab-stop:324.0pt;
mso-level-number-position:left;
text-indent:-18.0pt;}
@list l1
{mso-list-id:2024673066;
mso-list-template-ids:154433278;}
@list l1:level1
{mso-level-number-format:bullet;
mso-level-text:\F0A7;
mso-level-tab-stop:36.0pt;
mso-level-number-position:left;
text-indent:-18.0pt;
mso-ansi-font-size:10.0pt;
font-family:Wingdings;}
@list l1:level2
{mso-level-number-format:bullet;
mso-level-text:\F0B7;
mso-level-tab-stop:72.0pt;
mso-level-number-position:left;
text-indent:-18.0pt;
mso-ansi-font-size:10.0pt;
font-family:Symbol;}
@list l1:level3
{mso-level-number-format:bullet;
mso-level-text:\F0B0;
mso-level-tab-stop:108.0pt;
mso-level-number-position:left;
text-indent:-18.0pt;
font-family:Symbol;}
@list l1:level4
{mso-level-tab-stop:144.0pt;
mso-level-number-position:left;
text-indent:-18.0pt;}
@list l1:level5
{mso-level-tab-stop:180.0pt;
mso-level-number-position:left;
text-indent:-18.0pt;}
@list l1:level6
{mso-level-tab-stop:216.0pt;
mso-level-number-position:left;
text-indent:-18.0pt;}
@list l1:level7
{mso-level-tab-stop:252.0pt;
mso-level-number-position:left;
text-indent:-18.0pt;}
@list l1:level8
{mso-level-tab-stop:288.0pt;
mso-level-number-position:left;
text-indent:-18.0pt;}
@list l1:level9
{mso-level-tab-stop:324.0pt;
mso-level-number-position:left;
text-indent:-18.0pt;}
@list l2
{mso-list-id:2095200852;
mso-list-type:hybrid;
mso-list-template-ids:-391638944 67698693 67698691 67698693 67698689 67698691 67698693 67698689 67698691 67698693;}
@list l2:level1
{mso-level-number-format:bullet;
mso-level-text:\F0A7;
mso-level-tab-stop:36.0pt;
mso-level-number-position:left;
text-indent:-18.0pt;
font-family:Wingdings;}
@list l2:level2
{mso-level-tab-stop:72.0pt;
mso-level-number-position:left;
text-indent:-18.0pt;}
@list l2:level3
{mso-level-tab-stop:108.0pt;
mso-level-number-position:left;
text-indent:-18.0pt;}
@list l2:level4
{mso-level-tab-stop:144.0pt;
mso-level-number-position:left;
text-indent:-18.0pt;}
@list l2:level5
{mso-level-tab-stop:180.0pt;
mso-level-number-position:left;
text-indent:-18.0pt;}
@list l2:level6
{mso-level-tab-stop:216.0pt;
mso-level-number-position:left;
text-indent:-18.0pt;}
@list l2:level7
{mso-level-tab-stop:252.0pt;
mso-level-number-position:left;
text-indent:-18.0pt;}
@list l2:level8
{mso-level-tab-stop:288.0pt;
mso-level-number-position:left;
text-indent:-18.0pt;}
@list l2:level9
{mso-level-tab-stop:324.0pt;
mso-level-number-position:left;
text-indent:-18.0pt;}
ol
{margin-bottom:0cm;}
ul
{margin-bottom:0cm;}
-->
</style><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0cm 5.4pt 0cm 5.4pt; mso-para-margin:0cm; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman"; mso-fareast-font-family:"Times New Roman"; mso-ansi-language:#0400; mso-fareast-language:#0400; mso-bidi-language:#0400;} </style> <![endif]-->
<style type="disc">
</style><!--[if gte mso 9]><xml> <o:shapedefaults v:ext="edit" spidmax="45058"/> </xml><![endif]--><!--[if gte mso 9]><xml> <o:shapelayout v:ext="edit"> <o:idmap v:ext="edit" data="1"/> </o:shapelayout></xml><![endif]--><meta content="MCD Application Team" name="author"></head>
<body link="blue" vlink="blue">
<div class="Section1">
<p class="MsoNormal"><span style="font-family: Arial;"><br>
</span><span style="font-family: Arial;"><o:p></o:p></span></p>
<div align="center">
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
<tbody>
<tr style="">
<td style="padding: 0cm;" valign="top">
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
<tbody>
<tr style="">
<td style="padding: 1.5pt;">
<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
Notes for<o:p></o:p> STM32W108xx CMSIS<br>
</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright 2012 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../../../../_htmresc/logo.bmp" style="border: 0px solid ; width: 86px; height: 65px;"></span></p>
</td>
</tr>
</tbody>
</table>
<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p>&nbsp;</o:p></span></p>
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
<tbody>
<tr style="">
<td style="padding: 0cm;" valign="top">
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>
<ol style="margin-top: 0cm;" start="1" type="1">
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32W108xx CMSIS update history</a><o:p></o:p></span></li>
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>
</ol>
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32W108xx CMSIS update history<o:p></o:p></span></h2><span style="color: black;"><o:p></o:p></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 186px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.1 /30-November-2012</span></h3>
<span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;"><span style="font-weight: bold;"></span></span></span>
<span style="font-size: 10pt; font-family: Verdana;"></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 23px; width: 868px;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Development Toolchains<o:p></o:p></span></u></b></p>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">IAR Embedded Workbench for ARM (EWARM) toolchain V6.40<br>
</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;" lang="EN-US">Keil (MDK-ARM)&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">toolchain V4.54</span><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;" lang="EN-US"> </span><span style="font-size: 10pt; font-family: Verdana;"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;" lang="EN-US">TASKING VX-toolset for ARM Cortex-M3</span><b style=""><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;" lang="EN-US">&nbsp;</span></b><span style="font-size: 10pt; font-family: Verdana;">toolchain V4.2r1</span></li></ul><span style="font-size: 10pt; font-family: Verdana;"></span>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Raisonance IDE RIDE7
(RIDE)&nbsp;toolchain V7.40</span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Atollic TrueSTUDIO STM32
(TrueSTUDIO)&nbsp;toolchain V3.2.0</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 186px; margin-right: 500pt;"><span style="font-family: Arial; color: white; font-size: 10pt;">V1.0.0 /
09-October-2012</span></h3>
<p style="margin: 4.5pt 0cm 4.5pt 18pt;" class="MsoNormal"><b><u><span style="font-family: Verdana; color: black; font-size: 10pt;">Main
Changes<o:p></o:p></span></u></b></p><span style="font-family: Verdana; font-size: 10pt;">&nbsp; &nbsp; &nbsp;First official release
for </span><span style="font-family: Verdana; font-size: 10pt;"><span style="font-style: italic; font-weight: bold;">STM32W108xx</span></span><span style="font-family: Verdana; font-size: 10pt;"><span style="font-style: italic; font-weight: bold;"> devices </span></span><span style="font-family: Verdana; font-size: 10pt;">running on MBxxx
boards </span><br> <span style="font-family: Verdana; color: black; font-size: 10pt;"><o:p></o:p></span><span style="font-family: Verdana; font-size: 10pt;"></span><span style="font-family: Verdana; font-size: 10pt;"><span style="text-decoration: underline;"><span style="font-weight: bold;"></span></span></span><span style="font-family: Verdana; font-size: 10pt;"></span>
<p style="margin: 4.5pt 0cm 4.5pt 23px; width: 868px;" class="MsoNormal"><b><u><span style="font-family: Verdana; color: black; font-size: 10pt;">Development
Toolchains<o:p></o:p></span></u></b></p>
<span style="font-family: Verdana; font-size: 10pt;">&nbsp; &nbsp; &nbsp;IAR Embedded
Workbench for ARM (EWARM) toolchain V6.40</span><span style="font-size: 10pt; font-family: Verdana;"></span><ul style="margin-top: 0cm;" type="square"></ul>
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
<p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">package</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"> except in compliance with the License. You may obtain a copy of the License at:<br><br></span></p><div style="text-align: center;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a target="_blank" href="http://www.st.com/software_license_agreement_liberty_v2">http://www.st.com/software_license_agreement_liberty_v2</a></span><br><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"></span></div><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"><br>Unless
required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS, <br>WITHOUT
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See
the License for the specific language governing permissions and
limitations under the License.</span><p class="MsoNormal" style="margin: 4.5pt 0cm;"><b><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></b><span style="font-size: 10pt; font-family: Verdana; color: black;"><o:p></o:p></span></p>
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<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STMicroelectronics<span style="color: black;"> Microcontrollers visit </span><a target="_blank" href="http://www.st.com/internet/mcu/family/141.jsp"><u><span style="color: blue;">www.st.com</span></u></a></span><span style="color: black;"><o:p></o:p></span></p>
</td>
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</body></html>

266
libs/CMSIS/Device/ST/STM32W108xx/Source/Templates/TrueSTUDIO/startup_stm32w108xx.s
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@ -1,266 +0,0 @@
/**
******************************************************************************
* @file : startup_stm32w108xx.s
* Author : MCD Application Team
* Version : V0.0.1RC1
* Date : 18-April-2012
* @brief : stm32w108xx Devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the cortex-m3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF108F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M0. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word TIM1_IRQHandler
.word TIM2_IRQHandler
.word MNG_IRQHandler
.word BASEBAND_IRQHandler
.word SLPTIM_IRQHandler
.word SC1_IRQHandler
.word SC2_IRQHandler
.word SECURITY_IRQHandler
.word MAC_TIM_IRQHandler
.word MAC_TR_IRQHandler
.word MAC_RE_IRQHandler
.word ADC_IRQHandler
.word EXTIA_IRQHandler
.word EXTIB_IRQHandler
.word EXTIC_IRQHandler
.word EXTID_IRQHandler
.word DEBUG_IRQHandler
.word BootRAM /* @0x108. This is for boot in RAM mode for
stm32w108xx devices. */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak TIM1_IRQHandler
.thumb_set TIM1_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak MNG_IRQHandler
.thumb_set MNG_IRQHandler,Default_Handler
.weak BASEBAND_IRQHandler
.thumb_set BASEBAND_IRQHandler,Default_Handler
.weak SLPTIM_IRQHandler
.thumb_set SLPTIM_IRQHandler,Default_Handler
.weak SC1_IRQHandler
.thumb_set SC1_IRQHandler,Default_Handler
.weak SC2_IRQHandler
.thumb_set SC2_IRQHandler,Default_Handler
.weak SECURITY_IRQHandler
.thumb_set SECURITY_IRQHandler,Default_Handler
.weak MAC_TIM_IRQHandler
.thumb_set MAC_TIM_IRQHandler,Default_Handler
.weak MAC_TR_IRQHandler
.thumb_set MAC_TR_IRQHandler,Default_Handler
.weak MAC_RE_IRQHandler
.thumb_set MAC_RE_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak EXTIA_IRQHandler
.thumb_set EXTIA_IRQHandler,Default_Handler
.weak EXTIB_IRQHandler
.thumb_set EXTIB_IRQHandler,Default_Handler
.weak EXTIC_IRQHandler
.thumb_set EXTIC_IRQHandler,Default_Handler
.weak EXTID_IRQHandler
.thumb_set EXTID_IRQHandler,Default_Handler
.weak DEBUG_IRQHandler
.thumb_set DEBUG_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

231
libs/CMSIS/Device/ST/STM32W108xx/Source/Templates/arm/startup_stm32w108xx.s
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@ -1,231 +0,0 @@
;/**************************************************************************//**
; * @file startup_stm32w108.s
; * @brief CMSIS Core Device Startup File for
; * STM32W108 Device Series
; * @version V1.0.1
; * @date 30 November 2012
; *
; * @note
; * Copyright (C) 2012 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00001000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD TIM1_IRQHandler ; 16+ 0 Timer 1 Interrupt
DCD TIM2_IRQHandler ; 16+ 1 Timer 2 Interrupt
DCD MNG_IRQHandler ; 16+ 2 Management Peripheral Interrupt
DCD BASEBAND_IRQHandler ; 16+ 3 Base Band Interrupt
DCD SLPTIM_IRQHandler ; 16+ 4 Sleep Timer Interrupt
DCD SC1_IRQHandler ; 16+ 5 Serial Controller 1 Interrupt
DCD SC2_IRQHandler ; 16+ 6 Serial Controller 2 Interrupt
DCD SECURITY_IRQHandler ; 16+ 7 Security Interrupt
DCD MAC_TIM_IRQHandler ; 16+ 8 MAC Timer Interrupt
DCD MAC_TR_IRQHandler ; 16+ 9 MAC Transmit Interrupt
DCD MAC_RE_IRQHandler ; 16+10 MAC Receive Interrupt
DCD ADC_IRQHandler ; 16+11 ADC Interrupt
DCD EXTIA_IRQHandler ; 16+12 EXTIA Interrupt
DCD EXTIB_IRQHandler ; 16+13 EXTIB Interrupt
DCD EXTIC_IRQHandler ; 16+14 EXTIC Interrupt
DCD EXTID_IRQHandler ; 16+15 EXTID Interrupt
DCD DEBUG_IRQHandler ; 16+16 Debug Interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT TIM1_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT MNG_IRQHandler [WEAK]
EXPORT BASEBAND_IRQHandler [WEAK]
EXPORT SLPTIM_IRQHandler [WEAK]
EXPORT SC1_IRQHandler [WEAK]
EXPORT SC2_IRQHandler [WEAK]
EXPORT SECURITY_IRQHandler [WEAK]
EXPORT MAC_TIM_IRQHandler [WEAK]
EXPORT MAC_TR_IRQHandler [WEAK]
EXPORT MAC_RE_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT EXTIA_IRQHandler [WEAK]
EXPORT EXTIB_IRQHandler [WEAK]
EXPORT EXTIC_IRQHandler [WEAK]
EXPORT EXTID_IRQHandler [WEAK]
EXPORT DEBUG_IRQHandler [WEAK]
TIM1_IRQHandler
TIM2_IRQHandler
MNG_IRQHandler
BASEBAND_IRQHandler
SLPTIM_IRQHandler
SC1_IRQHandler
SC2_IRQHandler
SECURITY_IRQHandler
MAC_TIM_IRQHandler
MAC_TR_IRQHandler
MAC_RE_IRQHandler
ADC_IRQHandler
EXTIA_IRQHandler
EXTIB_IRQHandler
EXTIC_IRQHandler
EXTID_IRQHandler
DEBUG_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

252
libs/CMSIS/Device/ST/STM32W108xx/Source/Templates/gcc_ride7/startup_stm32w108xx.s
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@ -1,252 +0,0 @@
/**
******************************************************************************
* @file : startup_stm32w108xx.s
* Author : MCD Application Team
* Version : V0.0.1RC1
* Date : 18-April-2012
* @brief : stm32w108xx Devices vector table for Ride toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the cortex-m3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF108F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word TIM1_IRQHandler
.word TIM2_IRQHandler
.word MNG_IRQHandler
.word BASEBAND_IRQHandler
.word SLPTIM_IRQHandler
.word SC1_IRQHandler
.word SC2_IRQHandler
.word SECURITY_IRQHandler
.word MAC_TIM_IRQHandler
.word MAC_TR_IRQHandler
.word MAC_RE_IRQHandler
.word ADC_IRQHandler
.word EXTIA_IRQHandler
.word EXTIB_IRQHandler
.word EXTIC_IRQHandler
.word EXTID_IRQHandler
.word DEBUG_IRQHandler
.word BootRAM /* @0x108. This is for boot in RAM mode for
stm32w108xx devices. */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak TIM1_IRQHandler
.thumb_set TIM1_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak MNG_IRQHandler
.thumb_set MNG_IRQHandler,Default_Handler
.weak BASEBAND_IRQHandler
.thumb_set BASEBAND_IRQHandler,Default_Handler
.weak SLPTIM_IRQHandler
.thumb_set SLPTIM_IRQHandler,Default_Handler
.weak SC1_IRQHandler
.thumb_set SC1_IRQHandler,Default_Handler
.weak SC2_IRQHandler
.thumb_set SC2_IRQHandler,Default_Handler
.weak SECURITY_IRQHandler
.thumb_set SECURITY_IRQHandler,Default_Handler
.weak MAC_TIM_IRQHandler
.thumb_set MAC_TIM_IRQHandler,Default_Handler
.weak MAC_TR_IRQHandler
.thumb_set MAC_TR_IRQHandler,Default_Handler
.weak MAC_RE_IRQHandler
.thumb_set MAC_RE_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak EXTIA_IRQHandler
.thumb_set EXTIA_IRQHandler,Default_Handler
.weak EXTIB_IRQHandler
.thumb_set EXTIB_IRQHandler,Default_Handler
.weak EXTIC_IRQHandler
.thumb_set EXTIC_IRQHandler,Default_Handler
.weak EXTID_IRQHandler
.thumb_set EXTID_IRQHandler,Default_Handler
.weak DEBUG_IRQHandler
.thumb_set DEBUG_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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libs/CMSIS/Device/ST/STM32W108xx/Source/Templates/iar/startup_stm32w108xx.s
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@ -1,261 +0,0 @@
;/******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
;* File Name : startup_stm32w108xx.s
;* Author : MCD Application Team
;* Version : V1.0.1
;* Date : 30-November-2012
;* Description : STM32W108xx RF High Performance Devices vector table for *
;* EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************/
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD TIM1_IRQHandler ; Timer 1 Interrupt
DCD TIM2_IRQHandler ; Timer 2 Interrupt
DCD MNG_IRQHandler ; Management Peripheral Interrupt
DCD BASEBAND_IRQHandler ; Base Band Interrupt
DCD SLPTIM_IRQHandler ; Sleep Timer Interrupt
DCD SC1_IRQHandler ; Serial Controller 1 Interrupt
DCD SC2_IRQHandler ; Serial Controller 2 Interrupt
DCD SECURITY_IRQHandler ; Security Interrupt
DCD MAC_TIM_IRQHandler ; MAC Timer Interrupt
DCD MAC_TR_IRQHandler ; MAC Transmit Interrupt
DCD MAC_RE_IRQHandler ; MAC Receive Interrupt
DCD ADC_IRQHandler ; ADC Interrupt
DCD EXTIA_IRQHandler ; EXTIA Interrupt
DCD EXTIB_IRQHandler ; EXTIB Interrupt
DCD EXTIC_IRQHandler ; EXTIC Interrupt
DCD EXTID_IRQHandler ; EXTID Interrupt
DCD DEBUG_IRQHandler ; Debug Interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK TIM1_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_IRQHandler
B TIM1_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK MNG_IRQHandler
SECTION .text:CODE:REORDER(1)
MNG_IRQHandler
B MNG_IRQHandler
PUBWEAK BASEBAND_IRQHandler
SECTION .text:CODE:REORDER(1)
BASEBAND_IRQHandler
B BASEBAND_IRQHandler
PUBWEAK SLPTIM_IRQHandler
SECTION .text:CODE:REORDER(1)
SLPTIM_IRQHandler
B SLPTIM_IRQHandler
PUBWEAK SC1_IRQHandler
SECTION .text:CODE:REORDER(1)
SC1_IRQHandler
B SC1_IRQHandler
PUBWEAK SC2_IRQHandler
SECTION .text:CODE:REORDER(1)
SC2_IRQHandler
B SC2_IRQHandler
PUBWEAK SECURITY_IRQHandler
SECTION .text:CODE:REORDER(1)
SECURITY_IRQHandler
B SECURITY_IRQHandler
PUBWEAK MAC_TIM_IRQHandler
SECTION .text:CODE:REORDER(1)
MAC_TIM_IRQHandler
B MAC_TIM_IRQHandler
PUBWEAK MAC_TR_IRQHandler
SECTION .text:CODE:REORDER(1)
MAC_TR_IRQHandler
B MAC_TR_IRQHandler
PUBWEAK MAC_RE_IRQHandler
SECTION .text:CODE:REORDER(1)
MAC_RE_IRQHandler
B MAC_RE_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK EXTIA_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTIA_IRQHandler
B EXTIA_IRQHandler
PUBWEAK EXTIB_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTIB_IRQHandler
B EXTIB_IRQHandler
PUBWEAK EXTIC_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTIC_IRQHandler
B EXTIC_IRQHandler
PUBWEAK EXTID_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTID_IRQHandler
B EXTID_IRQHandler
PUBWEAK DEBUG_IRQHandler
SECTION .text:CODE:REORDER(1)
DEBUG_IRQHandler
B DEBUG_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file system_stm32w108xx.c
* @author MCD Application Team
* @version V1.0.1
* @date 30-November-2012
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): Setups the system clock (System clock source).
* This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32w108xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* 2. After each device reset the HSI (12 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32w108xx.s" file, to
* configure the system clock before to branch to main program.
*
* 3. If the system clock source selected by user fails to startup, the SystemInit()
* function will do nothing and HSI still used as system clock source. User can
* add some code to deal with this issue inside the SetSysClock() function.
*
* 4. The default value of HSE crystal is set to 24MHz, refer to "HSE_VALUE" define
* in "stm32w108xx.h" file. When HSE is used as system clock source, directly or
* through PLL, and you are using different crystal you have to adapt the HSE
* value to your own configuration.
*
* 5. This file configures the system clock as follows:
*=============================================================================
* System Clock Configuration
*=============================================================================
* System Clock source | HSE
*-----------------------------------------------------------------------------
* SYSCLK | 24000000 Hz
*-----------------------------------------------------------------------------
* HCLK | 24000000 Hz
*-----------------------------------------------------------------------------
* FCLK | 12000000 Hz
*-----------------------------------------------------------------------------
* PCLK = SYSCLK/2 | 12000000 Hz
*-----------------------------------------------------------------------------
* HSE Frequency | 24000000 Hz
*-----------------------------------------------------------------------------
* VDD | 3.3 V
*-----------------------------------------------------------------------------
* Flash Latency | 1 WS
*-----------------------------------------------------------------------------
*=============================================================================
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32w108xx_system
* @{
*/
/** @addtogroup STM32W108xx_System_Private_Includes
* @{
*/
#include "stm32w108xx.h"
/**
* @}
*/
/** @addtogroup STM32W108xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32W108xx_System_Private_Defines
* @{
*/
/**
* @}
*/
/** @addtogroup STM32W108xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32W108xx_System_Private_Variables
* @{
*/
uint32_t SystemCoreClock = 24000000;
/**
* @}
*/
/** @addtogroup STM32W108xx_System_Private_FunctionPrototypes
* @{
*/
static void SetSysClock(void);
/**
* @}
*/
/** @addtogroup STM32W108xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system.
* Initialize the Embedded Flash Interface, the PLL and update the
* SystemCoreClock variable.
* @param None
* @retval None
*/
void SystemInit (void)
{
/* reset the CLK_HSECR2 register */
CLK->HSECR2 &= (uint32_t)0x00000000;
/* reset the CLK_CPUCR register */
CLK->CPUCR &= (uint32_t)0x00000000;
/* Configure the System clock frequency */
SetSysClock();
}
/**
* @brief Update SystemCoreClock according to Clock Register Values
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* (*) HSI_VALUE is a constant defined in stm32w108xx.h file (default value
* 12 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32w108xx.h file (default value
* 24 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp = 0;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = (CLK->HSECR2) & (uint32_t)0x0000003;
if (tmp == 0x0000003) /* HSE used as system clock */
{
SystemCoreClock = HSE_VALUE;
}
else /* HSI used as system clock */
{
SystemCoreClock = HSI_VALUE;
}
}
/**
* @brief Configures the System clock frequency,
* @note This function should be called only once the CLOCK configuration
* is reset to the default reset state (done in SystemInit() function).
* @param None
* @retval None
*/
static void SetSysClock(void)
{
__IO uint32_t StartUpCounter = 0;
/* Enable HSE */
CLK->HSECR2 |= CLK_HSECR2_EN;
/* Wait till HSE is ready and if Time out is reached exit */
do
{
StartUpCounter++;
} while(StartUpCounter != HSE_STARTUP_TIMEOUT);
/* Select HSE system clock */
CLK->HSECR2 |= CLK_HSECR2_SW1;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/* Style Definitions */
p.MsoNormal, li.MsoNormal, div.MsoNormal
{mso-style-parent:"";
margin:0in;
margin-bottom:.0001pt;
mso-pagination:widow-orphan;
font-size:12.0pt;
font-family:"Times New Roman";
mso-fareast-font-family:"Times New Roman";}
h2
{mso-style-next:Normal;
margin-top:12.0pt;
margin-right:0in;
margin-bottom:3.0pt;
margin-left:0in;
mso-pagination:widow-orphan;
page-break-after:avoid;
mso-outline-level:2;
font-size:14.0pt;
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font-weight:bold;
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a:link, span.MsoHyperlink
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mso-fareast-font-family:"Times New Roman";}
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margin:1.0in 1.25in 1.0in 1.25in;
mso-header-margin:.5in;
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-->
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<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
Notes for STM32W108xx Standard Peripherals Library Drivers
(StdPeriph_Driver)</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright 2012 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../_htmresc/logo.bmp" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
</td>
</tr>
</tbody>
</table>
<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p>&nbsp;</o:p></span></p>
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
<tbody>
<tr style="">
<td style="padding: 0cm;" valign="top">
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>
<ol style="margin-top: 0cm;" start="1" type="1">
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32W108xx Standard Peripherals Library
Drivers update History</a><o:p></o:p></span></li>
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>
</ol>
<span style="font-family: &quot;Times New Roman&quot;;">
</span>
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32W108xx Standard
Peripherals Library Drivers&nbsp; update History</span></h2><br><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 186px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.1 /30-November-2012</span></h3>
<span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;"><span style="font-weight: bold;"></span></span></span>
<span style="font-size: 10pt; font-family: Verdana;"></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b><b><i><span style="font-family: Verdana; font-size: 10pt;"></span></i></b><i><span style="font-family: Verdana; font-size: 10pt;">&nbsp;</span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></p>
<span style="font-family: Verdana; font-size: 10pt;">&nbsp; &nbsp; &nbsp;Add template project for </span><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;" lang="EN-US">MDK-ARM</span><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;" lang="EN-US">,</span><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;" lang="EN-US">TASKING,</span><span style="font-size: 10pt; font-family: Verdana;">RIDE and&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">Atollic toolchains</span><span style="font-family: Verdana; font-size: 10pt;">.</span><span style="font-family: Verdana; font-size: 10pt;"></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 23px; width: 868px;"></p><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 23px; width: 868px;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Development Toolchains<o:p></o:p></span></u></b></p>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">IAR Embedded Workbench for ARM (EWARM) toolchain V6.40<br>
</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;" lang="EN-US">Keil (MDK-ARM)&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">toolchain V4.54</span><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;" lang="EN-US"> </span><span style="font-size: 10pt; font-family: Verdana;"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;" lang="EN-US">TASKING VX-toolset for ARM Cortex-M3</span><b style=""><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;" lang="EN-US">&nbsp;</span></b><span style="font-size: 10pt; font-family: Verdana;">toolchain V4.2r1</span></li></ul><span style="font-size: 10pt; font-family: Verdana;"></span>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Raisonance IDE RIDE7
(RIDE)&nbsp;toolchain V7.40</span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Atollic TrueSTUDIO STM32
(TrueSTUDIO)&nbsp;toolchain V3.2.0</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 186px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 09-October-2012</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<span style="font-size: 10pt; font-family: Verdana;">&nbsp; &nbsp; &nbsp;First official release for&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">STM32W108xx</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;"> devices </span></span><span style="font-size: 10pt; font-family: Verdana;"> running on MBxxx boards&nbsp;<br><br></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 23px; width: 868px;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Development Toolchains<o:p></o:p></span></u></b></p><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">IAR Embedded Workbench for ARM (EWARM) toolchain V6.40
</span></li></ul><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;"><span style="font-weight: bold;"></span></span></span><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2><p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">package</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"> except in compliance with the License. You may obtain a copy of the License at:<br><br></span></p><div style="text-align: center;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a target="_blank" href="http://www.st.com/software_license_agreement_liberty_v2">http://www.st.com/software_license_agreement_liberty_v2</a></span><br><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"></span></div><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"><br>Unless
required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS, <br>WITHOUT
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See
the License for the specific language governing permissions and
limitations under the License.</span><div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
<hr align="center" size="2" width="100%"></span></div>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32(<span style="color: black;">CORTEX M3) 32-Bit Microcontrollers
visit </span><u><span style="color: blue;"><a href="http://www.st.com/stm32" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
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libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_adc.h
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/**
******************************************************************************
* @file stm32w108xx_adc.h
* @author MCD Application Team
* @version V1.0.1
* @date 30-November-2012
* @brief This file contains all the functions prototypes for the ADC firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32W108XX_ADC_H
#define __STM32W108XX_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32w108xx.h"
/** @addtogroup STM32W108xx_StdPeriph_Driver
* @{
*/
/** @addtogroup ADC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief ADC Init structures definition
*/
typedef struct
{
uint32_t ADC_Resolution; /*!< Selects the resolution of the conversion.
This parameter can be a value of ADC_Resolution */
uint32_t ADC_VoltageP; /*!< Selects the voltage range for the P input channel.
This parameter can be a Low voltage range or High voltage range */
uint32_t ADC_VoltageN; /*!< Selects the voltage range for the N input channel.
This parameter can be a Low voltage range or High voltage range */
uint32_t ADC_Input; /*!< Selects the channels.
This parameter must range from 0x0 to 0x5 and from 0x9 to 0xB.
The other values are reserved */
uint32_t ADC_Clock; /*!< Selects the ADC clock.
This parameter must be 0 or 1 */
uint32_t ADC_DMAMode; /*!< Selects the ADC DMA mode.
This parameter must be linear or auto wrap */
int32_t ADC_Offset; /*!< Specifies the offset added to the basic ADC conversion result.
This parameter must be 16 bits signed offset */
uint32_t ADC_Gain; /*!< Specifies the gain factor that is multiplied by the offset-corrected ADC result
to produce the output value.
This parameter must be 16 bits unsigned gain */
}ADC_InitTypeDef;
/** @defgroup ADC_Exported_Constants
* @{
*/
/** @defgroup ADC_resolution
* @{
*/
#define ADC_Resolution_12b ((uint32_t)0x0000E000)
#define ADC_Resolution_11b ((uint32_t)0x0000C000)
#define ADC_Resolution_10b ((uint32_t)0x0000A000)
#define ADC_Resolution_9b ((uint32_t)0x00008000)
#define ADC_Resolution_8b ((uint32_t)0x00006000)
#define ADC_Resolution_7b ((uint32_t)0x00004000)
#define ADC_Resolution_6b ((uint32_t)0x00002000)
#define ADC_Resolution_5b ((uint32_t)0x00000000)
#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
((RESOLUTION) == ADC_Resolution_11b) || \
((RESOLUTION) == ADC_Resolution_10b) || \
((RESOLUTION) == ADC_Resolution_9b) || \
((RESOLUTION) == ADC_Resolution_8b) || \
((RESOLUTION) == ADC_Resolution_7b) || \
((RESOLUTION) == ADC_Resolution_6b) || \
((RESOLUTION) == ADC_Resolution_5b))
/**
* @}
*/
/** @defgroup ADC_VoltageP
* @{
*/
#define ADC_VoltageP_Low ((uint32_t)0x00000000)
#define ADC_VoltageP_High ((uint32_t)0x00001000)
#define IS_ADC_VoltageP(VOLTAGE_P) (((VOLTAGE_P) == ADC_VoltageP_Low) || \
((VOLTAGE_P) == ADC_VoltageP_High))
/**
* @}
*/
/** @defgroup ADC_VoltageN
* @{
*/
#define ADC_VoltageN_Low ((uint32_t)0x00000000)
#define ADC_VoltageN_High ((uint32_t)0x00000800)
#define IS_ADC_VoltageN(VOLTAGE_N) (((VOLTAGE_N) == ADC_VoltageN_Low) || \
((VOLTAGE_N) == ADC_VoltageN_High))
/**
* @}
*/
/** @defgroup ADC_Channels
* @{
*/
#define ADC_MUX_ADC0 ((uint32_t)0x00000000) /* Channel 0 : ADC0 on PB5 */
#define ADC_MUX_ADC1 ((uint32_t)0x00000001) /* Channel 1 : ADC0 on PB6 */
#define ADC_MUX_ADC2 ((uint32_t)0x00000002) /* Channel 2 : ADC0 on PB7 */
#define ADC_MUX_ADC3 ((uint32_t)0x00000003) /* Channel 3 : ADC0 on PC1 */
#define ADC_MUX_ADC4 ((uint32_t)0x00000004) /* Channel 4 : ADC0 on PA4 */
#define ADC_MUX_ADC5 ((uint32_t)0x00000005) /* Channel 5 : ADC0 on PA5 */
#define ADC_MUX_GND ((uint32_t)0x00000008) /* Channel 8 : VSS (0V) - not for high voltage range */
#define ADC_MUX_VREF2 ((uint32_t)0x00000009) /* Channel 9 : VREF/2 (0.6V) */
#define ADC_MUX_VREF ((uint32_t)0x0000000A) /* Channel A : VREF (1.2V)*/
#define ADC_MUX_VREG2 ((uint32_t)0x0000000B) /* Channel B : Regulator/2 (0.9V) - not for high voltage range */
#define ADC_MUXN_BITS ((uint32_t)0x00000004) /* number of bits to shift */
/* ADC_SOURCE_<pos>_<neg> selects <pos> as the positive input and <neg> as the negative input */
#define ADC_SOURCE_ADC0_VREF2 ((ADC_MUX_ADC0 << ADC_MUXN_BITS) | ADC_MUX_VREF2)
#define ADC_SOURCE_ADC0_GND ((ADC_MUX_ADC0 << ADC_MUXN_BITS) | ADC_MUX_GND)
#define ADC_SOURCE_ADC1_VREF2 ((ADC_MUX_ADC1 << ADC_MUXN_BITS) | ADC_MUX_VREF2)
#define ADC_SOURCE_ADC1_GND ((ADC_MUX_ADC1 << ADC_MUXN_BITS) | ADC_MUX_GND)
#define ADC_SOURCE_ADC2_VREF2 ((ADC_MUX_ADC2 << ADC_MUXN_BITS) | ADC_MUX_VREF2)
#define ADC_SOURCE_ADC2_GND ((ADC_MUX_ADC2 << ADC_MUXN_BITS) | ADC_MUX_GND)
#define ADC_SOURCE_ADC3_VREF2 ((ADC_MUX_ADC3 << ADC_MUXN_BITS) | ADC_MUX_VREF2)
#define ADC_SOURCE_ADC3_GND ((ADC_MUX_ADC3 << ADC_MUXN_BITS) | ADC_MUX_GND)
#define ADC_SOURCE_ADC4_VREF2 ((ADC_MUX_ADC4 << ADC_MUXN_BITS) | ADC_MUX_VREF2)
#define ADC_SOURCE_ADC5_VREF2 ((ADC_MUX_ADC5 << ADC_MUXN_BITS) | ADC_MUX_VREF2)
#define ADC_SOURCE_ADC1_ADC0 ((ADC_MUX_ADC1 << ADC_MUXN_BITS) | ADC_MUX_ADC0)
#define ADC_SOURCE_ADC0_ADC1 ((ADC_MUX_ADC1 << ADC_MUXN_BITS) | ADC_MUX_ADC0)
#define ADC_SOURCE_ADC3_ADC2 ((ADC_MUX_ADC3 << ADC_MUXN_BITS) | ADC_MUX_ADC2)
#define ADC_SOURCE_ADC2_ADC3 ((ADC_MUX_ADC3 << ADC_MUXN_BITS) | ADC_MUX_ADC2)
#define ADC_SOURCE_ADC5_ADC4 ((ADC_MUX_ADC5 << ADC_MUXN_BITS) | ADC_MUX_ADC4)
#define ADC_SOURCE_GND_VREF2 ((ADC_MUX_GND << ADC_MUXN_BITS) | ADC_MUX_VREF2)
#define ADC_SOURCE_GND ((ADC_MUX_GND << ADC_MUXN_BITS) | ADC_MUX_GND)
#define ADC_SOURCE_VREF_VREF2 ((ADC_MUX_VREF << ADC_MUXN_BITS) | ADC_MUX_VREF2)
#define ADC_SOURCE_VREF ((ADC_MUX_VREF << ADC_MUXN_BITS) | ADC_MUX_GND)
#define ADC_SOURCE_VREF2_VREF2 ((ADC_MUX_VREF2 << ADC_MUXN_BITS) | ADC_MUX_VREF2)
#define ADC_SOURCE_VREF2 ((ADC_MUX_VREF2 << ADC_MUXN_BITS) | ADC_MUX_GND)
#define ADC_SOURCE_VREG2_VREF2 ((ADC_MUX_VREG2 << ADC_MUXN_BITS) | ADC_MUX_VREF2)
#define ADC_SOURCE_VDD_GND ((ADC_MUX_VREG2 << ADC_MUXN_BITS) | ADC_MUX_GND)
#define IS_ADC_CHANNEL(CHANNELS) (((CHANNELS) == ADC_SOURCE_ADC0_VREF2) || \
((CHANNELS) == ADC_SOURCE_ADC0_GND) || \
((CHANNELS) == ADC_SOURCE_ADC1_VREF2) || \
((CHANNELS) == ADC_SOURCE_ADC1_GND) || \
((CHANNELS) == ADC_SOURCE_ADC2_VREF2) || \
((CHANNELS) == ADC_SOURCE_ADC2_GND) || \
((CHANNELS) == ADC_SOURCE_ADC3_VREF2) || \
((CHANNELS) == ADC_SOURCE_ADC3_GND) || \
((CHANNELS) == ADC_SOURCE_ADC4_VREF2) || \
((CHANNELS) == ADC_SOURCE_ADC5_VREF2) || \
((CHANNELS) == ADC_SOURCE_ADC1_ADC0) || \
((CHANNELS) == ADC_SOURCE_ADC0_ADC1) || \
((CHANNELS) == ADC_SOURCE_ADC3_ADC2) || \
((CHANNELS) == ADC_SOURCE_ADC2_ADC3) || \
((CHANNELS) == ADC_SOURCE_ADC5_ADC4) || \
((CHANNELS) == ADC_SOURCE_GND_VREF2) || \
((CHANNELS) == ADC_SOURCE_GND) || \
((CHANNELS) == ADC_SOURCE_VREF_VREF2) || \
((CHANNELS) == ADC_SOURCE_VREF) || \
((CHANNELS) == ADC_SOURCE_VREF2_VREF2 ) || \
((CHANNELS) == ADC_SOURCE_VREF2) || \
((CHANNELS) == ADC_SOURCE_VREG2_VREF2) || \
((CHANNELS) == ADC_SOURCE_VDD_GND))
/**
* @}
*/
/** @defgroup ADC_DMAMode
* @{
*/
#define ADC_DMAMode_Linear ((uint32_t)0x00000000)
#define ADC_DMAMode_AutoWrap ((uint32_t)0x00000002)
#define IS_ADC_DMA_MODE(MODE) (((MODE) == ADC_DMAMode_Linear) || \
((MODE) == ADC_DMAMode_AutoWrap))
/**
* @}
*/
/** @defgroup ADC_clock
* @{
*/
#define ADC_Clock_1MHz ADC_CR_CLK
#define ADC_Clock_6MHz 0x00000000
#define IS_ADC_CLOCK(CLOCK) (((CLOCK) == ADC_Clock_1MHz) || \
((CLOCK) == ADC_Clock_6MHz))
/**
* @}
*/
/** @defgroup ADC_offset
* @{
*/
#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0x0000FFFF)
/**
* @}
*/
/** @defgroup ADC_gain
* @{
*/
#define IS_ADC_GAIN(GAIN) ((GAIN) <= 0x0000FFFF)
/**
* @}
*/
/** @defgroup ADC_begin
* @{
*/
#if defined STM32W108CC
#define IS_ADC_BEGIN(BEGIN) (((BEGIN) <= 0x20003FFE) && ((BEGIN) >= 0x20000000) && (((BEGIN) & 0x00000001) == 0 ))
#else
#define IS_ADC_BEGIN(BEGIN) (((BEGIN) <= 0x20001FFE) && ((BEGIN) >= 0x20000000) && (((BEGIN) & 0x00000001) == 0 ))
#endif
/**
* @}
*/
/** @defgroup ADC_size
* @{
*/
#if defined STM32W108CC
#define IS_ADC_SIZE(SIZE) ((SIZE) <= 0x00001FFF)
#else
#define IS_ADC_SIZE(SIZE) ((SIZE) <= 0x00000FFF)
#endif
/**
* @}
*/
/** @defgroup ADC_interrupts_definition
* @{
*/
#define ADC_IT_DMABHF ((uint32_t)0x00000002)
#define ADC_IT_DMABF ((uint32_t)0x00000004)
#define ADC_IT_SAT ((uint32_t)0x00000008)
#define ADC_IT_DMAOVF ((uint32_t)0x00000010)
#define IS_ADC_IT(IT) (((IT) == ADC_IT_DMABHF )|| \
((IT) == ADC_IT_DMABF)|| \
((IT) == ADC_IT_SAT)|| \
((IT) == ADC_IT_DMAOVF))
/**
* @}
*/
/** @defgroup ADC_DMA_flags_definition
* @{
*/
#define ADC_FLAG_ACT ((uint32_t)0x00000001)
#define ADC_FLAG_OVF ((uint32_t)0x00000002)
#define IS_ADC_DMA_FLAG(FLAG) (((FLAG) == ADC_FLAG_ACT) || \
((FLAG) == ADC_FLAG_OVF))
/**
* @}
*/
/** @defgroup ADC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup ADC_Exported_Functions
* @{
*/
/* Function used to set the ADC configuration to the default reset state *****/
void ADC_DeInit(void);
/* Initialization and Configuration functions *********************************/
void ADC_Init(ADC_InitTypeDef* ADC_InitStruct);
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
void ADC_Cmd(FunctionalState NewState);
/* ADC Channels Configuration functions ***************************************/
void ADC_ChannelConfig(uint32_t ADC_Channels);
/* DMA Configuration functions ************************************************/
void ADC_DMA_ChannelLoadEnable(void);
void ADC_DMA_ChannelReset(void);
void ADC_DMA_Config(uint32_t ADC_DMABeg, uint32_t ADC_DMASize);
uint32_t ADC_DMA_GetNextAddress(void);
uint32_t ADC_DMA_GetCounter(void);
/* Interrupts and flags management functions **********************************/
void ADC_ITConfig(uint32_t ADC_IT, FunctionalState NewState);
FlagStatus ADC_DMA_GetFlagStatus(uint32_t ADC_DMA_FLAG);
ITStatus ADC_GetITStatus(uint32_t ADC_IT);
void ADC_ClearITPendingBit(uint32_t ADC_IT);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__STM32W108XX_ADC_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_clk.h
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/**
******************************************************************************
* @file stm32w108xx_clk.h
* @author MCD Application Team
* @version V1.0.1
* @date 30-November-2012
* @brief This file contains all the functions prototypes for the CLK firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32W108XX_CLK_H
#define __STM32W108XX_CLK_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32w108xx.h"
/** @addtogroup STM32W108xx_StdPeriph_Driver
* @{
*/
/** @addtogroup CLK
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CLK_Exported_Constants
* @{
*/
/** @defgroup CLK_HSE_configuration
* @{
*/
#define CLK_MODE0 ((uint32_t)0x00000000)
#define CLK_MODE1 ((uint32_t)0x00000001)
#define CLK_MODE2 ((uint32_t)0x00000010)
#define CLK_MODE3 ((uint32_t)0x00000011)
#define IS_CLK_MODE(MODE) (((MODE) == CLK_MODE0) || ((MODE) == CLK_MODE1) || \
((MODE) == CLK_MODE2) || ((MODE) == CLK_MODE3))
/**
* @}
*/
/** @defgroup SLPTIM_Clocks
* @{
*/
#define SLPTIM_CLK_32KH ((uint32_t)CLK_SLEEPCR_LSEEN)
#define SLPTIM_CLK_10KH ((uint32_t)CLK_SLEEPCR_LSI10KEN)
#define IS_SLPTIM_GET_CLK(CLK) (((CLK) == SLPTIM_CLK_32KH) || \
((CLK) == SLPTIM_CLK_10KH))
/**
* @}
*/
/** @defgroup Period_Measering_Mode
* @{
*/
#define MEASURE_CLKRC ((uint32_t)0x00000000)
#define MEASURE_OSCHF ((uint32_t)0x00000001)
#define MEASURE_TUNEFILT ((uint32_t)0x00000002)
#define IS_CLK_MEASURE(MEASURE) (((MEASURE) == MEASURE_CLKRC) || ((MEASURE) == MEASURE_OSCHF) || \
((MEASURE) == MEASURE_TUNEFILT))
/**
* @}
*/
#define IS_LSI1KCRINT(CALINT) (((CALINT) <= 0x0000001F))
#define IS_LSI1KCRFRAC(CALFRAC) (((CALFRAC) <= 0x000007FF))
#define IS_CLK_TUNE_VALUE(TUNE_VALUE) (((TUNE_VALUE) <= 0x0000000F))
/**
* @}
*/
/** @defgroup CLK_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup CLK_Exported_Functions
* @{
*/
/* Function used to set the CLK configuration to the default reset state *****/
void CLK_DeInit(void);
/* Internal/external clocks configuration functions *********/
void CLK_InternalCalibrateLSI(void);
void CLK_InternalCalibrateHSI(void);
void CLK_Config(uint8_t MODE);
void CLK_HSECmd(FunctionalState NewState);
void CLK_SLPTIMClockConfig(uint32_t CLK_SLPTIM, FunctionalState NewState);
void CLK_1KClockCalibration(uint32_t CALINT, uint32_t CALFRAC);
void CLK_RCTuneConfig(uint32_t TUNE_VALUE);
void CLK_MeasurePeriod(uint32_t CLK_MEASURED);
uint32_t CLK_GetMeasurePeriod(void);
uint32_t CLK_GetClocksFreq(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__STM32W108XX_CLK_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_exti.h
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/**
******************************************************************************
* @file stm32w108xx_exti.h
* @author MCD Application Team
* @version V1.0.1
* @date 30-November-2012
* @brief This file contains all the functions prototypes for the EXTI
* firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32W108xx_EXTI_H
#define __STM32W108xx_EXTI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32w108xx.h"
/** @addtogroup STM32W108xx_StdPeriph_Driver
* @{
*/
/** @addtogroup EXTI
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @brief EXTI Trigger enumeration
* @{
*/
typedef enum
{
EXTI_Trigger_Disable = 0x00,
EXTI_Trigger_Rising_Edge = 0x20,
EXTI_Trigger_Falling_Edge = 0x40,
EXTI_Trigger_Rising_Falling_Edge = 0x60,
EXTI_Trigger_High_Level = 0x80,
EXTI_Trigger_Low_Level = 0xA0
}EXTITrigger_TypeDef;
#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Disable) || \
((TRIGGER) == EXTI_Trigger_Rising_Edge) || \
((TRIGGER) == EXTI_Trigger_Falling_Edge) || \
((TRIGGER) == EXTI_Trigger_Rising_Falling_Edge) || \
((TRIGGER) == EXTI_Trigger_High_Level) || \
((TRIGGER) == EXTI_Trigger_Low_Level))
/**
* @brief EXTI Init Structure definition
*/
typedef struct
{
uint32_t EXTI_Source; /*!< Specifies the EXTI source to be configured.
This parameter can be GPIO_SourcePxy where x can be (A, B or C) and y can be (0..7). */
uint8_t EXTI_IRQn; /*!< Specifies the GPIO IRQ handler for the EXTI source.
This parameter can be EXTI_IRQn where n can be (A, B, C or D). */
EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
This parameter can be a value of @ref EXTITrigger_TypeDef */
FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI line.
This parameter can be set either to ENABLE or DISABLE */
FunctionalState EXTI_DigitalFilterCmd; /*!< Specifies the new state of the digital filter.
This parameter can be set either to ENABLE or DISABLE */
}EXTI_InitTypeDef;
/** @defgroup EXTI_Exported_Constants
* @{
*/
/** @defgroup EXTI_Pin_sources
* @{
*/
#define EXTI_SourcePA0 ((uint8_t)0x00)
#define EXTI_SourcePA1 ((uint8_t)0x01)
#define EXTI_SourcePA2 ((uint8_t)0x02)
#define EXTI_SourcePA3 ((uint8_t)0x03)
#define EXTI_SourcePA4 ((uint8_t)0x04)
#define EXTI_SourcePA5 ((uint8_t)0x05)
#define EXTI_SourcePA6 ((uint8_t)0x06)
#define EXTI_SourcePA7 ((uint8_t)0x07)
#define EXTI_SourcePB0 ((uint8_t)0x08)
#define EXTI_SourcePB1 ((uint8_t)0x09)
#define EXTI_SourcePB2 ((uint8_t)0x0A)
#define EXTI_SourcePB3 ((uint8_t)0x0B)
#define EXTI_SourcePB4 ((uint8_t)0x0C)
#define EXTI_SourcePB5 ((uint8_t)0x0D)
#define EXTI_SourcePB6 ((uint8_t)0x0E)
#define EXTI_SourcePB7 ((uint8_t)0x0F)
#define EXTI_SourcePC0 ((uint8_t)0x10)
#define EXTI_SourcePC1 ((uint8_t)0x11)
#define EXTI_SourcePC2 ((uint8_t)0x12)
#define EXTI_SourcePC3 ((uint8_t)0x13)
#define EXTI_SourcePC4 ((uint8_t)0x14)
#define EXTI_SourcePC5 ((uint8_t)0x15)
#define EXTI_SourcePC6 ((uint8_t)0x16)
#define EXTI_SourcePC7 ((uint8_t)0x17)
#define IS_EXTI_SOURCE(EXTI_SOURCE) (((EXTI_SOURCE) == EXTI_SourcePA0) || \
((EXTI_SOURCE) == EXTI_SourcePA1) || \
((EXTI_SOURCE) == EXTI_SourcePA2) || \
((EXTI_SOURCE) == EXTI_SourcePA3) || \
((EXTI_SOURCE) == EXTI_SourcePA4) || \
((EXTI_SOURCE) == EXTI_SourcePA5) || \
((EXTI_SOURCE) == EXTI_SourcePA6) || \
((EXTI_SOURCE) == EXTI_SourcePA7) || \
((EXTI_SOURCE) == EXTI_SourcePB0) || \
((EXTI_SOURCE) == EXTI_SourcePB1) || \
((EXTI_SOURCE) == EXTI_SourcePB2) || \
((EXTI_SOURCE) == EXTI_SourcePB3) || \
((EXTI_SOURCE) == EXTI_SourcePB4) || \
((EXTI_SOURCE) == EXTI_SourcePB5) || \
((EXTI_SOURCE) == EXTI_SourcePB6) || \
((EXTI_SOURCE) == EXTI_SourcePB7) || \
((EXTI_SOURCE) == EXTI_SourcePC0) || \
((EXTI_SOURCE) == EXTI_SourcePC1) || \
((EXTI_SOURCE) == EXTI_SourcePC2) || \
((EXTI_SOURCE) == EXTI_SourcePC3) || \
((EXTI_SOURCE) == EXTI_SourcePC4) || \
((EXTI_SOURCE) == EXTI_SourcePC5) || \
((EXTI_SOURCE) == EXTI_SourcePC6) || \
((EXTI_SOURCE) == EXTI_SourcePC7))
/**
* @}
*/
/** @defgroup EXTI_IRQ_Sources
* @{
*/
#define EXTI_IRQA ((uint32_t)0x00000000)
#define EXTI_IRQB ((uint32_t)0x00000010)
#define EXTI_IRQC ((uint32_t)0x00000020)
#define EXTI_IRQD ((uint32_t)0x00000031)
#define IS_EXTI_IRQ(EXTI_IRQ) (((EXTI_IRQ) == EXTI_IRQA) || \
((EXTI_IRQ) == EXTI_IRQB) || \
((EXTI_IRQ) == EXTI_IRQC) || \
((EXTI_IRQ) == EXTI_IRQD))
/**
* @}
*/
/**
* @}
*/
/** @defgroup EXTI_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup EXTI_Exported_Functions
* @{
*/
/* EXTI Initialization and Configuration **************************************/
void EXTI_DeInit(void);
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
/* Interrupts and flags management functions **********************************/
ITStatus EXTI_GetITStatus(uint32_t EXTI_IRQn);
void EXTI_ClearITPendingBit(uint32_t EXTI_IRQn);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__STM32W108xx_EXTI_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

327
libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_flash.h
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@ -1,327 +0,0 @@
/**
******************************************************************************
* @file stm32w108xx_flash.h
* @author MCD Application Team
* @version V1.0.1
* @date 30-November-2012
* @brief This file contains all the functions prototypes for the FLASH
* firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32W108xx_FLASH_H
#define __STM32W108xx_FLASH_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32w108xx.h"
/** @addtogroup STM32W108xx_StdPeriph_Driver
* @{
*/
/** @addtogroup FLASH
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief FLASH Status
*/
typedef enum
{
FLASH_BUSY = 1,
FLASH_ERROR_PG,
FLASH_ERROR_WRP,
FLASH_COMPLETE,
FLASH_TIMEOUT
}FLASH_Status;
/** @defgroup FLASH_Exported_Constants
* @{
*/
/** @defgroup Flash_Latency
* @{
*/
#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */
#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */
#define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
((LATENCY) == FLASH_Latency_1) || \
((LATENCY) == FLASH_Latency_2))
/**
* @}
*/
/** @defgroup Half_Cycle_Enable_Disable
* @{
*/
#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */
#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */
#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \
((STATE) == FLASH_HalfCycleAccess_Disable))
/**
* @}
*/
/** @defgroup Prefetch_Buffer_Enable_Disable
* @{
*/
#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */
#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */
#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \
((STATE) == FLASH_PrefetchBuffer_Disable))
/**
* @}
*/
/** @defgroup Option_Bytes_Write_Protection
* @{
*/
/* Values to be used with STM32W Low and Medium density devices */
#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32W Low and Medium density devices: Write protection of page 0 to 3 */
#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32W Low and Medium density devices: Write protection of page 4 to 7 */
#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32W Low and Medium density devices: Write protection of page 8 to 11 */
#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32W Low and Medium density devices: Write protection of page 12 to 15 */
#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32W Low and Medium density devices: Write protection of page 16 to 19 */
#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32W Low and Medium density devices: Write protection of page 20 to 23 */
#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32W Low and Medium density devices: Write protection of page 24 to 27 */
#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32W Low and Medium density devices: Write protection of page 28 to 31 */
#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32W Medium-density devices: Write protection of page 32 to 35 */
#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32W Medium-density devices: Write protection of page 36 to 39 */
#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32W Medium-density devices: Write protection of page 40 to 43 */
#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32W Medium-density devices: Write protection of page 44 to 47 */
#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32W Medium-density devices: Write protection of page 48 to 51 */
#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32W Medium-density devices: Write protection of page 52 to 55 */
#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32W Medium-density devices: Write protection of page 56 to 59 */
#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32W Medium-density devices: Write protection of page 60 to 63 */
/* Values to be used with STM32W Medium-density devices */
#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32W Medium-density devices: Write protection of page 64 to 67 */
#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32W Medium-density devices: Write protection of page 68 to 71 */
#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32W Medium-density devices: Write protection of page 72 to 75 */
#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32W Medium-density devices: Write protection of page 76 to 79 */
#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32W Medium-density devices: Write protection of page 80 to 83 */
#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32W Medium-density devices: Write protection of page 84 to 87 */
#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32W Medium-density devices: Write protection of page 88 to 91 */
#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32W Medium-density devices: Write protection of page 92 to 95 */
#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32W Medium-density devices: Write protection of page 96 to 99 */
#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32W Medium-density devices: Write protection of page 100 to 103 */
#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32W Medium-density devices: Write protection of page 104 to 107 */
#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32W Medium-density devices: Write protection of page 108 to 111 */
#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32W Medium-density devices: Write protection of page 112 to 115 */
#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32W Medium-density devices: Write protection of page 115 to 119 */
#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32W Medium-density devices: Write protection of page 120 to 123 */
#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32W Medium-density devices: Write protection of page 124 to 127 */
/* Values to be used with STM32W High-density and Connectivity line devices */
#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32W High-density and Connectivity line devices:
Write protection of page 0 to 1 */
#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32W High-density and Connectivity line devices:
Write protection of page 2 to 3 */
#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32W High-density and Connectivity line devices:
Write protection of page 4 to 5 */
#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32W High-density and Connectivity line devices:
Write protection of page 6 to 7 */
#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32W High-density and Connectivity line devices:
Write protection of page 8 to 9 */
#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32W High-density and Connectivity line devices:
Write protection of page 10 to 11 */
#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32W High-density and Connectivity line devices:
Write protection of page 12 to 13 */
#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32W High-density and Connectivity line devices:
Write protection of page 14 to 15 */
#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32W High-density and Connectivity line devices:
Write protection of page 16 to 17 */
#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32W High-density and Connectivity line devices:
Write protection of page 18 to 19 */
#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32W High-density and Connectivity line devices:
Write protection of page 20 to 21 */
#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32W High-density and Connectivity line devices:
Write protection of page 22 to 23 */
#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32W High-density and Connectivity line devices:
Write protection of page 24 to 25 */
#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32W High-density and Connectivity line devices:
Write protection of page 26 to 27 */
#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32W High-density and Connectivity line devices:
Write protection of page 28 to 29 */
#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32W High-density and Connectivity line devices:
Write protection of page 30 to 31 */
#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32W High-density and Connectivity line devices:
Write protection of page 32 to 33 */
#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32W High-density and Connectivity line devices:
Write protection of page 34 to 35 */
#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32W High-density and Connectivity line devices:
Write protection of page 36 to 37 */
#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32W High-density and Connectivity line devices:
Write protection of page 38 to 39 */
#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32W High-density and Connectivity line devices:
Write protection of page 40 to 41 */
#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32W High-density and Connectivity line devices:
Write protection of page 42 to 43 */
#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32W High-density and Connectivity line devices:
Write protection of page 44 to 45 */
#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32W High-density and Connectivity line devices:
Write protection of page 46 to 47 */
#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32W High-density and Connectivity line devices:
Write protection of page 48 to 49 */
#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32W High-density and Connectivity line devices:
Write protection of page 50 to 51 */
#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32W High-density and Connectivity line devices:
Write protection of page 52 to 53 */
#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32W High-density and Connectivity line devices:
Write protection of page 54 to 55 */
#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32W High-density and Connectivity line devices:
Write protection of page 56 to 57 */
#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32W High-density and Connectivity line devices:
Write protection of page 58 to 59 */
#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32W High-density and Connectivity line devices:
Write protection of page 60 to 61 */
#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32W High-density devices:
Write protection of page 62 to 127 */
#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000))
#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x08040000))
/**
* @}
*/
/** @defgroup FLASH_Interrupts
* @{
*/
#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */
#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */
#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
/**
* @}
*/
/** @defgroup FLASH_Flags
* @{
*/
#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */
#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */
#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */
#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
((FLAG) == FLASH_FLAG_OPTERR))
/**
* @}
*/
/** @defgroup FPEC_Flags
* @{
*/
#define FPEC_FLAG_ACK ((uint32_t)0x00000001) /*!< FPEC_CLK running flag */
#define FPEC_FLAG_BSY ((uint32_t)0x00000002) /*!< FPEC Busy flag */
#define IS_FPEC_GET_FLAG(FLAG) (((FLAG) == FPEC_FLAG_ACK) || \
((FLAG) == FPEC_FLAG_BSY))
/**
* @}
*/
/**
* @}
*/
/** @defgroup FLASH_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup FLASH_Exported_Functions
* @{
*/
/*------------ Functions used for all STM32W108xx devices -----*/
/* FLASH Interface configuration functions ************************************/
void FLASH_SetLatency(uint32_t FLASH_Latency);
FlagStatus FLASH_GetPrefetchBufferStatus(void);
void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer);
/* FLASH Memory Programming functions *****************************************/
void FPEC_ClockCmd(FunctionalState NewState);
void FLASH_Unlock(void);
void FLASH_Lock(void);
void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);
FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
FLASH_Status FLASH_EraseAllPages(void);
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
/* Option Bytes Programming functions *****************************************/
FLASH_Status FLASH_EraseOptionBytes(void);
FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);
FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
uint32_t FLASH_GetWriteProtectionOptionByte(void);
FlagStatus FLASH_GetReadOutProtectionStatus(void);
/* Interrupts and flags management functions **********************************/
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
FLASH_Status FLASH_GetStatus(void);
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32W108xx_FLASH_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

196
libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_gpio.h
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@ -1,196 +0,0 @@
/**
******************************************************************************
* @file stm32w108xx_gpio.h
* @author MCD Application Team
* @version V1.0.1
* @date 30-November-2012
* @brief This file contains all the functions prototypes for the GPIO
* firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32W108xx_GPIO_H
#define __STM32W108xx_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32w108xx.h"
/** @addtogroup STM32W108xx_StdPeriph_Driver
* @{
*/
/** @addtogroup GPIO
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @brief GPIO Mode enumeration
* @{
*/
typedef enum
{
GPIO_Mode_AN = 0x00, /*!< GPIO Analog Mode */
GPIO_Mode_OUT_PP = 0x01, /*!< GPIO Output Mode PP */
GPIO_Mode_IN = 0x04, /*!< GPIO Input Mode NOPULL */
GPIO_Mode_OUT_OD = 0x05, /*!< GPIO Output Mode OD */
GPIO_Mode_IN_PUD = 0x08, /*!< GPIO Input Mode PuPd */
GPIO_Mode_AF_PP = 0x09, /*!< GPIO Alternate function Mode PP */
GPIO_Mode_AF_PP_SPI = 0x0B, /*!< GPIO Alternate function Mode SPI SCLK PP */
GPIO_Mode_AF_OD = 0x0D /*!< GPIO Alternate function Mode OD */
}GPIOMode_TypeDef;
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AN) || ((MODE) == GPIO_Mode_OUT_PP) || \
((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT_OD) || \
((MODE) == GPIO_Mode_IN_PUD)|| ((MODE) == GPIO_Mode_AF_PP) || \
((MODE) == GPIO_Mode_AF_PP_SPI) ||((MODE) == GPIO_Mode_AF_OD))
/**
* @brief GPIO Init structure definition
*/
typedef struct
{
uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_pins_define */
GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIOMode_TypeDef */
}GPIO_InitTypeDef;
/** @defgroup GPIO_Exported_Constants
* @{
*/
#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
((PERIPH) == GPIOB) || \
((PERIPH) == GPIOC))
/** @defgroup Bit_SET_and_Bit_RESET_enumeration
* @{
*/
typedef enum
{ Bit_RESET = 0,
Bit_SET
}BitAction;
#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
/**
* @}
*/
/** @defgroup GPIO_pins_define
* @{
*/
#define GPIO_Pin_0 ((uint32_t)0x00000001) /*!< Pin 0 selected */
#define GPIO_Pin_1 ((uint32_t)0x00000002) /*!< Pin 1 selected */
#define GPIO_Pin_2 ((uint32_t)0x00000004) /*!< Pin 2 selected */
#define GPIO_Pin_3 ((uint32_t)0x00000008) /*!< Pin 3 selected */
#define GPIO_Pin_4 ((uint32_t)0x00000010) /*!< Pin 4 selected */
#define GPIO_Pin_5 ((uint32_t)0x00000020) /*!< Pin 5 selected */
#define GPIO_Pin_6 ((uint32_t)0x00000040) /*!< Pin 6 selected */
#define GPIO_Pin_7 ((uint32_t)0x00000080) /*!< Pin 7 selected */
#define GPIO_Pin_All ((uint32_t)0x000000FF) /*!< All pins selected */
#define IS_GPIO_PIN(PIN) ((PIN) != (uint32_t)0x00000000)
#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
((PIN) == GPIO_Pin_1) || \
((PIN) == GPIO_Pin_2) || \
((PIN) == GPIO_Pin_3) || \
((PIN) == GPIO_Pin_4) || \
((PIN) == GPIO_Pin_5) || \
((PIN) == GPIO_Pin_6) || \
((PIN) == GPIO_Pin_7))
/**
* @}
*/
#define IS_GPIO_GET_DBGFLAG(DBGFLAG) (((DBGFLAG) == GPIO_DBGSR_SWEN) || \
((DBGFLAG) == GPIO_DBGSR_FORCEDBG) || \
((DBGFLAG) == GPIO_DBGSR_BOOTMODE))
/**
* @}
*/
/** @defgroup CLK_PC_Trace_Select
* @{
*/
#define GPIO_BBDEBUG ((uint32_t)0x00000000)
#define GPIO_PCTRACE ((uint32_t)0x00000001)
#define IS_GPIO_PCTRACE(PCTRACE) (((PCTRACE) == GPIO_BBDEBUG) || \
((PCTRACE) == GPIO_PCTRACE))
/**
* @}
*/
/** @defgroup GPIO_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup GPIO_Exported_Functions
* @{
*/
/* Function used to set the GPIO configuration to the default reset state ****/
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
/* Initialization and Configuration functions *********************************/
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
/* GPIO Read and Write functions **********************************************/
uint32_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin);
uint32_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
uint32_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin);
uint32_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin);
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin);
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin, BitAction BitVal);
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
/* Debug functions ***********************************************************/
void GPIO_PCTraceConfig(uint32_t PCTRACE_SEL);
void GPIO_DebugInterfaceCmd(FunctionalState NewState);
void GPIO_ExternalOverrideCmd(FunctionalState NewState);
FlagStatus GPIO_GetDebugFlagStatus(uint16_t GPIO_DBGFLAG);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__STM32W108xx_GPIO_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_misc.h
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/**
******************************************************************************
* @file stm32w108xx_misc.h
* @author MCD Application Team
* @version V1.0.1
* @date 30-November-2012
* @brief This file contains all the functions prototypes for the miscellaneous
* firmware library functions (add-on to CMSIS functions).
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MISC_H
#define __MISC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32w108xx.h"
/** @addtogroup STM32W108xx_StdPeriph_Driver
* @{
*/
/** @addtogroup MISC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief NVIC Init Structure definition
*/
typedef struct
{
uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
This parameter can be a value of @ref IRQn_Type
(For the complete STM32 Devices IRQ Channels list, please
refer to stm32w108.h file) */
uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
specified in NVIC_IRQChannel. This parameter can be a value
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
in NVIC_IRQChannel. This parameter can be a value
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
will be enabled or disabled.
This parameter can be set either to ENABLE or DISABLE */
} NVIC_InitTypeDef;
/** @defgroup NVIC_Priority_Table
* @{
*/
/**
*
@verbatim
The table below gives the allowed values of the pre-emption priority and subpriority according
to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
============================================================================================================================
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
============================================================================================================================
NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
| | | 4 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
| | | 3 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
| | | 2 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
| | | 1 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
| | | 0 bits for subpriority
============================================================================================================================
@endverbatim
*/
/**
* @}
*/
/** @defgroup MISC_Exported_Constants
* @{
*/
/** @defgroup Vector_Table_Base
* @{
*/
#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
((VECTTAB) == NVIC_VectTab_FLASH))
/**
* @}
*/
/** @defgroup System_Low_Power
* @{
*/
#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
((LP) == NVIC_LP_SLEEPDEEP) || \
((LP) == NVIC_LP_SLEEPONEXIT))
/**
* @}
*/
/** @defgroup Preemption_Priority_Group
* @{
*/
#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
0 bits for subpriority */
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
((GROUP) == NVIC_PriorityGroup_1) || \
((GROUP) == NVIC_PriorityGroup_2) || \
((GROUP) == NVIC_PriorityGroup_3) || \
((GROUP) == NVIC_PriorityGroup_4))
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0005FFFF)
/**
* @}
*/
/**
* @}
*/
/** @defgroup MISC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup MISC_Exported_Functions
* @{
*/
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __MISC_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

213
libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_pwr.h
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@ -1,213 +0,0 @@
/**
******************************************************************************
* @file stm32w108xx_pwr.h
* @author MCD Application Team
* @version V1.0.1
* @date 30-November-2012
* @brief This file contains all the functions prototypes for the power
* firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32W108XX_PWR_H
#define __STM32W108XX_PWR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32w108xx.h"
/** @addtogroup STM32W108xx_StdPeriph_Driver
* @{
*/
/** @addtogroup POWER_MANAGEMENT
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief VREG Init structure definition
*/
typedef struct
{
uint32_t PWR_VREFCmd; /*!< Specifies the new state of the selected VREF.
This parameter can be set either to ENABLE or DISABLE */
uint32_t PWR_1V8Cmd; /*!< Specifies the new state of the selected 1V8.
This parameter can be set either to ENABLE or DISABLE */
uint32_t PWR_1V8TRIM; /*!< Specifies wether the 1V8 regulator trim value.*/
uint32_t PWR_1V2Cmd; /*!< Specifies the new state of the selected 1V2.
This parameter can be set either to ENABLE or DISABLE */
uint32_t PWR_1V2TRIM; /*!< Specifies wether the 1V2 regulator trim value.*/
}PWR_VREG_InitTypeDef;
/** @defgroup PWR_Exported_Constants
* @{
*/
/** @defgroup LowPower_VoltageCommand_definition
* @{
*/
#define POWER_ENABLE ((uint32_t)0x00)
#define POWER_DISABLE ((uint32_t)!POWER_ENABLE)
#define IS_POWER_FUNCTIONAL_STATE(STATE) (((STATE) == POWER_ENABLE) || ((STATE) == POWER_DISABLE))
/**
* @}
*/
/** @defgroup LowPower_WakeUpFilter_definition
* @{
*/
#define PWR_WAKEFILTER_IRQD ((uint32_t)PWR_WAKEFILTR_IRQD)
#define PWR_WAKEFILTER_SC2 ((uint32_t)PWR_WAKEFILTR_SC2)
#define PWR_WAKEFILTER_SC1 ((uint32_t)PWR_WAKEFILTR_SC1)
#define PWR_WAKEFILTER_GPIO ((uint32_t)PWR_WAKEFILTR_GPIO)
#define IS_PWR_WAKEUPFILTERSOURCE(WAKEUP) (((WAKEUP) == PWR_WAKEFILTER_GPIO) || \
((WAKEUP) == PWR_WAKEFILTER_SC1) || \
((WAKEUP) == PWR_WAKEFILTER_SC2) || \
((WAKEUP) == PWR_WAKEFILTER_IRQD ))
/**
* @}
*/
/** @defgroup LowPower_WakeUpMethod_definition
* @{
*/
#define PWR_WAKEUP_CSYSPWRRUPREQ ((uint32_t)PWR_WAKECR1_CSYSPWRRUPREQ)
#define PWR_WAKEUP_CPWRRUPREQ ((uint32_t)PWR_WAKECR1_CPWRRUPREQ)
#define PWR_WAKEUP_CORE ((uint32_t)PWR_WAKECR1_CORE)
#define PWR_WAKEUP_WRAP ((uint32_t)PWR_WAKECR1_WRAP)
#define PWR_WAKEUP_COMPB ((uint32_t)PWR_WAKECR1_COMPB)
#define PWR_WAKEUP_COMPA ((uint32_t)PWR_WAKECR1_COMPA)
#define PWR_WAKEUP_IRQD ((uint32_t)PWR_WAKECR1_IRQD)
#define PWR_WAKEUP_SC2 ((uint32_t)PWR_WAKECR1_SC2)
#define PWR_WAKEUP_SC1 ((uint32_t)PWR_WAKECR1_SC1)
#define PWR_WAKEUP_MON ((uint32_t)PWR_WAKECR1_MONEN)
#define IS_PWR_WAKEUPSOURCE(WAKEUP) (((WAKEUP) == PWR_WAKEUP_CSYSPWRRUPREQ) || \
((WAKEUP) == PWR_WAKEUP_CPWRRUPREQ) || \
((WAKEUP) == PWR_WAKEUP_CORE) || \
((WAKEUP) == PWR_WAKEUP_WRAP) || \
((WAKEUP) == PWR_WAKEUP_COMPB) || \
((WAKEUP) == PWR_WAKEUP_COMPA) || \
((WAKEUP) == PWR_WAKEUP_IRQD) || \
((WAKEUP) == PWR_WAKEUP_SC2) || \
((WAKEUP) == PWR_WAKEUP_SC1) || \
((WAKEUP) == PWR_WAKEUP_MON))
/**
* @}
*/
/** @defgroup LowPower_flags_definition
* @{
*/
#define PWR_FLAG_CSYSPWRRUPREQ ((uint32_t)PWR_WAKESR_CSYSPWRRUPREQ)
#define PWR_FLAG_CPWRRUPREQ ((uint32_t)PWR_WAKESR_CPWRRUPREQ)
#define PWR_FLAG_CORE ((uint32_t)PWR_WAKESR_CORE)
#define PWR_FLAG_WRAP ((uint32_t)PWR_WAKESR_WRAP)
#define PWR_FLAG_COMPB ((uint32_t)PWR_WAKESR_COMPB)
#define PWR_FLAG_COMPA ((uint32_t)PWR_WAKESR_COMPA)
#define PWR_FLAG_IRQD ((uint32_t)PWR_WAKESR_IRQD)
#define PWR_FLAG_SC2 ((uint32_t)PWR_WAKESR_SC2)
#define PWR_FLAG_SC1 ((uint32_t)PWR_WAKESR_SC1)
#define PWR_FLAG_MON ((uint32_t)PWR_WAKESR_MON)
#define PWR_FLAG_CPWRUPREQ ((uint32_t)0x10000001)
#define PWR_FLAG_CSYSPWRUPREQ ((uint32_t)0x20000001)
#define PWR_FLAG_CSYSPWRUPACK ((uint32_t)0x30000001)
#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_CSYSPWRRUPREQ) || ((FLAG) == PWR_FLAG_CPWRRUPREQ) || \
((FLAG) == PWR_FLAG_CORE) || ((FLAG) == PWR_FLAG_WRAP) || \
((FLAG) == PWR_FLAG_COMPB) || ((FLAG) == PWR_FLAG_COMPA) || \
((FLAG) == PWR_FLAG_IRQD) || ((FLAG) == PWR_FLAG_SC2) || \
((FLAG) == PWR_FLAG_SC1) || ((FLAG) == PWR_FLAG_MON) || \
((FLAG) == PWR_FLAG_CPWRUPREQ) || ((FLAG) == PWR_FLAG_CSYSPWRUPREQ) || \
((FLAG) == PWR_FLAG_CSYSPWRUPACK))
#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_CSYSPWRRUPREQ) || ((FLAG) == PWR_FLAG_CPWRRUPREQ) || \
((FLAG) == PWR_FLAG_CORE) || ((FLAG) == PWR_FLAG_WRAP) || \
((FLAG) == PWR_FLAG_COMPB) || ((FLAG) == PWR_FLAG_COMPA) || \
((FLAG) == PWR_FLAG_IRQD) || ((FLAG) == PWR_FLAG_SC2) || \
((FLAG) == PWR_FLAG_SC1) || ((FLAG) == PWR_FLAG_MON))
/**
* @}
*/
#define IS_TRIM_VALUE(TRIM) ((TRIM) < 8)
/**
* @}
*/
/** @defgroup PWR_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup PWR_Exported_Functions
* @{
*/
void PWR_DeInit(void);
void PWR_VREGStructInit(PWR_VREG_InitTypeDef* VREG_InitStruct);
void PWR_VREGInit(PWR_VREG_InitTypeDef* VREG_InitStruct);
void PWR_GPIOWakeUpPinCmd(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin, FunctionalState NewState);
void PWR_WakeUpFilterConfig(uint32_t PWR_WakeUpSource, FunctionalState NewState);
void PWR_WakeUpSourceConfig(uint32_t PWR_WakeUpSource, FunctionalState NewState);
void PWR_DeepSleepMode0Cmd(FunctionalState NewState);
void PWR_FreezestateLVoutput(FunctionalState NewState);
void PWR_CoreWake(void);
void PWR_InhibitCSYSPWRUPACK(void);
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
void PWR_ClearFlag(uint32_t PWR_FLAG);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__STM32W108XX_PWR_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

110
libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_rst.h
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/**
******************************************************************************
* @file stm32w108xx_rst.h
* @author MCD Application Team
* @version V1.0.1
* @date 30-November-2012
* @brief This file contains all the functions prototypes for the RST firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32W108XX_RST_H
#define __STM32W108XX_RST_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32w108xx.h"
/** @addtogroup STM32W108xx_StdPeriph_Driver
* @{
*/
/** @addtogroup RST
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup RST_Exported_Constants
* @{
*/
/** @defgroup RESET_Event
* @{
*/
#define RST_FLAG_PWRHV ((uint32_t)RST_SR_PWRHV)
#define RST_FLAG_PWRLV ((uint32_t)RST_SR_PWRLV)
#define RST_FLAG_PIN ((uint32_t)RST_SR_PIN)
#define RST_FLAG_WDG ((uint32_t)RST_SR_WDG)
#define RST_FLAG_SWRST ((uint32_t)RST_SR_SWRST)
#define RST_FLAG_WKUP ((uint32_t)RST_SR_WKUP)
#define RST_FLAG_OBFAIL ((uint32_t)RST_SR_OBFAIL)
#define RST_FLAG_LKUP ((uint32_t)RST_SR_LKUP)
#define IS_RST_FLAG(FLAG) (((FLAG) == RST_FLAG_PWRHV) || ((FLAG) == RST_FLAG_PWRLV) || \
((FLAG) == RST_FLAG_PIN) || ((FLAG) == RST_FLAG_WDG) || \
((FLAG) == RST_FLAG_SWRST) || ((FLAG) == RST_FLAG_WKUP) || \
((FLAG) == RST_FLAG_OBFAIL) || ((FLAG) == RST_FLAG_LKUP))
/**
* @}
*/
/**
* @}
*/
/** @defgroup RST_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup RST_Exported_Functions
* @{
*/
FlagStatus RST_GetFlagStatus(uint32_t RST_FLAG);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__STM32W108XX_RST_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

635
libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_sc.h
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@ -1,635 +0,0 @@
/**
******************************************************************************
* @file stm32w108xx_sc.h
* @author MCD Application Team
* @version V1.0.1
* @date 30-November-2012
* @brief This file contains all the functions prototypes for the serial controller
* firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32W108XX_SC_H
#define __STM32W108XX_SC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32w108xx.h"
/** @addtogroup STM32W108xx_StdPeriph_Driver
* @{
*/
/** @addtogroup SERIAL_CONTROLLER
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief SPI Init structure definition
*/
typedef struct
{
uint16_t SPI_Mode; /*!< Specifies the SPI mode (Master/Slave).
This parameter can be a value of @ref SPI_mode */
uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
This parameter can be a value of @ref SPI_Clock_Polarity */
uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
This parameter can be a value of @ref SPI_Clock_Phase */
uint32_t SPI_ClockRate; /*!< This member configures the SPI communication clock rate.
The clock rate is computed using the following formula:
- clock rate = 12MHz/((LIN+1)*(2^EXP)*/
uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
}SPI_InitTypeDef;
/**
* @brief UART Init Structure definition
*/
typedef struct
{
uint32_t UART_BaudRate; /*!< This member configures the UART communication baud rate.
The baud rate is computed using the following formula:
- Baudrate = 24MHz/(2*N+F)*/
uint32_t UART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref UART_Word_Length */
uint32_t UART_StopBits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref UART_Stop_Bits */
uint32_t UART_Parity; /*!< Specifies the parity mode.
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits)
This parameter can be a value of @ref UART_Parity */
uint32_t UART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled or disabled.
This parameter can be a value of @ref UART_Hardware_Flow_Control */
}UART_InitTypeDef;
/**
* @brief I2C Init structure definition
*/
typedef struct
{
uint32_t I2C_ClockRate; /*!< This member configures the I2C communication clock rate.
The clock rate is computed using the following formula:
- clock rate = 12MHz/((LIN+1)*(2^EXP)
This parameter must be set to a value lower than 400kHz */
}I2C_InitTypeDef;
/**
* @brief DMA Init structure definition
*/
typedef struct
{
uint32_t DMA_BeginAddrA; /*!< Specifies the peripheral begin address A for the selected
DMA_channel */
uint32_t DMA_EndAddrA; /*!< Specifies the peripheral end address A for the selected
DMA_channel */
uint32_t DMA_BeginAddrB; /*!< Specifies the peripheral begin address B for the selected
DMA_channel */
uint32_t DMA_EndAddrB; /*!< Specifies the peripheral end address B for the selected
DMA_channel */
}SC_DMA_InitTypeDef;
/** @defgroup SC_Exported_Constants
* @{
*/
#define IS_UART_PERIPH(PERIPH) (((PERIPH) == SC1_UART))
#define IS_SPI_PERIPH(PERIPH) (((PERIPH) == SC1_SPI) || \
((PERIPH) == SC2_SPI))
#define IS_I2C_PERIPH(PERIPH) (((PERIPH) == SC1_I2C) || \
((PERIPH) == SC2_I2C))
#define IS_DMA_PERIPH(PERIPH) (((PERIPH) == SC1_DMA) || \
((PERIPH) == SC2_DMA))
#define IS_I2C_SPI_DMA_IT_PERIPH(PERIPH) (((PERIPH) == SC1_IT) || \
((PERIPH) == SC2_IT))
#define IS_UART_IT_PERIPH(PERIPH) (((PERIPH) == SC1_IT))
/** @defgroup SC_mode
* @{
*/
#define SC_Mode_Disable ((uint32_t)0x00000000)
#define SC_Mode_UART ((uint32_t)0x00000001)
#define SC_Mode_SPI ((uint32_t)0x00000002)
#define SC_Mode_I2C ((uint32_t)0x00000003)
#define IS_SC_MODE(MODE) (((MODE) == SC_Mode_Disable) || ((MODE) == SC_Mode_SPI) || \
((MODE) == SC_Mode_I2C) || ((MODE) == SC_Mode_UART))
/**
* @}
*/
/** @defgroup Trigger_Event
* @{
*/
#define SC_TriggerEvent_Edge ((uint32_t)0x00000000)
#define SC_TriggerEvent_Level ((uint32_t)0x00000001)
#define IS_SC_TRIGGEREVENT(EVENT) (((EVENT) == SC_TriggerEvent_Edge) || ((EVENT) == SC_TriggerEvent_Level))
/**
* @}
*/
/** @defgroup SC_SPI_Exported_Constants
* @{
*/
/** @defgroup SPI_mode
* @{
*/
#define SPI_Mode_Slave ((uint32_t)0x00000000)
#define SPI_Mode_Master ((uint32_t)SC_SPICR_MSTR)
#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
((MODE) == SPI_Mode_Slave))
/**
* @}
*/
/** @defgroup SPI_Clock_Polarity
* @{
*/
#define SPI_CPOL_Low ((uint32_t)0x00000000)
#define SPI_CPOL_High ((uint32_t)SC_SPICR_CPOL)
#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
((CPOL) == SPI_CPOL_High))
/**
* @}
*/
/** @defgroup SPI_Clock_Phase
* @{
*/
#define SPI_CPHA_1Edge ((uint32_t)0x00000000)
#define SPI_CPHA_2Edge ((uint32_t)SC_SPICR_CPHA)
#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
((CPHA) == SPI_CPHA_2Edge))
/**
* @}
*/
/** @defgroup SPI_MSB_LSB_transmission
* @{
*/
#define SPI_FirstBit_MSB ((uint32_t)0x00000000)
#define SPI_FirstBit_LSB ((uint32_t)SC_SPICR_LSBFIRST)
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
((BIT) == SPI_FirstBit_LSB))
/**
* @}
*/
/** @defgroup SPI_Receiver_driven_Mode
* @{
*/
#define SPI_ReceiverMode_TxDataReady ((uint32_t)0x00000000)
#define SPI_ReceiverMode_RxFIFOFree ((uint32_t)SC_SPICR_RXMODE)
#define IS_SPI_RECEIVER_DRIVEN_MODE(MODE) (((MODE) == SPI_ReceiverMode_TxDataReady) || \
((MODE) == SPI_ReceiverMode_RxFIFOFree))
/**
* @}
*/
/** @defgroup SPI_flags_definition
* @{
*/
#define SPI_FLAG_OVR ((uint32_t)SC_SPISR_OVR)
#define SPI_FLAG_TXE ((uint32_t)SC_SPISR_TXE)
#define SPI_FLAG_RXNE ((uint32_t)SC_SPISR_RXNE)
#define SPI_FLAG_IDLE ((uint32_t)SC_SPISR_IDLE)
#define IS_SPI_GET_FLAG(FLAG) (((FLAG) == SPI_FLAG_IDLE) || ((FLAG) == SPI_FLAG_RXNE) || \
((FLAG) == SPI_FLAG_TXE) || ((FLAG) == SPI_FLAG_OVR))
/**
* @}
*/
/** @defgroup SPI_interrupts_definition
* @{
*/
#define SPI_IT_UND ((uint32_t)SC_ISR_UND)
#define SPI_IT_OVR ((uint32_t)SC_ISR_OVR)
#define SPI_IT_IDLE ((uint32_t)SC_ISR_IDLE)
#define SPI_IT_TXE ((uint32_t)SC_ISR_TXE)
#define SPI_IT_RXNE ((uint32_t)SC_ISR_RXNE)
#define IS_SPI_IT(IT) (((IT) == SPI_IT_UND) || ((IT) == SPI_IT_OVR) || \
((IT) == SPI_IT_IDLE) || ((IT) == SPI_IT_TXE) || \
((IT) == SPI_IT_RXNE))
#define IS_SPI_TRIGGEREVENT_IT(IT) (((IT) == SPI_IT_IDLE) || ((IT) == SPI_IT_TXE) || \
((IT) == SPI_IT_RXNE))
/**
* @}
*/
#define IS_SPI_CLOCK_RATE(RATE) (((RATE) > 0) && ((RATE) <= 6000000))
/**
* @}
*/
/** @defgroup SC_UART_Exported_Constants
* @{
*/
/** @defgroup UART_Word_Length
* @{
*/
#define UART_WordLength_7b ((uint32_t)0x00000000)
#define UART_WordLength_8b ((uint32_t)SC_UARTCR_M)
#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WordLength_7b) || \
((LENGTH) == UART_WordLength_8b))
/**
* @}
*/
/** @defgroup UART_Stop_Bits
* @{
*/
#define UART_StopBits_1 ((uint32_t)0x00000000)
#define UART_StopBits_2 ((uint32_t)SC_UARTCR_STOP)
#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_StopBits_1) || \
((STOPBITS) == UART_StopBits_2))
/**
* @}
*/
/** @defgroup UART_Parity
* @{
*/
#define UART_Parity_No ((uint32_t)0x00000000)
#define UART_Parity_Even ((uint32_t)SC_UARTCR_PCE)
#define UART_Parity_Odd ((uint32_t)SC_UARTCR_PCE | SC_UARTCR_PS)
#define IS_UART_PARITY(PARITY) (((PARITY) == UART_Parity_No) || \
((PARITY) == UART_Parity_Even) || \
((PARITY) == UART_Parity_Odd))
/**
* @}
*/
/** @defgroup UART_Hardware_Flow_Control
* @{
*/
#define UART_HardwareFlowControl_Disable ((uint32_t)0x00000000)
#define UART_HardwareFlowControl_Enable ((uint32_t)0x00000020)
#define UART_HardwareFlowControl_Automatic ((uint32_t)0x00000060)
#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == UART_HardwareFlowControl_Disable) || \
((CONTROL) == UART_HardwareFlowControl_Enable) || \
((CONTROL) == UART_HardwareFlowControl_Automatic))
/**
* @}
*/
/** @defgroup UART_flags_definition
* @{
*/
#define UART_FLAG_CTS ((uint32_t)SC_UARTSR_CTS)
#define UART_FLAG_RXNE ((uint32_t)SC_UARTSR_RXNE)
#define UART_FLAG_TXE ((uint32_t)SC_UARTSR_TXE)
#define UART_FLAG_OVR ((uint32_t)SC_UARTSR_OVR)
#define UART_FLAG_FE ((uint32_t)SC_UARTSR_FE)
#define UART_FLAG_PE ((uint32_t)SC_UARTSR_PE)
#define UART_FLAG_IDLE ((uint32_t)SC_UARTSR_IDLE)
#define IS_UART_GET_FLAG(FLAG) (((FLAG) == UART_FLAG_CTS) || ((FLAG) == UART_FLAG_RXNE) || \
((FLAG) == UART_FLAG_TXE) || ((FLAG) == UART_FLAG_OVR) || \
((FLAG) == UART_FLAG_FE) || ((FLAG) == UART_FLAG_PE)|| \
((FLAG) == UART_FLAG_IDLE))
/**
* @}
*/
/** @defgroup UART_interrupts_definition
* @{
*/
#define UART_IT_PE ((uint32_t)SC_ISR_PE)
#define UART_IT_FE ((uint32_t)SC_ISR_FE)
#define UART_IT_UND ((uint32_t)SC_ISR_UND)
#define UART_IT_OVR ((uint32_t)SC_ISR_OVR)
#define UART_IT_IDLE ((uint32_t)SC_ISR_IDLE)
#define UART_IT_TXE ((uint32_t)SC_ISR_TXE)
#define UART_IT_RXNE ((uint32_t)SC_ISR_RXNE)
#define IS_UART_IT(IT) (((IT) == UART_IT_PE) || ((IT) == UART_IT_FE) || \
((IT) == UART_IT_UND) || ((IT) == UART_IT_OVR) || \
((IT) == UART_IT_IDLE) || ((IT) == UART_IT_TXE) || \
((IT) == UART_IT_RXNE))
#define IS_UART_TRIGGEREVENT_IT(IT) (((IT) == UART_IT_IDLE) || ((IT) == UART_IT_TXE) || \
((IT) == UART_IT_RXNE))
/**
* @}
*/
#define IS_UART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) <= 1500000))
/**
* @}
*/
/** @defgroup SC_I2C_Exported_Constants
* @{
*/
/** @defgroup I2C_transfer_direction
* @{
*/
#define I2C_Direction_Transmitter ((uint8_t)0x00)
#define I2C_Direction_Receiver ((uint8_t)0x01)
#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
((DIRECTION) == I2C_Direction_Receiver))
/**
* @}
*/
/** @defgroup I2C_flags_definition
* @{
*/
#define I2C_FLAG_NACK ((uint32_t)SC_I2CSR_NACK)
#define I2C_FLAG_BTF ((uint32_t)SC_I2CSR_BTF)
#define I2C_FLAG_BRF ((uint32_t)SC_I2CSR_BRF)
#define I2C_FLAG_CMDFIN ((uint32_t)SC_I2CSR_CMDFIN)
#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == SC_I2CSR_NACK) || ((FLAG) == SC_I2CSR_BTF) || \
((FLAG) == SC_I2CSR_BRF) || ((FLAG) == SC_I2CSR_CMDFIN))
/**
* @}
*/
/** @defgroup I2C_interrupts_definition
* @{
*/
#define I2C_IT_NACK ((uint32_t)SC_ISR_NACK)
#define I2C_IT_CMDFIN ((uint32_t)SC_ISR_CMDFIN)
#define I2C_IT_BTF ((uint32_t)SC_ISR_BTF)
#define I2C_IT_BRF ((uint32_t)SC_ISR_BRF)
#define IS_I2C_IT(IT) (((IT) == I2C_IT_NACK) || ((IT) == I2C_IT_CMDFIN) || \
((IT) == I2C_IT_BTF) || ((IT) == I2C_IT_BRF))
/**
* @}
*/
#define IS_I2C_CLOCK_RATE(RATE) (((RATE) > 0) && ((RATE) <= 400000))
/**
* @}
*/
/** @defgroup SC_DMA_Exported_Constants
* @{
*/
/** @defgroup DMA_Channel_Load
* @{
*/
#define DMA_ChannelLoad_BTx ((uint32_t)SC_DMACR_TXLODB)
#define DMA_ChannelLoad_ATx ((uint32_t)SC_DMACR_TXLODA)
#define DMA_ChannelLoad_BRx ((uint32_t)SC_DMACR_RXLODB)
#define DMA_ChannelLoad_ARx ((uint32_t)SC_DMACR_RXLODA)
#define IS_DMA_CHANNEL_LOAD(CHANNEL) (((CHANNEL) == DMA_ChannelLoad_BTx) || ((CHANNEL) == DMA_ChannelLoad_ATx) || \
((CHANNEL) == DMA_ChannelLoad_BRx) || ((CHANNEL) == DMA_ChannelLoad_ARx))
/**
* @}
*/
/** @defgroup DMA_Counter_Register
* @{
*/
#define DMA_Counter_RXCNTA ((uint32_t)0x00000000)
#define DMA_Counter_RXCNTB ((uint32_t)0x00000004)
#define DMA_Counter_TXCNT ((uint32_t)0x00000008)
#define DMA_Counter_RXCNTSAVED ((uint32_t)0x00000050)
#define IS_DMA_COUNTER(COUNTER) (((COUNTER) == DMA_Counter_RXCNTA) || ((COUNTER) == DMA_Counter_RXCNTB) || \
((COUNTER) == DMA_Counter_TXCNT) || ((COUNTER) == DMA_Counter_RXCNTSAVED))
/**
* @}
*/
/** @defgroup DMA_Receiver_Error_Register
* @{
*/
#define DMA_ReceiverError_CNTA ((uint32_t)0x00000014)
#define DMA_ReceiverError_CNTB ((uint32_t)0x00000018)
#define IS_DMA_RECEIVER_ERROR(REGISTER) (((REGISTER) == DMA_ReceiverError_CNTA) || ((REGISTER) == DMA_ReceiverError_CNTB))
/**
* @}
*/
/** @defgroup DMA_Channel_Reset
* @{
*/
#define DMA_ChannelReset_Tx ((uint32_t)SC_DMACR_TXRST)
#define DMA_ChannelReset_Rx ((uint32_t)SC_DMACR_RXRST)
#define IS_DMA_CHANNEL_RESET(CHANNEL) (((CHANNEL) == DMA_ChannelReset_Tx) || ((CHANNEL) == DMA_ChannelReset_Rx))
/**
* @}
*/
/** @defgroup DMA_flags_definition
* @{
*/
#define DMA_FLAG_RXAACK ((uint32_t)SC_DMASR_RXAACK)
#define DMA_FLAG_RXBACK ((uint32_t)SC_DMASR_RXBACK)
#define DMA_FLAG_TXAACK ((uint32_t)SC_DMASR_TXAACK)
#define DMA_FLAG_TXBACK ((uint32_t)SC_DMASR_TXBACK)
#define DMA_FLAG_OVRA ((uint32_t)SC_DMASR_OVRA)
#define DMA_FLAG_OVRB ((uint32_t)SC_DMASR_OVRB)
#define DMA_FLAG_PEA ((uint32_t)SC_DMASR_PEA)
#define DMA_FLAG_PEB ((uint32_t)SC_DMASR_PEB)
#define DMA_FLAG_FEA ((uint32_t)SC_DMASR_FEA)
#define DMA_FLAG_FEB ((uint32_t)SC_DMASR_FEB)
#define DMA_FLAG_NSSS ((uint32_t)SC_DMASR_NSSS)
#define IS_DMA_FLAG(FLAG) (((FLAG) == DMA_FLAG_RXAACK) || ((FLAG) == DMA_FLAG_RXBACK) || \
((FLAG) == DMA_FLAG_TXAACK) || ((FLAG) == DMA_FLAG_TXBACK) || \
((FLAG) == DMA_FLAG_OVRA) || ((FLAG) == DMA_FLAG_OVRB) || \
((FLAG) == DMA_FLAG_PEA) || ((FLAG) == DMA_FLAG_PEB) || \
((FLAG) == DMA_FLAG_FEA) || ((FLAG) == DMA_FLAG_FEB) || \
((FLAG) == DMA_FLAG_NSSS))
/**
* @}
*/
/** @defgroup DMA_interrupts_definition
* @{
*/
#define DMA_IT_TXULODB ((uint32_t)SC_ISR_TXULODB)
#define DMA_IT_TXULODA ((uint32_t)SC_ISR_TXULODA)
#define DMA_IT_RXULODB ((uint32_t)SC_ISR_RXULODB)
#define DMA_IT_RXULODA ((uint32_t)SC_ISR_RXULODA)
#define IS_DMA_IT(IT) (((IT) == DMA_IT_TXULODB) || ((IT) == DMA_IT_TXULODA) || \
((IT) == DMA_IT_RXULODB) || ((IT) == DMA_IT_RXULODA))
/**
* @}
*/
#define IS_DMA_CHANNEL_PERIPH(PERIPH) (((PERIPH) == SC1_DMA_ChannelTx) || \
((PERIPH) == SC1_DMA_ChannelRx) || \
((PERIPH) == SC2_DMA_ChannelTx) || \
((PERIPH) == SC2_DMA_ChannelRx))
#define IS_DMA_VALID_ADDRESS(ADDRESS) (((ADDRESS) >= 0x20000000) && ((ADDRESS) <= 0x20000FFF))
/**
* @}
*/
/**
* @}
*/
/** @defgroup SC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup SC_Exported_Functions
* @{
*/
void UART_DeInit(SC_UART_TypeDef* SCx_UART);
void UART_Init(SC_UART_TypeDef* SCx_UART, UART_InitTypeDef* UART_InitStruct);
void UART_StructInit(UART_InitTypeDef* UART_InitStruct);
void UART_Cmd(SC_UART_TypeDef* SCx_UART, FunctionalState NewState);
void UART_ITConfig(SC_IT_TypeDef* SCx_IT, uint32_t UART_IT, FunctionalState NewState);
void UART_TriggerEventConfig(SC_IT_TypeDef* SCx_IT, uint32_t UART_IT, uint32_t TriggerEvent);
void UART_RTSAssertionCmd(SC_UART_TypeDef* SCx_UART, FunctionalState NewState);
void UART_SendData(SC_UART_TypeDef* SCx_UART, uint8_t Data);
uint8_t UART_ReceiveData(SC_UART_TypeDef* SCx_UART);
FlagStatus UART_GetFlagStatus(SC_UART_TypeDef* SCx_UART, uint32_t UART_FLAG);
ITStatus UART_GetITStatus(SC_IT_TypeDef* SCx_IT, uint32_t UART_IT);
void UART_ClearITPendingBit(SC_IT_TypeDef* SCx_IT, uint32_t UART_IT);
void SPI_DeInit(SC_SPI_TypeDef* SCx_SPI);
void SPI_Init(SC_SPI_TypeDef* SCx_SPI, SPI_InitTypeDef* SPI_InitStruct);
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
void SPI_ReceiverModeConfig(SC_SPI_TypeDef* SCx_SPI, uint32_t SPI_ReceiverMode);
void SPI_LastByteRepeatCmd(SC_SPI_TypeDef* SCx_SPI, FunctionalState NewState);
void SPI_Cmd(SC_SPI_TypeDef* SCx_SPI, FunctionalState NewState);
void SPI_ITConfig(SC_IT_TypeDef* SCx_IT, uint32_t SPI_IT, FunctionalState NewState);
void SPI_TriggerEventConfig(SC_IT_TypeDef* SCx_IT, uint32_t SPI_IT, uint32_t TriggerEvent);
void SPI_SendData(SC_SPI_TypeDef* SCx_SPI, uint8_t Data);
uint8_t SPI_ReceiveData(SC_SPI_TypeDef* SCx_SPI);
FlagStatus SPI_GetFlagStatus(SC_SPI_TypeDef* SCx_SPI, uint32_t SPI_FLAG);
ITStatus SPI_GetITStatus(SC_IT_TypeDef* SCx_IT, uint32_t SPI_IT);
void SPI_ClearITPendingBit(SC_IT_TypeDef* SCx_IT, uint32_t SPI_IT);
void I2C_DeInit(SC_I2C_TypeDef* SCx_I2C);
void I2C_Init(SC_I2C_TypeDef* SCx_I2C, I2C_InitTypeDef* I2C_InitStruct);
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
void I2C_Cmd(SC_I2C_TypeDef* SCx_I2C, FunctionalState NewState);
void I2C_ITConfig(SC_IT_TypeDef* SCx_IT, uint32_t I2C_IT, FunctionalState NewState);
void I2C_GenerateSTART(SC_I2C_TypeDef* SCx_I2C);
void I2C_GenerateSTOP(SC_I2C_TypeDef* SCx_I2C);
void I2C_AcknowledgeConfig(SC_I2C_TypeDef* SCx_I2C, FunctionalState NewState);
void I2C_Send7bitAddress(SC_I2C_TypeDef* SCx_I2C, uint8_t Address, uint8_t I2C_Direction);
void I2C_SendData(SC_I2C_TypeDef* SCx_I2C, uint8_t Data);
uint8_t I2C_ReceiveData(SC_I2C_TypeDef* SCx_I2C);
FlagStatus I2C_GetFlagStatus(SC_I2C_TypeDef* SCx_I2C, uint32_t I2C_FLAG);
ITStatus I2C_GetITStatus(SC_IT_TypeDef* SCx_IT, uint32_t I2C_IT);
void I2C_ClearITPendingBit(SC_IT_TypeDef* SCx_IT, uint32_t I2C_IT);
void SC_DMA_ChannelReset(SC_DMA_TypeDef* SCx_DMA, uint32_t Channely);
void SC_DMA_Init(SC_DMA_Channel_TypeDef* SCx_DMA_Channely, SC_DMA_InitTypeDef* SC_DMA_InitStruct);
void SC_DMA_StructInit(SC_DMA_InitTypeDef* SC_DMA_InitStruct);
void SC_DMA_ChannelLoadEnable(SC_DMA_TypeDef* SCx_DMA, uint32_t Channelxy);
void SC_DMA_ITConfig(SC_IT_TypeDef* SCx_IT, uint32_t DMA_IT, FunctionalState NewState);
uint32_t SC_DMA_GetCounter(SC_DMA_TypeDef* SCx_DMA, uint32_t Counter);
uint32_t SC_DMA_GetReceiverErrorOffset(SC_DMA_TypeDef* SCx_DMA, uint32_t RegisterError);
FlagStatus SC_DMA_GetFlagStatus(SC_DMA_TypeDef* SCx_DMA, uint32_t DMA_FLAG);
ITStatus SC_DMA_GetITStatus(SC_IT_TypeDef* SCx_IT, uint32_t DMA_IT);
void SC_DMA_ClearITPendingBit(SC_IT_TypeDef* SCx_IT, uint32_t DMA_IT);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__STM32W108XX_SC_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

213
libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_slptim.h
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@ -1,213 +0,0 @@
/**
******************************************************************************
* @file stm32w108xx_slptim.h
* @author MCD Application Team
* @version V1.0.1
* @date 30-November-2012
* @brief This file contains all the functions prototypes for the TIM
* firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32W108XX_SLPTIM_H
#define __STM32W108XX_SLPTIM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32w108xx.h"
/** @addtogroup STM32W108xx_StdPeriph_Driver
* @{
*/
/** @addtogroup SLPTIM
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief SLPTIM Init structure definition
*/
typedef struct
{
uint32_t SLPTIM_Clock; /*!< Specifies the clock to be used.
This parameter must be a value of @ref SLPTIM_Clocks_Select */
uint32_t SLPTIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
This parameter can be a value of @ref SLPTIM_Clock_Division */
uint32_t SLPTIM_DebugMode; /*!< Specifies whether the timer is running or paused during debug mode.
This parameter must be a value of @ref SLPTIM_Debug_Mode */
uint32_t SLPTIM_CounterMode; /*!< Specifies the counter mode.
This parameter can be a value of @ref SLPTIM_Counter_Mode */
} SLPTIM_InitTypeDef;
/** @defgroup SLPTIM_Exported_Constants
* @{
*/
/** @defgroup SLPTIM_Clocks_Select
* @{
*/
#define SLPTIM_CLK_32KHZ ((uint32_t)SLPTMR_CR_CLKSEL)
#define SLPTIM_CLK_1KHZ ((uint32_t)0x00000000)
#define IS_SLPTIM_GET_CLKSEL(CLK) (((CLK) == SLPTIM_CLK_32KHZ) || \
((CLK) == SLPTIM_CLK_1KHZ))
/**
* @}
*/
/** @defgroup SLPTIM_Clock_Division
* @{
*/
#define SLPTIM_CLK_DIV0 ((uint32_t)0x00000000)
#define SLPTIM_CLK_DIV1 ((uint32_t)0x00000010)
#define SLPTIM_CLK_DIV2 ((uint32_t)0x00000020)
#define SLPTIM_CLK_DIV3 ((uint32_t)0x00000030)
#define SLPTIM_CLK_DIV4 ((uint32_t)0x00000040)
#define SLPTIM_CLK_DIV5 ((uint32_t)0x00000050)
#define SLPTIM_CLK_DIV6 ((uint32_t)0x00000060)
#define SLPTIM_CLK_DIV7 ((uint32_t)0x00000070)
#define SLPTIM_CLK_DIV8 ((uint32_t)0x00000080)
#define SLPTIM_CLK_DIV9 ((uint32_t)0x00000090)
#define SLPTIM_CLK_DIV10 ((uint32_t)0x000000A0)
#define SLPTIM_CLK_DIV11 ((uint32_t)0x000000B0)
#define SLPTIM_CLK_DIV12 ((uint32_t)0x000000C0)
#define SLPTIM_CLK_DIV13 ((uint32_t)0x000000D0)
#define SLPTIM_CLK_DIV14 ((uint32_t)0x000000E0)
#define SLPTIM_CLK_DIV15 ((uint32_t)0x000000F0)
#define IS_SLPTIM_CLKDIV(CLKDIV) (((CLKDIV) == SLPTIM_CLK_DIV0) || ((CLKDIV) == SLPTIM_CLK_DIV1) || \
((CLKDIV) == SLPTIM_CLK_DIV2) || ((CLKDIV) == SLPTIM_CLK_DIV3) || \
((CLKDIV) == SLPTIM_CLK_DIV4) || ((CLKDIV) == SLPTIM_CLK_DIV5) || \
((CLKDIV) == SLPTIM_CLK_DIV6) || ((CLKDIV) == SLPTIM_CLK_DIV7) || \
((CLKDIV) == SLPTIM_CLK_DIV8) || ((CLKDIV) == SLPTIM_CLK_DIV9) || \
((CLKDIV) == SLPTIM_CLK_DIV10) || ((CLKDIV) == SLPTIM_CLK_DIV11) || \
((CLKDIV) == SLPTIM_CLK_DIV12) || ((CLKDIV) == SLPTIM_CLK_DIV13) || \
((CLKDIV) == SLPTIM_CLK_DIV14) || ((CLKDIV) == SLPTIM_CLK_DIV15))
/**
* @}
*/
/** @defgroup SLPTIM_Debug_Mode
* @{
*/
#define SLPTIM_DBGRUN ((uint32_t)0x00000000)
#define SLPTIM_DBGPAUSE ((uint32_t)SLPTMR_CR_DBGP)
#define IS_SLPTIM_DBGMODE(DBGMODE) (((DBGMODE) == SLPTIM_DBGRUN) || \
((DBGMODE) == SLPTIM_DBGPAUSE))
/**
* @}
*/
/** @defgroup SLPTIM_Counter_Mode
* @{
*/
#define SLPTIM_CountForward ((uint32_t)0x00000000)
#define SLPTIM_CountBackward ((uint32_t)SLPTMR_CR_REVERSE)
#define IS_SLPTIM_COUNTER_MODE(MODE) (((MODE) == SLPTIM_CountForward) || \
((MODE) == SLPTIM_CountBackward))
/**
* @}
*/
/** @defgroup SLPTIM_interrupt_sources
* @{
*/
#define SLPTIM_IT_WRAP ((uint32_t)SLPTMR_IER_WRAP)
#define SLPTIM_IT_CMPA ((uint32_t)SLPTMR_IER_CMPA)
#define SLPTIM_IT_CMPB ((uint32_t)SLPTMR_IER_CMPB)
#define IS_SLPTIM_IT(IT) (((IT) == SLPTIM_IT_WRAP) || \
((IT) == SLPTIM_IT_CMPA) || \
((IT) == SLPTIM_IT_CMPB))
/**
* @}
*/
/** @defgroup SLPTIM_flags
* @{
*/
#define SLPTIM_FLAG_WRAP ((uint32_t)SLPTMR_ISR_WRAP)
#define SLPTIM_FLAG_CMPA ((uint32_t)SLPTMR_ISR_CMPA)
#define SLPTIM_FLAG_CMPB ((uint32_t)SLPTMR_ISR_CMPB)
#define IS_SLPTIM_FLAG(FLAG) (((FLAG) == SLPTIM_FLAG_WRAP) || \
((FLAG) == SLPTIM_FLAG_CMPA) || \
((FLAG) == SLPTIM_FLAG_CMPB))
/**
* @}
*/
/**
* @}
*/
/** @defgroup SLPTIM_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup SLPTIM_Exported_Functions
* @{
*/
/* SLPTIM management functions ************************************************/
void SLPTIM_DeInit(void);
void SLPTIM_Init(SLPTIM_InitTypeDef* SLPTIM_InitStruct);
void SLPTIM_StructInit(SLPTIM_InitTypeDef* SLPTIM_InitStruct);
void SLPTIM_Cmd(FunctionalState NewState);
void SLPTIM_SetCompareA(uint32_t CompareA);
void SLPTIM_SetCompareB(uint32_t CompareB);
uint32_t SLPTIM_GetCounter(void);
uint32_t SLPTIM_GetCounterHigh(void);
uint32_t SLPTIM_GetCounterLow(void);
/* Interrupts and flags management functions **********************************/
void SLPTIM_ForceIT(uint32_t SLPTIM_IT);
void SLPTIM_ITConfig(uint32_t SLPTIM_IT, FunctionalState NewState);
FlagStatus SLPTIM_GetFlagStatus(uint32_t SLPTIM_FLAG);
void SLPTIM_ClearFlag(uint32_t SLPTIM_FLAG);
ITStatus SLPTIM_GetITStatus(uint32_t SLPTIM_IT);
void SLPTIM_ClearITPendingBit(uint32_t SLPTIM_IT);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__STM32W108XX_SLPTIM_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

658
libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_tim.h
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@ -1,658 +0,0 @@
/**
******************************************************************************
* @file stm32w108xx_tim.h
* @author MCD Application Team
* @version V1.0.1
* @date 30-November-2012
* @brief This file contains all the functions prototypes for the TIM
* firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32W108XX_TIM_H
#define __STM32W108XX_TIM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32w108xx.h"
/** @addtogroup STM32W108xx_StdPeriph_Driver
* @{
*/
/** @addtogroup TIM
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief TIM Time Base Init structure definition
* @note This sturcture is used with all TIMx.
*/
typedef struct
{
uint32_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
This parameter can be a number between 0x0000 and 0x000F */
uint32_t TIM_CounterMode; /*!< Specifies the counter mode.
This parameter can be a value of @ref TIM_Counter_Mode */
uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active
Auto-Reload Register at the next update event.
This parameter must be a number between 0x0000 and 0xFFFF. */
} TIM_TimeBaseInitTypeDef;
/**
* @brief TIM Output Compare Init structure definition
*/
typedef struct
{
uint32_t TIM_OCMode; /*!< Specifies the TIM mode.
This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
uint32_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
This parameter can be a value of @ref TIM_Output_Compare_state */
uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
This parameter can be a number between 0x0000 and 0xFFFF */
uint32_t TIM_OCPolarity; /*!< Specifies the output polarity.
This parameter can be a value of @ref TIM_Output_Compare_Polarity */
} TIM_OCInitTypeDef;
/**
* @brief TIM Input Capture Init structure definition
*/
typedef struct
{
uint32_t TIM_Channel; /*!< Specifies the TIM channel.
This parameter can be a value of @ref TIM_Channel */
uint32_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
uint32_t TIM_ICSelection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
uint32_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
uint32_t TIM_ICFilter; /*!< Specifies the input capture filter.
This parameter can be a number between 0x0 and 0xF */
} TIM_ICInitTypeDef;
/** @defgroup TIM_Exported_constants
* @{
*/
#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
((PERIPH) == TIM2))
#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM2))
#define IS_TIM_IT_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1_IT) || \
((PERIPH) == TIM2_IT))
/** @defgroup TIM_Output_Compare_and_PWM_modes
* @{
*/
#define TIM_OCMode_Timing ((uint32_t)0x00000000)
#define TIM_OCMode_Active ((uint32_t)0x00000010)
#define TIM_OCMode_Inactive ((uint32_t)0x00000020)
#define TIM_OCMode_Toggle ((uint32_t)0x00000030)
#define TIM_OCMode_PWM1 ((uint32_t)0x00000060)
#define TIM_OCMode_PWM2 ((uint32_t)0x00000070)
#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
((MODE) == TIM_OCMode_Active) || \
((MODE) == TIM_OCMode_Inactive) || \
((MODE) == TIM_OCMode_Toggle)|| \
((MODE) == TIM_OCMode_PWM1) || \
((MODE) == TIM_OCMode_PWM2))
#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
((MODE) == TIM_OCMode_Active) || \
((MODE) == TIM_OCMode_Inactive) || \
((MODE) == TIM_OCMode_Toggle)|| \
((MODE) == TIM_OCMode_PWM1) || \
((MODE) == TIM_OCMode_PWM2) || \
((MODE) == TIM_ForcedAction_Active) || \
((MODE) == TIM_ForcedAction_InActive))
/**
* @}
*/
/** @defgroup TIM_One_Pulse_Mode
* @{
*/
#define TIM_OPMode_Single ((uint32_t)0x00000008)
#define TIM_OPMode_Repetitive ((uint32_t)0x00000000)
#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
((MODE) == TIM_OPMode_Repetitive))
/**
* @}
*/
/** @defgroup TIM_Channel
* @{
*/
#define TIM_Channel_1 ((uint32_t)0x00000000)
#define TIM_Channel_2 ((uint32_t)0x00000004)
#define TIM_Channel_3 ((uint32_t)0x00000008)
#define TIM_Channel_4 ((uint32_t)0x0000000C)
#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
((CHANNEL) == TIM_Channel_2) || \
((CHANNEL) == TIM_Channel_3) || \
((CHANNEL) == TIM_Channel_4))
#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
((CHANNEL) == TIM_Channel_2))
/**
* @}
*/
/** @defgroup TIM_Counter_Mode
* @{
*/
#define TIM_CounterMode_Up ((uint32_t)0x00000000)
#define TIM_CounterMode_Down ((uint32_t)0x00000010)
#define TIM_CounterMode_CenterAligned1 ((uint32_t)0x00000020)
#define TIM_CounterMode_CenterAligned2 ((uint32_t)0x00000040)
#define TIM_CounterMode_CenterAligned3 ((uint32_t)0x00000060)
#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
((MODE) == TIM_CounterMode_Down) || \
((MODE) == TIM_CounterMode_CenterAligned1) || \
((MODE) == TIM_CounterMode_CenterAligned2) || \
((MODE) == TIM_CounterMode_CenterAligned3))
/**
* @}
*/
/** @defgroup TIM_Output_Compare_Polarity
* @{
*/
#define TIM_OCPolarity_High ((uint32_t)0x00000000)
#define TIM_OCPolarity_Low ((uint32_t)0x00000002)
#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
((POLARITY) == TIM_OCPolarity_Low))
/**
* @}
*/
/** @defgroup TIM_Output_Compare_state
* @{
*/
#define TIM_OutputState_Disable ((uint32_t)0x00000000)
#define TIM_OutputState_Enable ((uint32_t)0x00000001)
#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
((STATE) == TIM_OutputState_Enable))
/**
* @}
*/
/** @defgroup TIM_Capture_Compare_state
* @{
*/
#define TIM_CCx_Enable ((uint32_t)0x00000001)
#define TIM_CCx_Disable ((uint32_t)0x00000000)
#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
((CCX) == TIM_CCx_Disable))
/**
* @}
*/
/** @defgroup TIM_Input_Capture_Polarity
* @{
*/
#define TIM_ICPolarity_Rising ((uint32_t)0x00000000)
#define TIM_ICPolarity_Falling ((uint32_t)0x00000002)
#define TIM_ICPolarity_BothEdge ((uint32_t)0x0000000A)
#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
((POLARITY) == TIM_ICPolarity_Falling)|| \
((POLARITY) == TIM_ICPolarity_BothEdge))
/**
* @}
*/
/** @defgroup TIM_Input_Capture_Selection
* @{
*/
#define TIM_ICSelection_DirectTI ((uint32_t)0x00000001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
connected to IC1, IC2, IC3 or IC4, respectively */
#define TIM_ICSelection_IndirectTI ((uint32_t)0x00000002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
connected to IC2, IC1, IC4 or IC3, respectively. */
#define TIM_ICSelection_TRGI ((uint32_t)0x00000003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
((SELECTION) == TIM_ICSelection_IndirectTI) || \
((SELECTION) == TIM_ICSelection_TRGI))
/**
* @}
*/
/** @defgroup TIM_Input_Capture_Prescaler
* @{
*/
#define TIM_ICPSC_DIV1 ((uint32_t)0x00000000) /*!< Capture performed each time an edge is detected on the capture input. */
#define TIM_ICPSC_DIV2 ((uint32_t)0x00000004) /*!< Capture performed once every 2 events. */
#define TIM_ICPSC_DIV4 ((uint32_t)0x00000008) /*!< Capture performed once every 4 events. */
#define TIM_ICPSC_DIV8 ((uint32_t)0x0000000C) /*!< Capture performed once every 8 events. */
#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
((PRESCALER) == TIM_ICPSC_DIV2) || \
((PRESCALER) == TIM_ICPSC_DIV4) || \
((PRESCALER) == TIM_ICPSC_DIV8))
/**
* @}
*/
/** @defgroup TIM_interrupt_sources
* @{
*/
#define TIM_IT_Update ((uint32_t)0x00000001)
#define TIM_IT_CC1 ((uint32_t)0x00000002)
#define TIM_IT_CC2 ((uint32_t)0x00000004)
#define TIM_IT_CC3 ((uint32_t)0x00000008)
#define TIM_IT_CC4 ((uint32_t)0x00000010)
#define TIM_IT_Trigger ((uint32_t)0x00000040)
#define IS_TIM_ITRPT(IT) ((((IT) & (uint32_t)0xFFFFFF00) == 0x00000000) && ((IT) != 0x00000000))
#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
((IT) == TIM_IT_CC1) || \
((IT) == TIM_IT_CC2) || \
((IT) == TIM_IT_CC3) || \
((IT) == TIM_IT_CC4) || \
((IT) == TIM_IT_Trigger))
/**
* @}
*/
/** @defgroup TIM_External_Trigger_Prescaler
* @{
*/
#define TIM_ExtTRGPSC_OFF ((uint32_t)0x00000000)
#define TIM_ExtTRGPSC_DIV2 ((uint32_t)0x00001000)
#define TIM_ExtTRGPSC_DIV4 ((uint32_t)0x00002000)
#define TIM_ExtTRGPSC_DIV8 ((uint32_t)0x00003000)
#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
((PRESCALER) == TIM_ExtTRGPSC_DIV8))
/**
* @}
*/
/** @defgroup TIM_Internal_Trigger_Selection
* @{
*/
#define TIM_TS_ITR0 ((uint32_t)0x00000000)
#define TIM_TS_TI1F_ED ((uint32_t)0x00000040)
#define TIM_TS_TI1FP1 ((uint32_t)0x00000050)
#define TIM_TS_TI2FP2 ((uint32_t)0x00000060)
#define TIM_TS_ETRF ((uint32_t)0x00000070)
#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
((SELECTION) == TIM_TS_TI1F_ED) || \
((SELECTION) == TIM_TS_TI1FP1) || \
((SELECTION) == TIM_TS_TI2FP2) || \
((SELECTION) == TIM_TS_ETRF))
#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0))
/**
* @}
*/
/** @defgroup TIM_TIx_External_Clock_Source
* @{
*/
#define TIM_TIxExternalCLK1Source_TI1 ((uint32_t)0x00000050)
#define TIM_TIxExternalCLK1Source_TI2 ((uint32_t)0x00000060)
#define TIM_TIxExternalCLK1Source_TI1ED ((uint32_t)0x00000040)
/**
* @}
*/
/** @defgroup TIM_External_Trigger_Polarity
* @{
*/
#define TIM_ExtTRGPolarity_Inverted ((uint32_t)0x00008000)
#define TIM_ExtTRGPolarity_NonInverted ((uint32_t)0x00000000)
#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
/**
* @}
*/
/** @defgroup TIM_Prescaler_Reload_Mode
* @{
*/
#define TIM_PSCReloadMode_Update ((uint32_t)0x00000000)
#define TIM_PSCReloadMode_Immediate ((uint32_t)0x00000001)
#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
((RELOAD) == TIM_PSCReloadMode_Immediate))
/**
* @}
*/
/** @defgroup TIM_Forced_Action
* @{
*/
#define TIM_ForcedAction_Active ((uint32_t)0x00000050)
#define TIM_ForcedAction_InActive ((uint32_t)0x00000040)
#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
((ACTION) == TIM_ForcedAction_InActive))
/**
* @}
*/
/** @defgroup TIM_Encoder_Mode
* @{
*/
#define TIM_EncoderMode_TI1 ((uint32_t)0x00000001)
#define TIM_EncoderMode_TI2 ((uint32_t)0x00000002)
#define TIM_EncoderMode_TI12 ((uint32_t)0x00000003)
#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
((MODE) == TIM_EncoderMode_TI2) || \
((MODE) == TIM_EncoderMode_TI12))
/**
* @}
*/
/** @defgroup TIM_Event_Source
* @{
*/
#define TIM_EventSource_Update ((uint32_t)0x00000001)
#define TIM_EventSource_CC1 ((uint32_t)0x00000002)
#define TIM_EventSource_CC2 ((uint32_t)0x00000004)
#define TIM_EventSource_CC3 ((uint32_t)0x00000008)
#define TIM_EventSource_CC4 ((uint32_t)0x00000010)
#define TIM_EventSource_Trigger ((uint32_t)0x00000040)
#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint32_t)0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
/**
* @}
*/
/** @defgroup TIM_Update_Source
* @{
*/
#define TIM_UpdateSource_Global ((uint32_t)0x00000000) /*!< Source of update is the counter overflow/underflow
or the setting of UG bit, or an update generation
through the slave mode controller. */
#define TIM_UpdateSource_Regular ((uint32_t)0x00000001) /*!< Source of update is counter overflow/underflow. */
#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
((SOURCE) == TIM_UpdateSource_Regular))
/**
* @}
*/
/** @defgroup TIM_Output_Compare_Preload_State
* @{
*/
#define TIM_OCPreload_Enable ((uint32_t)0x00000008)
#define TIM_OCPreload_Disable ((uint32_t)0x00000000)
#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
((STATE) == TIM_OCPreload_Disable))
/**
* @}
*/
/** @defgroup TIM_Output_Compare_Fast_State
* @{
*/
#define TIM_OCFast_Enable ((uint32_t)0x00000004)
#define TIM_OCFast_Disable ((uint32_t)0x00000000)
#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
((STATE) == TIM_OCFast_Disable))
/**
* @}
*/
/** @defgroup TIM_Trigger_Output_Source
* @{
*/
#define TIM_TRGOSource_Reset ((uint32_t)0x00000000)
#define TIM_TRGOSource_Enable ((uint32_t)0x00000010)
#define TIM_TRGOSource_Update ((uint32_t)0x00000020)
#define TIM_TRGOSource_OC1 ((uint32_t)0x00000030)
#define TIM_TRGOSource_OC1Ref ((uint32_t)0x00000040)
#define TIM_TRGOSource_OC2Ref ((uint32_t)0x00000050)
#define TIM_TRGOSource_OC3Ref ((uint32_t)0x00000060)
#define TIM_TRGOSource_OC4Ref ((uint32_t)0x00000070)
#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
((SOURCE) == TIM_TRGOSource_Enable) || \
((SOURCE) == TIM_TRGOSource_Update) || \
((SOURCE) == TIM_TRGOSource_OC1) || \
((SOURCE) == TIM_TRGOSource_OC1Ref) || \
((SOURCE) == TIM_TRGOSource_OC2Ref) || \
((SOURCE) == TIM_TRGOSource_OC3Ref) || \
((SOURCE) == TIM_TRGOSource_OC4Ref))
/**
* @}
*/
/** @defgroup TIM_Slave_Mode
* @{
*/
#define TIM_SlaveMode_Reset ((uint32_t)0x00000004)
#define TIM_SlaveMode_Gated ((uint32_t)0x00000005)
#define TIM_SlaveMode_Trigger ((uint32_t)0x00000006)
#define TIM_SlaveMode_External1 ((uint32_t)0x00000007)
#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
((MODE) == TIM_SlaveMode_Gated) || \
((MODE) == TIM_SlaveMode_Trigger) || \
((MODE) == TIM_SlaveMode_External1))
/**
* @}
*/
/** @defgroup TIM_Master_Slave_Mode
* @{
*/
#define TIM_MasterSlaveMode_Enable ((uint32_t)0x00000080)
#define TIM_MasterSlaveMode_Disable ((uint32_t)0x00000000)
#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
((STATE) == TIM_MasterSlaveMode_Disable))
/**
* @}
*/
/** @defgroup TIM_Input_Capture_Filer_Value
* @{
*/
#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
/**
* @}
*/
/** @defgroup TIM_External_Trigger_Filter
* @{
*/
#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
/**
* @}
*/
/** @defgroup TIM_OCReferenceClear
* @{
*/
#define TIM_OCReferenceClear_ETRF ((uint32_t)0x00000008)
#define TIM_OCReferenceClear_OCREFCLR ((uint32_t)0x00000000)
#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \
((SOURCE) == TIM_OCReferenceClear_OCREFCLR))
/**
* @}
*/
/** @defgroup TIM_Remap
* @{
*/
#define TIM_REMAPC1 ((uint32_t)0x00000010)
#define TIM_REMAPC2 ((uint32_t)0x00000020)
#define TIM_REMAPC3 ((uint32_t)0x00000040)
#define TIM_REMAPC4 ((uint32_t)0x00000080)
#define IS_TIM_REMAP(TIM_Remap) (((TIM_Remap) == TIM_REMAPC1) || \
((TIM_Remap) == TIM_REMAPC2) || \
((TIM_Remap) == TIM_REMAPC3) || \
((TIM_Remap) == TIM_REMAPC4))
/**
* @}
*/
/** @defgroup TIM_External_Trigger_Selection
* @{
*/
#define TIM_EXTRIGPCLK ((uint32_t)0x00000000)
#define TIM_EXTRIG1KHCLK ((uint32_t)0x00000001)
#define TIM_EXTRIG32KHCLK ((uint32_t)0x00000002)
#define TIM_EXTRIGTIMxCLK ((uint32_t)0x00000003)
#define IS_TIM_EXTRIGCLK(EXTRIGCLK) (((EXTRIGCLK) == TIM_EXTRIGPCLK) || \
((EXTRIGCLK) == TIM_EXTRIG1KHCLK) || \
((EXTRIGCLK) == TIM_EXTRIG32KHCLK) || \
((EXTRIGCLK) == TIM_EXTRIGTIMxCLK))
/**
* @}
*/
/**
* @}
*/
/** @defgroup TIM_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup TIM_Exported_Functions
* @{
*/
/* TimeBase management ********************************************************/
void TIM_DeInit(TIM_TypeDef* TIMx);
void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint32_t Prescaler, uint32_t TIM_PSCReloadMode);
void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint32_t TIM_CounterMode);
void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
uint32_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint32_t TIM_UpdateSource);
void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint32_t TIM_OPMode);
void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
/* Output Compare management **************************************************/
void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint32_t TIM_Channel, uint32_t TIM_OCMode);
void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint32_t TIM_ForcedAction);
void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint32_t TIM_ForcedAction);
void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint32_t TIM_ForcedAction);
void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint32_t TIM_ForcedAction);
void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPreload);
void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPreload);
void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPreload);
void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPreload);
void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCFast);
void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCFast);
void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCFast);
void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCFast);
void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPolarity);
void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPolarity);
void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPolarity);
void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPolarity);
void TIM_CCxCmd(TIM_TypeDef* TIMx, uint32_t TIM_Channel, uint32_t TIM_CCx);
/* Input Capture management ***************************************************/
void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint32_t TIM_ICPSC);
void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint32_t TIM_ICPSC);
void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint32_t TIM_ICPSC);
void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint32_t TIM_ICPSC);
/* Interrupts and flags management functions **********************************/
void TIM_ITConfig(TIM_IT_TypeDef* TIMx_IT, uint32_t TIM_ITRPT, FunctionalState NewState);
ITStatus TIM_GetITStatus(TIM_IT_TypeDef* TIMx_IT, uint32_t TIM_ITRPT);
void TIM_ClearITPendingBit(TIM_IT_TypeDef* TIMx_IT, uint32_t TIM_ITRPT);
void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint32_t TIM_EventSource);
/* Clocks management **********************************************************/
void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint32_t TIM_InputTriggerSource);
void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint32_t TIM_TIxExternalCLKSource,
uint32_t TIM_ICPolarity, uint32_t ICFilter);
void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity,
uint32_t ExtTRGFilter);
void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
/* Synchronization management *************************************************/
void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint32_t TIM_InputTriggerSource);
void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint32_t TIM_TRGOSource);
void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint32_t TIM_SlaveMode);
void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint32_t TIM_MasterSlaveMode);
void TIM_ETRConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity,
uint32_t ExtTRGFilter);
/* Specific interface management **********************************************/
void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint32_t TIM_EncoderMode,
uint32_t TIM_IC1Polarity, uint32_t TIM_IC2Polarity);
void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
/* Specific remapping management **********************************************/
void TIM_ClockMaskConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
void TIM_SelectExternalTriggerClock(TIM_TypeDef* TIMx, uint32_t TIM_EXTRIGCLK);
void TIM_RemapCmd(TIM_TypeDef* TIMx, uint32_t TIM_Remap, FunctionalState NewState);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__STM32W108XX_TIM_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

105
libs/STM32W108xx_StdPeriph_Driver/inc/stm32w108xx_wdg.h
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@ -1,105 +0,0 @@
/**
******************************************************************************
* @file stm32w108xx_wdg.h
* @author MCD Application Team
* @version V1.0.1
* @date 30-November-2012
* @brief This file contains all the functions prototypes for the WDG
* firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32W108XX_WDG_H
#define __STM32W108XX_WDG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32w108xx.h"
/** @addtogroup STM32W108xx_StdPeriph_Driver
* @{
*/
/** @addtogroup WDG
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup WDG_Exported_Constants
* @{
*/
/** @defgroup WDG_DebugStatus
* @{
*/
#define WDG_DBG_RUN ((uint32_t)0x00000000)
#define WDG_DBG_PAUSE ((uint32_t)0x00000400)
#define IS_WDG_DEBUG_STATUS(STATUS) (((STATUS) == WDG_DBG_RUN) || ((STATUS) == WDG_DBG_PAUSE))
/**
* @}
*/
/**
* @}
*/
/** @defgroup WDG_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup WDG_Exported_Functions
* @{
*/
/* WDG activation function ****************************************************/
void WDG_DeInit(void);
void WDG_ReloadCounter(void);
void WDG_Cmd(FunctionalState NewState);
void WDG_DebugConfig(uint32_t DBG_STATUS);
FunctionalState WDG_GetStatus(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32W108XX_WDG_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

501
libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_adc.c
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@ -1,501 +0,0 @@
/**
******************************************************************************
* @file stm32w108xx_adc.c
* @author MCD Application Team
* @version V1.0.1
* @date 30-November-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC) peripheral:
* + ADC initialization and Configuration
* + DMA Configuration functions
* + Interrupts and flags management functions
*
* @verbatim
*
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
(#) Configure GPIO pins to be used by the ADC in analog mode.
(#) Configure the voltage reference (internal or external).
(#) Set the offset and gain values.
(#) Reset the ADC DMA, define the DMA buffer, and start the DMA in the
proper transfer mode.
(#) Write the ADC configuration register to define the inputs, voltage
range, sample time and start the conversions.
@endverbatim
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32w108xx_adc.h"
/** @addtogroup STM32W108xx_StdPeriph_Driver
* @{
*/
/** @defgroup ADC
* @brief ADC driver modules
* @{
*/
/* External variables --------------------------------------------------------*/
/* Private typedef -----------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/* ADC INPUTN and INPUTP channel mask */
#define ADC_INPUT_NP_Reset ((uint16_t)0xF807)
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup ADC_Private_Functions
* @{
*/
/** @defgroup ADC_Group1 Initialization and Control functions
* @brief Initialization and Control functions
*
@verbatim
===============================================================================
##### Initialization and Control functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize and configure the ADC
(+) ADC Conversion Resolution (5bits --> 12bits)
(+) Enable or disable the ADC peripheral
@endverbatim
* @{
*/
/**
* @brief Deinitializes ADC peripheral registers to their default reset
* values.
* @param None
* @retval None
*/
void ADC_DeInit(void)
{
ADC->ISR = 0x0000001F;
ADC->IER = 0x00000000;
ADC->CR = 0x00001800;
ADC->OFFSETR = 0x00000000;
ADC->GAINR = 0x00008000;
ADC->DMACR = 0x00000010;
ADC->DMAMSAR = 0x20000000;
ADC->DMANDTR = 0x00000000;
}
/**
* @brief Initializes the ADC peripheral according to the specified
* parameters in the ADC_InitStruct.
* @param ADC_InitStruct: pointer to ADC_InitTypeDef structure
* that contains the configuration information for the ADC peripheral.
* @retval None
*/
void ADC_Init(ADC_InitTypeDef* ADC_InitStruct)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution));
assert_param(IS_ADC_VoltageP(ADC_InitStruct->ADC_VoltageP));
assert_param(IS_ADC_VoltageN(ADC_InitStruct->ADC_VoltageN));
assert_param(IS_ADC_CHANNEL(ADC_InitStruct->ADC_Input));
assert_param(IS_ADC_DMA_MODE(ADC_InitStruct->ADC_DMAMode));
assert_param(IS_ADC_CLOCK(ADC_InitStruct->ADC_Clock));
assert_param(IS_ADC_OFFSET(ADC_InitStruct->ADC_Offset));
assert_param(IS_ADC_GAIN(ADC_InitStruct->ADC_Gain));
/*---------------------------- ADC CR Configuration -----------------------*/
/* Configure ADC: scan conversion mode and resolution */
/* Set ADC_1MHZCLK bit according to ADC_Clock value */
/* Set ADC_MUX bits according to ADC_Input values */
/* Set ADC_HVSELN bit according to ADC_VoltageN value */
/* Set ADC_HVSELP bit according to ADC_VoltageP value */
/* Set ADC_PERIOD[0:2] bits according to ADC_Clock value */
tmpreg |= (uint32_t)(ADC_InitStruct->ADC_Resolution | ADC_InitStruct->ADC_VoltageP |
ADC_InitStruct->ADC_VoltageN | (uint32_t)((ADC_InitStruct->ADC_Input) << 0x3) |
ADC_InitStruct->ADC_Clock);
/* Write to ADC CR */
ADC->CR = (uint32_t)tmpreg;
/*---------------------------- ADC DMA Configuration -----------------------*/
/* Write to ADC DMA */
ADC->DMACR = (uint32_t)(ADC_InitStruct->ADC_DMAMode);
/*---------------------------- ADC ADC_OFFSETR Configuration ---------------*/
/* Write to ADC ADC_OFFSETR */
ADC->OFFSETR = (int32_t)(ADC_InitStruct->ADC_Offset);
/*---------------------------- ADC ADC_GAINR Configuration -----------------*/
/* Write to ADC ADC_GAINR */
ADC->GAINR = (uint32_t)(ADC_InitStruct->ADC_Gain);
}
/**
* @brief Fills each ADC_InitStruct member with its default value
* @param ADC_InitStruct: pointer to a ADC_InitTypeDef structure
* which will be initialized.
* @retval None
*/
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
{
/* Initialize the ADC resolution */
ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;
ADC_InitStruct->ADC_VoltageP = ADC_VoltageP_Low;
ADC_InitStruct->ADC_VoltageN = ADC_VoltageN_Low;
ADC_InitStruct->ADC_Input = ADC_SOURCE_VREF;
ADC_InitStruct->ADC_DMAMode = ADC_DMAMode_Linear;
ADC_InitStruct->ADC_Clock = ADC_Clock_6MHz;
ADC_InitStruct->ADC_Offset = 0;
ADC_InitStruct->ADC_Gain = 0x00008000;
}
/**
* @brief Enables or disables the specified ADC peripheral
* @param NewState: new state of the ADC peripheral.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void ADC_Cmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the ADC peripheral */
ADC->CR |= (uint32_t)ADC_CR_ADON;
}
else
{
/* Disable the ADC peripheral */
ADC->CR &= (uint32_t)(~ADC_CR_ADON);
}
}
/**
* @}
*/
/** @defgroup ADC_Group2 ADC channel Configuration functions
* @brief ADC channel Configuration functions
*
@verbatim
===============================================================================
##### ADC channel Configuration functions #####
===============================================================================
[..] This section provides function allowing to configure the ADC channels
@endverbatim
* @{
*/
/**
* @brief Selects the ADC channel
* @param ADC_Channels: specifies the ADC channel
* This parameter can be one of the following values:
* @arg ADC_SOURCE_ADC0_VREF2
* @arg ADC_SOURCE_ADC0_GND
* @arg ADC_SOURCE_ADC1_VREF2
* @arg ADC_SOURCE_ADC1_GND
* @arg ADC_SOURCE_ADC2_VREF2
* @arg ADC_SOURCE_ADC2_GND
* @arg ADC_SOURCE_ADC3_VREF2
* @arg ADC_SOURCE_ADC3_GND
* @arg ADC_SOURCE_ADC4_VREF2
* @arg ADC_SOURCE_ADC5_VREF2
* @arg ADC_SOURCE_ADC1_ADC0
* @arg ADC_SOURCE_ADC0_ADC1
* @arg ADC_SOURCE_ADC3_ADC2
* @arg ADC_SOURCE_ADC2_ADC3
* @arg ADC_SOURCE_ADC5_ADC4
* @arg ADC_SOURCE_GND_VREF2
* @arg ADC_SOURCE_VGND
* @arg ADC_SOURCE_VREF_VREF2
* @arg ADC_SOURCE_VREF
* @retval None
*/
void ADC_ChannelConfig(uint32_t ADC_Channels)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_ADC_CHANNEL(ADC_Channels));
/* Get the old register value */
tmpreg = ADC->CR;
/* Clear the old channels */
tmpreg &= ADC_INPUT_NP_Reset;
/* Set the new channels */
tmpreg |= (uint32_t)((ADC_Channels << 0x3));
/* Store the new register value */
ADC->CR = (uint32_t)tmpreg;
}
/**
* @}
*/
/** @defgroup ADC_Group3 DMA Configuration functions
* @brief DMA Configuration functions
*
@verbatim
===============================================================================
##### DMA Configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) initialize and configure the DMA
(+) reset and enable the DMA
@endverbatim
* @{
*/
/**
* @brief Selects the specified DMA configuration
* @param ADC_DMABeg: specifies the ADC buffer start address
* @param ADC_DMASize: specifies the ADC buffer size
* @retval None
*/
void ADC_DMA_Config(uint32_t ADC_DMABeg, uint32_t ADC_DMASize)
{
/* Check the parameters */
assert_param(IS_ADC_BEGIN(ADC_DMABeg));
assert_param(IS_ADC_SIZE(ADC_DMASize));
ADC->DMAMSAR = (uint32_t)ADC_DMABeg;
ADC->DMANDTR = (uint32_t)ADC_DMASize;
}
/**
* @brief Enables specified ADC DMA Channel
* @param None
* @retval None
*/
void ADC_DMA_ChannelLoadEnable(void)
{
/* Start the ADC DMA */
ADC->DMACR |= (uint32_t)ADC_DMACR_LOAD;
}
/**
* @brief Reset specified ADC DMA
* @param None
* @retval None
*/
void ADC_DMA_ChannelReset(void)
{
/* Reset the ADC DMA */
ADC->DMACR = (uint32_t)ADC_DMACR_RST;
}
/**
* @brief Gets the the location that will be written next by the DMA
* @param None
* @retval the current DMA address
*/
uint32_t ADC_DMA_GetNextAddress(void)
{
/*return the next address buffer*/
return (uint32_t) ADC->DMAMNAR;
}
/**
* @brief Gets the number of 16-bit conversion results that have been
* written to the buffer
* @param None
* @retval The number of conversions
*/
uint32_t ADC_DMA_GetCounter(void)
{
/*return the number of conversions*/
return (uint32_t) ADC->DMACNDTR;
}
/** @defgroup ADC_Group4 Interrupts and flags management functions
* @brief Interrupts and flags management functions
*
@verbatim
===============================================================================
##### Interrupts and flags management functions #####
===============================================================================
[..] This section provides functions allowing to :
(+) configure the ADC Interrupts and to get the status and clear flags
and Interrupts pending bits.
(+) get the status of DMA and clear flags
*** Flags and Interrupts for ADC ***
==============================================
[..]
(+)Flags :
(##) ADC_IT_DMABHF: DMA buffer half full interrupt pending
(##) ADC_IT_DMABF: DMA buffer full interrupt pending
(##) ADC_IT_SAT: Gain correction saturation interrupt pending
(##) ADC_IT_DMAOVF: DMA buffer overflow interrupt pending
(+)Interrupts :
(##) ADC_IT_DMABHF: DMA buffer half full interrupt enable
(##) ADC_IT_DMABF: DMA buffer full interrupt enable
(##) ADC_IT_SAT: Gain correction saturation interrupt enable
(##) ADC_IT_DMAOVF: DMA buffer overflow interrupt enable
*** Flags for ADC_DMA ***
==============================================
[..]
(+)Flags :
(##) ADC_FLAG_ACT: DMA active
(##) ADC_FLAG_OVF: DMA over flow
@endverbatim
* @{
*/
/**
* @brief Enables or disables the specified ADC interrupts
* @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled
* This parameter can be one of the following values:
* @arg ADC_IT_DMABHF: DMA buffer half full interrupt enable
* @arg ADC_IT_DMABF: DMA buffer full interrupt enable
* @arg ADC_IT_SAT: Gain correction saturation interrupt enable
* @arg ADC_IT_DMAOVF: DMA buffer overflow interrupt enable
* @param NewState: new state of the specified ADC interrupts
* This parameter can be: ENABLE or DISABLE
* @retval None
*/
void ADC_ITConfig(uint32_t ADC_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
assert_param(IS_ADC_IT(ADC_IT));
if (NewState != DISABLE)
{
/* Enable the selected ADC interrupts */
ADC->IER |= (uint32_t)ADC_IT;
}
else
{
/* Disable the selected ADC interrupts */
ADC->IER &= ~(uint32_t)ADC_IT;
}
}
/**
* @brief Checks whether the specified ADC interrupt has occurred or not
* @param ADC_DMA_FLAG: specifies the flag to check
* This parameter can be one of the following values:
* @arg ADC_FLAG_ACT: DMA active
* @arg ADC_FLAG_OVF: DMA over flow
* @retval The new state of ADC_DMA_FLAG (SET or RESET).
*/
FlagStatus ADC_DMA_GetFlagStatus(uint32_t ADC_DMA_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_ADC_DMA_FLAG(ADC_DMA_FLAG));
if ((ADC->ISR & ADC_DMA_FLAG) != RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/**
* @brief Checks whether the specified ADC pending interrupt has occurred or not
* @param ADC_IT: specifies the flag to check
* This parameter can be one of the following values:
* @arg ADC_IT_DMABHF: DMA buffer half full interrupt pending
* @arg ADC_IT_DMABF: DMA buffer full interrupt pending
* @arg ADC_IT_SAT: Gain correction saturation interrupt pending
* @arg ADC_IT_DMAOVF: DMA buffer overflow interrupt pending
* @retval The new state of ADC_IT (SET or RESET)
*/
ITStatus ADC_GetITStatus(uint32_t ADC_IT)
{
ITStatus bitstatus = RESET;
uint32_t enablestatus = 0;
/* Check the parameters */
assert_param(IS_ADC_IT(ADC_IT));
enablestatus = (uint32_t)(ADC->IER & ADC_IT);
if (((ADC->ISR & ADC_IT) != (uint32_t)RESET) && enablestatus)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/**
* @brief Clears the ADC interrupt pending bits
* @param ADC_IT: specifies the flag to clear
* This parameter can be one of the following values:
* @arg ADC_IT_DMABHF: DMA buffer half full interrupt pending
* @arg ADC_IT_DMABF: DMA buffer full interrupt pending
* @arg ADC_IT_SAT: Gain correction saturation interrupt pending
* @arg ADC_IT_DMAOVF: DMA buffer overflow interrupt pending
* @retval None
*/
void ADC_ClearITPendingBit(uint32_t ADC_IT)
{
/* Check the parameters */
assert_param(IS_ADC_IT(ADC_IT));
/* Clear the selected ADC flags */
ADC->ISR = (uint32_t)ADC_IT;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

557
libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_clk.c
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@ -1,557 +0,0 @@
/**
******************************************************************************
* @file stm32w108xx_clk.c
* @author MCD Application Team
* @version V1.0.1
* @date 30-November-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the clock peripheral:
* + Internal/external clocks,
* + Modes management
*
* @verbatim
*
===============================================================================
##### CLK specific features #####
===============================================================================
[..] After reset the device is running from OSCHF (12 MHz)
[..] Once the device started from reset, the user application has to:
(#) Configure the clock source to be used to drive the System clock
(#) Configure the System clock frequency: 24Mhz/12Mhz
(#) Configure the Flash clock frequency: 24Mhz/12Mhz/6Mhz
@endverbatim
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32w108xx_clk.h"
/** @addtogroup STM32W108xx_StdPeriph_Driver
* @{
*/
/** @defgroup CLK
* @brief CLK driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
#define SLOWRC_PERIOD_SETTLE_TIME 4250
#define SLOWRC_PERIOD_SAMPLES 8
#define CLK1K_NUMERATOR 384000000
#define FASTRC_PERIOD_SETTLE_TIME 128
/* CLK_HSECR2 register Mask */
#define CLK_HSECR2_Mask ((uint32_t)0x00000003)
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup CLK_Private_Functions
* @{
*/
/** @defgroup CLK_Group1 Internal and external clocks
* @brief Internal and external clocks configuration functions
*
@verbatim
===============================================================================
##### Internal-external clocks configuration functions #####
===============================================================================
[..] This section provides functions allowing to configure the internal/external clocks,
(#) HSI (high-frequency RC oscillator (OSCHF)), is used as the default system clock
source when power is applied to the core domain. The nominal frequency coming
out of reset is 12 MHz.
(#) HSE (high-frequency crystal oscillator), 24 MHz crystal oscillator
@endverbatim
* @{
*/
/**
* @brief Resets the CLOCK configuration to the default reset state.
* @note The default reset state of the clock configuration is given below:
* HSI ON and used as system clock source
* @param None
* @retval None
*/
void CLK_DeInit(void)
{
CLK->SLEEPCR = 0x00000002;
CLK->LSI10KCR = 0x00000000;
CLK->LSI1KCR = 0x00005000;
CLK->HSECR1 = 0x0000000F;
CLK->HSICR = 0x00000017;
CLK->PERIODCR = 0x00000000;
CLK->DITHERCR = 0x00000000;
CLK->HSECR2 = 0x00000000;
CLK->CPUCR = 0x00000000;
}
/**
* @brief Calibrate the low speed internal clock (LSI) to be close to 10KHZ in
* order to generate 1KHZ clock.
* @param None
* @retval None
*/
void CLK_InternalCalibrateLSI(void)
{
uint8_t i = 0;
uint32_t average = 0;
int16_t delta = 0;
uint32_t period = 0;
__IO uint32_t StartUpCounter = 0;
__IO uint32_t LSI10KCR_RESET = 0x0, LSI1KCR_RESET = 0x5000;
/* The slowest frequency for the 10kHz RC source is 8kHz (125us). The PERIODSR
register updates every 16 cycles, so to be safe 17 cycles = 2125us. But,
we need twice this maximum time because the period measurement runs
asynchronously, and the value of LSI10KCR is changed immediately before
the delay.
SLOWRC_PERIOD_SETTLE_TIME 4250
The CLK_PERIOD register measures the number of 12MHz clock cycles that
occur in 16 cycles of the SlowRC clock. This is meant to smooth out the the
noise inherently present in the analog RC source. While these 16 cycles
smooths out most noise, there is still some jitter in the bottom bits of
PERIODSR. To further smooth out the noise, we take several readings of
PERIODSR and average them out. Testing has shown that the bottom 3 and 4
bits of PERIODSR contain most of the jitter. Averaging 8 samples will
smooth out 3 bits of jitter and provide a realiable and stable reading useful
in the calculations, while taking much less time than 16 or 32 samples.
SLOWRC_PERIOD_SAMPLES 8
The register LSI1KCR is a fractional divider that divides the 10kHz analog
source with the goal of generating a 1024Hz, clk1k output.
10000Hz / LSI1KCR = 1024Hz.
Since the PERIODSR register measures the number of 12MHz cycles in 16
cycles of the RC:
16 * 12000000
------------- = ~10kHz
PERIODSR
and
~10kHz / 1024 = X
where X is the fractional number that belongs in LSI1KCR. Since the
integer portion of LSI1KCR is bits 15:11 and the fractional is 10:0,
multiplying X by 2048 (bit shift left by 11) generates the proper LSI1KCR
register value.
Putting this all together:
16 * 12000000 * 2048 384000000
-------------------- = ------------ = LSI1KCR
PERIODSR * 1024 PERIODSR
CLK1K_NUMERATOR 384000000 */
/* ---- STEP 1: coarsely tune SlowRC in analog section to ~10kHz ---- */
/* To operate properly across the full temperature and voltage range,
the RC source in the analog section needs to be first coarsely tuned
to 10kHz. The LSI10KCR register, which is 2's compliment, provides 16
steps at ~400Hz per step yielding approximate frequences of 8kHz at 7
and 15kHz at -8. */
/* Start with our reset values for TUNE and CAL */
CLK->PERIODCR = 0; /* measure SlowRC */
CLK->LSI10KCR = LSI10KCR_RESET;
CLK->LSI1KCR = LSI1KCR_RESET;
/* wait for the PERIODSR register to properly update */
do
{
StartUpCounter++;
} while(StartUpCounter != SLOWRC_PERIOD_SETTLE_TIME);
/* Measure the current PERIODSR to obtain a baseline
For 10kHz, the ideal PERIODSR value is 19200. Calculate the PERIOD delta.
It's possible for a chip's 10kHz source RC to be too far out of range
for the LSI10KCR to bring it back to 10kHz. Therefore, we have to
ensure that our delta correction does not exceed the tune range so
tune has to be capped to the end of the vailable range so it does not
wrap. Even if we cannot achieve 10kHz, the 1kHz calibration can still
properly correct to 1kHz.
Each LSI10KCR step yields a PERIODSR delta of *approximately* 800.
Calculate how many steps we are off. While dividing by 800 may seem
like an ugly calculation, the precision of the result is worth the small
bit of code and time needed to do a divide. */
period = CLK->PERIODSR;
/* Round to the nearest integer */
delta = (19200+400) - period;
delta /= 800;
/* LSI10KCR is a 4 bit signed number. cap the delta to 7/-8 */
if(delta > 7) {
delta = 7;
}
if(delta < -8) {
delta = -8;
}
CLK->LSI10KCR = delta;
/* Wait for PERIOD to update before taking another sample */
StartUpCounter = 0;
do
{
StartUpCounter++;
} while(StartUpCounter != SLOWRC_PERIOD_SETTLE_TIME);
/* The analog section should now be producing an output of ~10kHz */
/* ---- STEP 2: fine tune the SlowRC to 1024Hz ---- */
/* Our goal is to generate a 1024Hz source. The register LSI1KCR is a
fractional divider that divides the 10kHz analog source and generates
the clk1k output. At reset, the default value is 0x5000 which yields a
division of 10.000. By averaging several samples of CLK_PERIOD, we
can then calculate the proper divisor need for LSI1KCR to make 1024Hz. */
for(i=0;i<SLOWRC_PERIOD_SAMPLES;i++) {
StartUpCounter = 0;
do
{
StartUpCounter++;
} while(StartUpCounter != SLOWRC_PERIOD_SETTLE_TIME);
average += CLK->PERIODSR;
}
/* Calculate the average, with proper rounding */
average = (average+(SLOWRC_PERIOD_SAMPLES/2))/SLOWRC_PERIOD_SAMPLES;
/* Using an average period sample, calculate the clk1k divisor */
CLK->LSI1KCR = (uint16_t)(CLK1K_NUMERATOR/average);
/* The SlowRC timer is now producing a 1024Hz tick (+/-2Hz). */
}
/**
* @brief Calibrate the high speed internal clock (HSI) to be close to 12MHZ.
* @note To calibrate the HSI, the high speed external clock (HSE) must be the
* system clock.
* @param None
* @retval None
*/
void CLK_InternalCalibrateHSI(void)
{
__IO uint32_t StartUpCounter = 0, CLK_PERIOD = 0;
__IO int32_t newTune = -16;
/* ---- coarsely tune FastRC in analog section to ~12MHz ---- */
/* The slowest frequency for the FastRC source is 4MHz (250ns). The PERIODSR
register updates every 256 cycles, so to be safe 257 cycles = 64us. But,
we need twice this maximum time because the period measurement runs
asynchronously, and the value of HSICR1 is changed immediately before
the delay.
The CLK_PERIODSR register measures the number of 12MHz cycles in 256
cycles of OSCHF:
256 * 12000000
------------- = ~12MHz
CLK_PERIOD
The RC source in the analog section needs to be coarsely tuned
to 12MHz. The HSICR1 register, which is 2's compliment, provides 32
steps at ~0.5MHz per step yielding approximate frequences of 4MHz at 15
and 20MHz at -16. */
CLK->PERIODCR = 1; /* Measure FastRC */
/* Start at the fastest possible frequency */
CLK->HSICR = newTune;
/* Wait for the PERIOD register to properly update */
do
{
StartUpCounter++;
} while(StartUpCounter != FASTRC_PERIOD_SETTLE_TIME);
/* For 12MHz, the ideal CLK_PERIOD is 256. Tune the frequency down until
the period is <= 256, which says the frequency is as close to 12MHz as
possible (without going over 12MHz)
Start at the fastest possible frequency (-16) and increase to the slowest
possible (15). When CLK_PERIOD is <=256 or we run out of tune values,
we're done. */
for(;newTune<16;newTune++)
{
StartUpCounter = 0;
/* Decrease frequency by one step (by increasing tune value) */
CLK->HSICR = newTune;
/* Wait for the PERIOD register to properly update */
do
{
StartUpCounter++;
} while(StartUpCounter != FASTRC_PERIOD_SETTLE_TIME);
/* Kickout if we're tuned */
CLK_PERIOD = CLK->PERIODSR;
if(CLK_PERIOD >= 256) {
break;
}
}
/* The analog section should now be producing an output of 11.5MHz - 12.0MHz */
}
/**
* @brief Configures the clock mode to use:
* @param MODE: specifies the frequency mode to use.
* This parameter can be one of the following values:
* @arg MODE0: Normal CPU, SCLK =12MHZ, PCLK=6MHZ, Flash Program/Erase Inactive =6Mhz,
* FlashProgram/Erase Active = 12Mhz.
* @arg MODE1: Fast CPU, SCLK =12MHZ, PCLK=6MHZ, Flash Program/Erase Inactive =12Mhz,
* FlashProgram/Erase Active = 12Mhz.
* @arg MODE2: Normal CPU, SCLK =24MHZ, PCLK=12MHZ, Flash Program/Erase Inactive =12Mhz,
* FlashProgram/Erase Active = 12Mhz.
* @arg MODE3: Fast CPU, SCLK =24MHZ, PCLK=12MHZ, Flash Program/Erase Inactive =24Mhz,
* FlashProgram/Erase Active = 12Mhz.
* @retval None
*/
void CLK_Config(uint8_t MODE)
{
__IO uint32_t StartUpCounter = 0;
/* Check the parameters */
assert_param(IS_CLK_MODE(MODE));
switch (MODE)
{
case CLK_MODE0: /* HSI used as system clock : Normal CPU*/
CLK->HSECR2 &= ~CLK_HSECR2_SW1;
CLK->CPUCR &= ~CLK_CPUCR_SW2;
break;
case CLK_MODE1: /* HSI used as system clock : Fast CPU */
CLK->HSECR2 &= ~CLK_HSECR2_SW1;
CLK->CPUCR |= CLK_CPUCR_SW2;
break;
case CLK_MODE2: /* HSE used as system clock : Normal CPU*/
/* Enable HSE */
CLK->HSECR2 |= CLK_HSECR2_EN;
/* Wait till HSE is ready and if Time out is reached exit */
do
{
StartUpCounter++;
} while(StartUpCounter != HSE_STARTUP_TIMEOUT);
CLK->HSECR2 |= CLK_HSECR2_SW1;
CLK->CPUCR &= ~CLK_CPUCR_SW2;
break;
case CLK_MODE3: /* HSE used as system clock : Fast CPU*/
/* Enable HSE */
CLK->HSECR2 |= CLK_HSECR2_EN;
/* Wait till HSE is ready and if Time out is reached exit */
do
{
StartUpCounter++;
} while(StartUpCounter != HSE_STARTUP_TIMEOUT);
CLK->HSECR2 |= CLK_HSECR2_SW1;
CLK->CPUCR |= CLK_CPUCR_SW2;
break;
default: /* HSI used as system clock */
CLK->HSECR2 &= ~CLK_HSECR2_SW1;
CLK->CPUCR &= ~CLK_CPUCR_SW2;
break;
}
}
/**
* @brief Enables or disables the External High Speed oscillator (HSE).
* @note After enabling HSE the user should wait for HSE_STARTUP_TIMEOUT
* @note to be sure that the clok is stabilized.
* @param NewState: new state of the HSE.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void CLK_HSECmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
CLK->HSECR2 |= CLK_HSECR2_EN;
}
else
{
CLK->HSECR2 = 0x00;
}
}
/**
* @brief Enables or disables the specified SLPTIM clock.
* @param CLK_SLPTIM: specifies the SLPTIM clock to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg SLPTIM_CLK_32KH: 32kHz external XTAL
* @arg SLPTIM_CLK_10KH: 10kHz internal RC (during deep sleep)
* @param NewState: new state of the SLPTIM clock.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void CLK_SLPTIMClockConfig(uint32_t CLK_SLPTIM, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_SLPTIM_GET_CLK(CLK_SLPTIM));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
if (CLK_SLPTIM == SLPTIM_CLK_32KH)
{
CLK->SLEEPCR &= 0x0;
}
/* Enable the clock */
CLK->SLEEPCR |= (uint32_t)CLK_SLPTIM;
}
else
{
/* Disable the clock */
CLK->SLEEPCR &= (uint32_t)~CLK_SLPTIM;
}
}
/**
* @brief Calibration of CLK1K clock.
* @param CALINT: specifies the divider value integer portion.
* This parameter can be a value between 0x0 and 0x1F.
* @param CALFRAC: specifies the divider value fractional portion.
* This parameter can be a value between 0x0 and 0x7FF.
* @retval None.
*/
void CLK_1KClockCalibration(uint32_t CALINT, uint32_t CALFRAC)
{
uint32_t tmpclk1k;
/* Check the parameters */
assert_param(IS_LSI1KCRINT(CALINT));
assert_param(IS_LSI1KCRFRAC(CALFRAC));
CLK->LSI1KCR = 0x00000000;
/* set the divider value integer portion */
tmpclk1k = (uint32_t)(CALINT <<11);
/* set the divider value fractional portion */
tmpclk1k |= CALFRAC;
CLK->LSI1KCR = tmpclk1k;
}
/**
* @brief Set tune value for CLKRC clock.
* @param TUNE_VALUE: specifies the tune value for CLKRC clock.
* This parameter can be a value between 0x0 and 0xF.
* @retval None.
*/
void CLK_RCTuneConfig(uint32_t TUNE_VALUE)
{
/* Check the parameters */
assert_param(IS_CLK_TUNE_VALUE(TUNE_VALUE));
CLK->LSI10KCR = 0x00000000;
/* set the tune value for CLKRC */
CLK->LSI10KCR = TUNE_VALUE;
}
/**
* @brief Select the clock period to be measured.
* @param CLK_MEASURED: specifies the clock for which the period will be measured.
* This parameter can be :
* @arg MEASURE_CLKRC: Measure CLKRC.
* @arg MEASURE_OSCHF: Measure OSCHF.
* @arg MEASURE_TUNEFILT: Measure TUNE_FILTER_RESULT.
* @retval None.
*/
void CLK_MeasurePeriod(uint32_t CLK_MEASURED)
{
/* Check the parameters */
assert_param(IS_CLK_MEASURE(CLK_MEASURED));
CLK->PERIODCR = CLK_MEASURED;
}
/**
* @brief Returns the clock period measured depend on clock selected.
*@note measured period is equal to:
* 16 x Clock period in clk12m cycles (CLKRC/TUNE_FILTER_RESULT modes)
* 256 x clock period in clk12m cycles (OSCHF mode)
* @param None.
* @retval None.
*/
uint32_t CLK_GetMeasurePeriod(void)
{
return CLK->PERIODSR;
}
/**
* @brief Returns the clock source used as system clock.
* @param None
* @retval The clock source used as system clock. The returned value can
* be one of the following:
* - 0x00,0x01,0x10: HSI used as system clock
* - 0x03: HSE used as system clock
*/
uint32_t CLK_GetClocksFreq(void)
{
uint32_t tmp = 0;
uint32_t clockvalue = 0;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = CLK->HSECR2 & CLK_HSECR2_Mask;
switch (tmp)
{
case 0x00:
case 0x02: /* HSI used as system clock */
clockvalue = (uint32_t)HSI_VALUE;
break;
case 0x03: /* HSE used as system clock */
clockvalue = (uint32_t)HSE_VALUE;
break;
default: /* HSI used as system clock */
clockvalue = (uint32_t)HSI_VALUE;
break;
}
return clockvalue;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

238
libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_exti.c
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@ -1,238 +0,0 @@
/**
******************************************************************************
* @file stm32w108xx_exti.c
* @author MCD Application Team
* @version V1.0.1
* @date 30-November-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the EXTI peripheral:
* + Initialization and Configuration
* + Interrupts and flags management
*
* @verbatim
*
==============================================================================
##### EXTI features #####
==============================================================================
[..] External interrupt/event lines are mapped as following:
(#) All available GPIO pins are connected to the 4 external
interrupt/event lines from EXTIA to EXTID.
(#) EXTIA and EXTIB have fixed pins assignement (PB0 and PB6).
(#) EXTIC and EXTID can use any GPIO pin.
##### How to use this driver #####
==============================================================================
[..] In order to use an I/O pin as an external interrupt source, follow
steps below:
(#) Configure the I/O in input mode using GPIO_Init()
(#) Select the mode(interrupt, event) and configure the trigger selection
using EXTI_Init().
(#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init().
@endverbatim
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32w108xx_exti.h"
/** @addtogroup STM32W108xx_StdPeriph_Driver
* @{
*/
/** @defgroup EXTI
* @brief EXTI driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup EXTI_Private_Functions
* @{
*/
/** @defgroup EXTI_Group1 EXTI Initialization and Configuration
* @brief Initialization and Configuration of External Interrupt
*
@verbatim
===============================================================================
EXTI Initialization and Configuration
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Deinitializes the EXTI_IRQn line registers to their default reset values.
* @param None
* @retval None
*/
void EXTI_DeInit(void)
{
uint8_t i;
EXTI->PR = 0x00000000;
EXTI->CR[0] = 0x0000000F;
EXTI->CR[1] = 0x00000010;
for (i=0; i<4; i++)
{
EXTI->TSR[i] = 0x00000000;
}
}
/**
* @brief Initializes the EXTI peripheral according to the specified
* parameters in the EXTI_InitStruct.
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
* that contains the configuration information for the EXTI peripheral.
* @retval None
*/
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
{
/* Check the parameters */
assert_param(IS_EXTI_SOURCE(EXTI_InitStruct->EXTI_Source));
assert_param(IS_EXTI_IRQ(EXTI_InitStruct->EXTI_IRQn));
assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_DigitalFilterCmd));
if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
{
/* Clear Rising Falling edge configuration */
EXTI->TSR[(uint32_t)(EXTI_InitStruct->EXTI_IRQn & 0x000000F0) >>4] &= (uint32_t)(~EXTI_TSR_INTMOD);
/* Rising Falling edge */
EXTI->TSR[(uint32_t)(EXTI_InitStruct->EXTI_IRQn & 0x000000F0) >>4] |= (uint32_t)(EXTI_InitStruct->EXTI_Trigger);
}
else
{
EXTI->TSR[(uint32_t)(EXTI_InitStruct->EXTI_IRQn & 0x000000F0) >>4] &= (uint32_t)(~EXTI_TSR_INTMOD);
}
if (EXTI_InitStruct->EXTI_DigitalFilterCmd != DISABLE)
{
/* Set the EXTI_TSR_FILTEN bit to Enable degital filtering on the EXTI_IRQn */
EXTI->TSR[(uint32_t)(EXTI_InitStruct->EXTI_IRQn & 0x000000F0) >>4] |= (uint32_t)EXTI_TSR_FILTEN;
}
else
{
/* Clear the EXTI_TSR_FILTEN bit to disable degital filtering on the EXTI_IRQn */
EXTI->TSR[(uint32_t)(EXTI_InitStruct->EXTI_IRQn & 0x000000F0) >>4] &= (uint32_t)~EXTI_TSR_FILTEN;
}
/* Connect The EXTI_PinSource to the EXTI_IRQn handler */
if ((EXTI_InitStruct->EXTI_IRQn == EXTI_IRQC) || (EXTI_InitStruct->EXTI_IRQn == EXTI_IRQD))
{
EXTI->CR[(uint32_t)(EXTI_InitStruct->EXTI_IRQn & 0x0000000F)] &= 0x00000000;
EXTI->CR[(uint32_t)(EXTI_InitStruct->EXTI_IRQn & 0x0000000F)] |= (uint32_t)(EXTI_InitStruct->EXTI_Source);
}
else
{}
}
/**
* @brief Fills each EXTI_InitStruct member with its reset value.
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
* be initialized.
* @retval None
*/
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
{
EXTI_InitStruct->EXTI_Source = EXTI_SourcePB0;
EXTI_InitStruct->EXTI_IRQn = EXTI_IRQA;
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Disable;
EXTI_InitStruct->EXTI_LineCmd = DISABLE;
EXTI_InitStruct->EXTI_DigitalFilterCmd = DISABLE;
}
/** @defgroup EXTI_Group2 Interrupts and flags management functions
* @brief Interrupts and flags management functions
*
@verbatim
==============================================================================
##### Interrupts and flags management functions #####
==============================================================================
@endverbatim
* @{
*/
/**
* @brief Checks whether the specified EXTI line is asserted or not.
* @param EXTI_IRQn: specifies the EXTI line to check.
* This parameter can be:
* EXTI_IRQn: External interrupt line n where x(A, B, C or D).
* @retval The new state of EXTI_IRQn (SET or RESET).
*/
ITStatus EXTI_GetITStatus(uint32_t EXTI_IRQn)
{
ITStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_EXTI_IRQ(EXTI_IRQn));
if ((EXTI->PR & (uint32_t)(1<< ((uint32_t)(EXTI_IRQn & 0x000000F0) >>4))) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/**
* @brief Clears the EXTI's line pending bits.
* @param EXTI_IRQn: specifies the EXTI lines to clear.
* This parameter can be any combination of EXTI_IRQn where n can be (A, B, C or D).
* @retval None
*/
void EXTI_ClearITPendingBit(uint32_t EXTI_IRQn)
{
/* Check the parameters */
assert_param(IS_EXTI_IRQ(EXTI_IRQn));
EXTI->PR = (uint32_t)(1<< ((EXTI_IRQn & 0x000000F0) >>4));
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

925
libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_flash.c
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@ -1,925 +0,0 @@
/**
******************************************************************************
* @file stm32w108xx_flash.c
* @author MCD Application Team
* @version V1.0.1
* @date 30-November-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the FLASH peripheral:
* + FLASH Interface configuration
* + FLASH Memory Programming
* + Option Bytes Programming
* + Interrupts and flags management
*
* @verbatim
*
===============================================================================
##### How to use this driver #####
===============================================================================
[..] This driver provides functions to configure and program the Flash
memory of all STM32W108xx devices. These functions are split in 4 groups
(#) FLASH Interface configuration functions: this group includes the
management of following features:
(++) Set the latency
(++) Enable/Disable the prefetch buffer
(#) FLASH Memory Programming functions: this group includes all needed
functions to erase and program the main memory:
(++) Lock and Unlock the Flash interface.
(++) Erase function: Erase Page, erase all pages.
(++) Program functions: Half Word and Word write.
(#) FLASH Option Bytes Programming functions: this group includes all
needed functions to:
(++) Set/Reset the write protection
(++) Set the Read protection Level
(++) Get the Write protection
(++) Get the read protection status
(#) FLASH Interrupts and flag management functions: this group includes
all needed functions to:
(++) Enable/Disable the flash interrupt sources
(++) Get flags status
(++) Clear flags
(++) Get Flash operation status
(++) Wait for last flash operation
@endverbatim
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32w108xx_flash.h"
/** @addtogroup STM32W108xx_StdPeriph_Driver
* @{
*/
/** @defgroup FLASH
* @brief FLASH driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Flash Access Control Register bits */
#define ACR_LATENCY_Mask ((uint32_t)0x00000038)
#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7)
#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF)
/* Flash Access Control Register bits */
#define ACR_PRFTBS_Mask ((uint32_t)0x00000020)
/* Flash Control Register bits */
#define CR_PG_Set ((uint32_t)0x00000001)
#define CR_PG_Reset ((uint32_t)0x00001FFE)
#define CR_PER_Set ((uint32_t)0x00000002)
#define CR_PER_Reset ((uint32_t)0x00001FFD)
#define CR_MER_Set ((uint32_t)0x00000004)
#define CR_MER_Reset ((uint32_t)0x00001FFB)
#define CR_OPTPG_Set ((uint32_t)0x00000010)
#define CR_OPTPG_Reset ((uint32_t)0x00001FEF)
#define CR_OPTER_Set ((uint32_t)0x00000020)
#define CR_OPTER_Reset ((uint32_t)0x00001FDF)
#define CR_STRT_Set ((uint32_t)0x00000040)
#define CR_LOCK_Set ((uint32_t)0x00000080)
/* FLASH Mask */
#define RDPRT_Mask ((uint32_t)0x00000002)
#define WRP0_Mask ((uint32_t)0x000000FF)
#define WRP1_Mask ((uint32_t)0x0000FF00)
#define WRP2_Mask ((uint32_t)0x00FF0000)
#define WRP3_Mask ((uint32_t)0xFF000000)
/* FLASH Keys */
#define RDP_Key ((uint16_t)0x00A5)
#define FLASH_KEY1 ((uint32_t)0x45670123)
#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
/* Delay definition */
#define EraseTimeout ((uint32_t)0x000B0000)
#define ProgramTimeout ((uint32_t)0x00002000)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup FLASH_Private_Functions
* @{
*/
/**
@code
This driver provides functions to configure and program the Flash memory of all STM32W108xx devices.
STM32W108xx devices features only one bank with memory up to 256 Kbytes.
@endcode
*/
/** @defgroup FLASH_Group1 FLASH Interface configuration functions
* @brief FLASH Interface configuration functions
*
@verbatim
===============================================================================
##### FLASH Interface configuration functions #####
===============================================================================
[..] FLASH_Interface configuration_Functions, includes the following functions:
(+) void FLASH_SetLatency(uint32_t FLASH_Latency):
[..] To correctly read data from Flash memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock (SCLK)
(+) FlagStatus FLASH_GetPrefetchBufferStatus(void);
(+) void FLASH_PrefetchBufferCmd(FunctionalState NewState);
[..]
All these functions don't need the unlock sequence.
@endverbatim
* @{
*/
/**
* @brief Sets the code latency value.
* @param FLASH_Latency: specifies the FLASH Latency value.
* This parameter can be one of the following values:
* @arg FLASH_Latency_0: FLASH Zero Latency cycle
* @arg FLASH_Latency_1: FLASH One Latency cycle
* @arg FLASH_Latency_2: FLASH Two Latency cycles
* @retval None
*/
void FLASH_SetLatency(uint32_t FLASH_Latency)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_FLASH_LATENCY(FLASH_Latency));
/* Read the ACR register */
tmpreg = FLASH->ACR;
/* Sets the Latency value */
tmpreg &= ACR_LATENCY_Mask;
tmpreg |= FLASH_Latency;
/* Write the ACR register */
FLASH->ACR = tmpreg;
}
/**
* @brief Checks whether the FLASH Prefetch Buffer status is set or not.
* @param None
* @retval FLASH Prefetch Buffer Status (SET or RESET).
*/
FlagStatus FLASH_GetPrefetchBufferStatus(void)
{
FlagStatus bitstatus = RESET;
if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
/* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */
return bitstatus;
}
/**
* @brief Enables or disables the Prefetch Buffer.
* @param FLASH_PrefetchBuffer: specifies the Prefetch buffer status.
* This parameter can be one of the following values:
* @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable
* @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable
* @retval None
*/
void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer)
{
/* Check the parameters */
assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer));
/* Enable or disable the Prefetch Buffer */
FLASH->ACR &= ACR_PRFTBE_Mask;
FLASH->ACR |= FLASH_PrefetchBuffer;
}
/**
* @}
*/
/** @defgroup FLASH_Group2 FLASH Memory Programming functions
* @brief FLASH Memory Programming functions
*
@verbatim
===============================================================================
##### FLASH Memory Programming functions #####
===============================================================================
[..] The FLASH Memory Programming functions, includes the following functions:
(+) void FPEC_ClockCmd(FunctionalState NewState)
(+) void FLASH_Unlock(void);
(+) void FLASH_Lock(void);
(+) void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess)
(+) FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
(+) FLASH_Status FLASH_EraseAllPages(void);
(+) FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
(+) FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
[..] Any operation of erase or program should follow these steps:
(#) Call the FPEC_ClockCmd() function to enable/disable the flash control
register and enable/disable flash clock.
(#) Call the desired function to erase page or program data.
@endverbatim
* @{
*/
/**
* @brief Enables or disables the FPEC clock.
* @param NewState: new state of the FPEC clock.
* This parameter can be: ENABLE or DISABLE.
* @retval None.
*/
void FPEC_ClockCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Unlock the FPEC */
FLASH->KEYR = FLASH_KEY1;
FLASH->KEYR = FLASH_KEY2;
/* Unlock the Option bytes write enable (OPTWRE) */
FLASH->OPTKEYR = FLASH_KEY1;
FLASH->OPTKEYR = FLASH_KEY2;
/* Enable the FPEC Clock */
FLASH->CLKER |= (uint32_t)FLASH_CLKER_EN;
/* Verifying that the FPEC clock is running before proceeding */
while( (FLASH->CLKSR&FLASH_CLKSR_ACK) != FLASH_CLKSR_ACK)
{}
/* Wait until the flash is no longer busy */
while( (FLASH->SR&FLASH_SR_BSY) == (uint32_t)FLASH_SR_BSY )
{}
}
else
{
/* Verifying the FPEC is completely idle before turning off the clock */
while( (FLASH->CLKSR&FLASH_CLKSR_BSY) == FLASH_CLKSR_BSY)
{}
/* Disable the FPEC Clock */
FLASH->CLKER &= (uint32_t)~FLASH_CLKER_EN;
/* Set the Lock Bit to lock the FPEC and the CR of flash */
FLASH->CR |= (uint32_t)FLASH_CR_LOCK;
}
}
/**
* @brief Unlocks the FLASH Program Erase Controller.
* @param None
* @retval None
*/
void FLASH_Unlock(void)
{
/* Unlock the FPEC */
FLASH->KEYR = FLASH_KEY1;
FLASH->KEYR = FLASH_KEY2;
}
/**
* @brief Locks the FLASH Program Erase Controller.
* @param None
* @retval None
*/
void FLASH_Lock(void)
{
/* Set the Lock Bit to lock the FPEC and the CR of flash */
FLASH->CR |= CR_LOCK_Set;
}
/**
* @brief Enables or disables the Half cycle flash access.
* @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode.
* This parameter can be one of the following values:
* @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable
* @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable
* @retval None
*/
void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess)
{
/* Check the parameters */
assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess));
/* Enable or disable the Half cycle access */
FLASH->ACR &= ACR_HLFCYA_Mask;
FLASH->ACR |= FLASH_HalfCycleAccess;
}
/**
* @brief Erases a specified FLASH page.
* @param Page_Address: The page address to be erased.
* @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
{
FLASH_Status status = FLASH_COMPLETE;
/* Check the parameters */
assert_param(IS_FLASH_ADDRESS(Page_Address));
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(EraseTimeout);
if(status == FLASH_COMPLETE)
{
/* if the previous operation is completed, proceed to erase the page */
FLASH->CR|= CR_PER_Set;
FLASH->AR = Page_Address;
FLASH->CR|= CR_STRT_Set;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(EraseTimeout);
/* Disable the PER Bit */
FLASH->CR &= CR_PER_Reset;
}
/* Return the Erase Status */
return status;
}
/**
* @brief Erases all FLASH pages.
* @param None
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_EraseAllPages(void)
{
FLASH_Status status = FLASH_COMPLETE;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(EraseTimeout);
if(status == FLASH_COMPLETE)
{
/* if the previous operation is completed, proceed to erase all pages */
FLASH->CR |= CR_MER_Set;
FLASH->CR |= CR_STRT_Set;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(EraseTimeout);
/* Disable the MER Bit */
FLASH->CR &= CR_MER_Reset;
}
/* Return the Erase Status */
return status;
}
/**
* @brief Programs a word at a specified address.
* @param Address: specifies the address to be programmed.
* @param Data: specifies the data to be programmed.
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
{
FLASH_Status status = FLASH_COMPLETE;
__IO uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_FLASH_ADDRESS(Address));
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status == FLASH_COMPLETE)
{
/* if the previous operation is completed, proceed to program the new first
half word */
FLASH->CR |= CR_PG_Set;
*(__IO uint16_t*)Address = (uint16_t)Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status == FLASH_COMPLETE)
{
/* if the previous operation is completed, proceed to program the new second
half word */
tmp = Address + 2;
*(__IO uint16_t*) tmp = Data >> 16;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
/* Disable the PG Bit */
FLASH->CR &= CR_PG_Reset;
}
else
{
/* Disable the PG Bit */
FLASH->CR &= CR_PG_Reset;
}
}
/* Return the Program Status */
return status;
}
/**
* @brief Programs a half word at a specified address.
* @param Address: specifies the address to be programmed.
* @param Data: specifies the data to be programmed.
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
{
FLASH_Status status = FLASH_COMPLETE;
/* Check the parameters */
assert_param(IS_FLASH_ADDRESS(Address));
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status == FLASH_COMPLETE)
{
/* if the previous operation is completed, proceed to program the new data */
FLASH->CR |= CR_PG_Set;
*(__IO uint16_t*)Address = Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
/* Disable the PG Bit */
FLASH->CR &= CR_PG_Reset;
}
/* Return the Program Status */
return status;
}
/**
* @}
*/
/** @defgroup FLASH_Group3 Option Bytes Programming functions
* @brief Option Bytes Programming functions
*
@verbatim
===============================================================================
##### Option Bytes Programming functions #####
===============================================================================
[..] The FLASH_Option Bytes Programming_functions, includes the following functions:
(+) FLASH_Status FLASH_EraseOptionBytes(void);
(+) FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);
(+) FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
(+) uint32_t FLASH_GetWriteProtectionOptionByte(void);
(+) FlagStatus FLASH_GetReadOutProtectionStatus(void);
@endverbatim
* @{
*/
/**
* @brief Erases the FLASH option bytes.
* @note This functions erases all option bytes except the Read protection (RDP).
* @param None
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_EraseOptionBytes(void)
{
uint16_t rdptmp = RDP_Key;
FLASH_Status status = FLASH_COMPLETE;
/* Get the actual read protection Option Byte value */
if(FLASH_GetReadOutProtectionStatus() != RESET)
{
rdptmp = 0x00;
}
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(EraseTimeout);
if(status == FLASH_COMPLETE)
{
/* Authorize the small information block programming */
FLASH->OPTKEYR = FLASH_KEY1;
FLASH->OPTKEYR = FLASH_KEY2;
/* if the previous operation is completed, proceed to erase the option bytes */
FLASH->CR |= CR_OPTER_Set;
FLASH->CR |= CR_STRT_Set;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(EraseTimeout);
if(status == FLASH_COMPLETE)
{
/* if the erase operation is completed, disable the OPTER Bit */
FLASH->CR &= CR_OPTER_Reset;
/* Enable the Option Bytes Programming operation */
FLASH->CR |= CR_OPTPG_Set;
/* Restore the last read protection Option Byte value */
OB->RDP = (uint16_t)rdptmp;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status != FLASH_TIMEOUT)
{
/* if the program operation is completed, disable the OPTPG Bit */
FLASH->CR &= CR_OPTPG_Reset;
}
}
else
{
if (status != FLASH_TIMEOUT)
{
/* Disable the OPTPG Bit */
FLASH->CR &= CR_OPTPG_Reset;
}
}
}
/* Return the erase status */
return status;
}
/**
* @brief Write protects the desired pages
* @param FLASH_Pages: specifies the address of the pages to be write protected.
* This parameter can be:
* @arg For @b STM32W_Low-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages60to63.
* @arg For @b STM32W_Medium-density_devices: value between FLASH_WRProt_Pages0to3
* and FLASH_WRProt_Pages124to127.
* @arg For @b STM32W_High-density_devices: value between FLASH_WRProt_Pages0to1 and
* FLASH_WRProt_Pages126to127.
* @arg For @b STM32W_Connectivity_line_devices: value between FLASH_WRProt_Pages0to1 and
* FLASH_WRProt_Pages94to95.
* @arg FLASH_WRProt_AllPages
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages)
{
uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
FLASH_Status status = FLASH_COMPLETE;
/* Check the parameters */
assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages));
FLASH_Pages = (uint32_t)(~FLASH_Pages);
WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask);
WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8);
WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16);
WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24);
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status == FLASH_COMPLETE)
{
/* Authorizes the small information block programming */
FLASH->OPTKEYR = FLASH_KEY1;
FLASH->OPTKEYR = FLASH_KEY2;
FLASH->CR |= CR_OPTPG_Set;
if(WRP0_Data != 0xFF)
{
OB->WRP0 = WRP0_Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
}
if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))
{
OB->WRP1 = WRP1_Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
}
if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF))
{
OB->WRP2 = WRP2_Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
}
if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF))
{
OB->WRP3 = WRP3_Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
}
if(status != FLASH_TIMEOUT)
{
/* if the program operation is completed, disable the OPTPG Bit */
FLASH->CR &= CR_OPTPG_Reset;
}
}
/* Return the write protection operation Status */
return status;
}
/**
* @brief Enables or disables the read out protection.
* @param NewState : new state of the ReadOut Protection.
* This parameter can be: ENABLE or DISABLE.
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState)
{
FLASH_Status status = FLASH_COMPLETE;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
status = FLASH_WaitForLastOperation(EraseTimeout);
if(status == FLASH_COMPLETE)
{
/* Authorizes the small information block programming */
FLASH->OPTKEYR = FLASH_KEY1;
FLASH->OPTKEYR = FLASH_KEY2;
FLASH->CR |= CR_OPTER_Set;
FLASH->CR |= CR_STRT_Set;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(EraseTimeout);
if(status == FLASH_COMPLETE)
{
/* if the erase operation is completed, disable the OPTER Bit */
FLASH->CR &= CR_OPTER_Reset;
/* Enable the Option Bytes Programming operation */
FLASH->CR |= CR_OPTPG_Set;
if(NewState != DISABLE)
{
OB->RDP = 0x00;
}
else
{
OB->RDP = RDP_Key;
}
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(EraseTimeout);
if(status != FLASH_TIMEOUT)
{
/* if the program operation is completed, disable the OPTPG Bit */
FLASH->CR &= CR_OPTPG_Reset;
}
}
else
{
if(status != FLASH_TIMEOUT)
{
/* Disable the OPTER Bit */
FLASH->CR &= CR_OPTER_Reset;
}
}
}
/* Return the protection operation Status */
return status;
}
/**
* @brief Returns the FLASH Write Protection Option Bytes Register value.
* @param None
* @retval The FLASH Write Protection Option Bytes Register value
*/
uint32_t FLASH_GetWriteProtectionOptionByte(void)
{
/* Return the Flash write protection Register value */
return (uint32_t)(FLASH->WRPR);
}
/**
* @brief Checks whether the FLASH Read Out Protection Status is set or not.
* @param None
* @retval FLASH ReadOut Protection Status(SET or RESET)
*/
FlagStatus FLASH_GetReadOutProtectionStatus(void)
{
FlagStatus readoutstatus = RESET;
if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET)
{
readoutstatus = SET;
}
else
{
readoutstatus = RESET;
}
return readoutstatus;
}
/**
* @}
*/
/** @defgroup FLASH_Group4 Interrupts and flags management functions
* @brief Interrupts and flags management functions
*
@verbatim
===============================================================================
##### Interrupts and flags management functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables or disables the specified FLASH interrupts.
* @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg FLASH_IT_ERROR: FLASH Error Interrupt
* @arg FLASH_IT_EOP: FLASH end of operation Interrupt
* @param NewState: new state of the specified Flash interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FLASH_IT(FLASH_IT));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if(NewState != DISABLE)
{
/* Enable the interrupt sources */
FLASH->CR |= FLASH_IT;
}
else
{
/* Disable the interrupt sources */
FLASH->CR &= ~(uint32_t)FLASH_IT;
}
}
/**
* @brief Checks whether the specified FLASH flag is set or not.
* @param FLASH_FLAG: specifies the FLASH flag to check.
* This parameter can be one of the following values:
* @arg FLASH_FLAG_BSY: FLASH Busy flag
* @arg FLASH_FLAG_PGERR: FLASH Program error flag
* @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
* @arg FLASH_FLAG_EOP: FLASH End of Operation flag
* @arg FLASH_FLAG_OPTERR: FLASH Option Byte error flag
* @retval The new state of FLASH_FLAG (SET or RESET).
*/
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;
if(FLASH_FLAG == FLASH_FLAG_OPTERR)
{
if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
}
else
{
if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
}
/* Return the new state of FLASH_FLAG (SET or RESET) */
return bitstatus;
}
/**
* @brief Clears the FLASH's pending flags.
* @param FLASH_FLAG: specifies the FLASH flags to clear.
* This parameter can be any combination of the following values:
* @arg FLASH_FLAG_PGERR: FLASH Program error flag
* @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
* @arg FLASH_FLAG_EOP: FLASH End of Operation flag
* @retval None
*/
void FLASH_ClearFlag(uint32_t FLASH_FLAG)
{
/* Check the parameters */
assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;
/* Clear the flags */
FLASH->SR = FLASH_FLAG;
}
/**
* @brief Returns the FLASH Status.
* @param None
* @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP or FLASH_COMPLETE
*/
FLASH_Status FLASH_GetStatus(void)
{
FLASH_Status flashstatus = FLASH_COMPLETE;
if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
{
flashstatus = FLASH_BUSY;
}
else
{
if((FLASH->SR & FLASH_FLAG_PGERR) != 0)
{
flashstatus = FLASH_ERROR_PG;
}
else
{
if((FLASH->SR & FLASH_FLAG_WRPRTERR) != 0 )
{
flashstatus = FLASH_ERROR_WRP;
}
else
{
flashstatus = FLASH_COMPLETE;
}
}
}
/* Return the Flash Status */
return flashstatus;
}
/**
* @brief Waits for a Flash operation to complete or a TIMEOUT to occur.
* @param Timeout: FLASH programming Timeout
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
{
FLASH_Status status = FLASH_COMPLETE;
/* Check for the Flash Status */
status = FLASH_GetStatus();
/* Wait for a Flash operation to complete or a TIMEOUT to occur */
while((status == FLASH_BUSY) && (Timeout != 0x00))
{
status = FLASH_GetStatus();
Timeout--;
}
if(Timeout == 0x00 )
{
status = FLASH_TIMEOUT;
}
/* Return the operation status */
return status;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

504
libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_gpio.c
View File

@ -1,504 +0,0 @@
/**
******************************************************************************
* @file stm32w108xx_gpio.c
* @author MCD Application Team
* @version V1.0.1
* @date 30-November-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the GPIO peripheral:
* + Initialization and Configuration
* + GPIO Read and Write
* @verbatim
*
================================================================================
##### How to use this driver #####
================================================================================
[..]
(#) Configure the GPIO pin(s) using GPIO_Init().
Four possible configuration are available for each pin:
(++) Input: Floating, Pull-up, Pull-down.
(++) Output: Push-Pull (Pull-up, Pull-down or no Pull)
Open Drain (Pull-up, Pull-down or no Pull).
(++) Alternate Function: Push-Pull (PP or SPI mode)
Open Drain (Pull-up, Pull-down or no Pull).
(++) Analog
(#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
(#) To set/reset the level of a pin configured in output mode use
GPIO_SetBits()/GPIO_ResetBits()
(#) During and just after reset, the alternate functions are not active and
the GPIO pins are configured in input floating mode (except JTAG pins).
(#) A full chip reset affects the GPIO configuration as follows:
(++) All pins are configured as floating inputs.
(++) The GPIO_EXTREGEN bit is set which overrides the normal configuration for PA7.
(++) The GPIO_DBGDIS bit is cleared, allowing Serial Wire/JTAG access
to override the normal configuration of PC0, PC2, PC3, and PC4.
@endverbatim
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32w108xx_gpio.h"
/** @addtogroup STM32W108xx_StdPeriph_Driver
* @{
*/
/** @defgroup GPIO
* @brief GPIO driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup GPIO_Private_Functions
* @{
*/
/** @defgroup GPIO_Group1 Initialization and Configuration
* @brief Initialization and Configuration
*
@verbatim
===============================================================================
Initialization and Configuration
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Deinitializes the GPIOx peripheral registers to their default reset values.
* @param GPIOx: where x can be (A..C) to select the GPIO peripheral.
* @retval None
*/
void GPIO_DeInit(GPIO_TypeDef* GPIOx)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
GPIOx->CRL = 0x00004444;
GPIOx->CRH = 0x00004444;
GPIOx->IDR = 0x00000000;
GPIOx->ODR = 0x00000000;
GPIOx->BSR = 0x00000000;
GPIOx->BRR = 0x00000000;
GPIO_DBG->PCTRACECR = 0x00000000;
GPIO_DBG->DBGCR = 0x00000010;
}
/**
* @brief Initializes the GPIOx peripheral according to the specified
* parameters in the GPIO_InitStruct.
* @param GPIOx: where x can be (A, B or C) to select the GPIO peripheral.
* @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
* contains the configuration information for the specified GPIO
* peripheral.
* GPIO_Pin: selects the pin to be configured: GPIO_Pin_0 -> GPIO_Pin_7
* GPIO_Mode: selects the mode of the pin:
* - GPIO Analog Mode: GPIO_Mode_AN
* - GPIO Output Mode PP: GPIO_Mode_OUT_PP
* - GPIO Input Mode NOPULL: GPIO_Mode_IN
* - GPIO Output Mode OD: GPIO_Mode_OUT_OD
* - GPIO Input Mode PuPd: GPIO_Mode_IN_PUD
* - GPIO Alternate function Mode PP: GPIO_Mode_AF_PP
* - GPIO Alternate function Mode SPI SCLK PP: GPIO_Mode_AF_PP_SPI
* - GPIO Alternate function Mode OD: GPIO_Mode_AF_OD
* @retval None
*/
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
{
uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
uint32_t tmpreg = 0x00, pinmask = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
/*---------------------------- GPIO Mode Configuration -----------------------*/
currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
/*---------------------------- GPIO CRL Configuration ------------------------*/
/* Configure the four low port pins */
if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x0F)) != 0x00)
{
tmpreg = GPIOx->CRL;
for (pinpos = 0x00; pinpos < 0x04; pinpos++)
{
pos = ((uint32_t)0x01) << pinpos;
/* Get the port pins position */
currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
if (currentpin == pos)
{
pos = pinpos << 2;
/* Clear the corresponding low control register bits */
pinmask = ((uint32_t)0x0F) << pos;
tmpreg &= ~pinmask;
/* Write the mode configuration in the corresponding bits */
tmpreg |= (currentmode << pos);
}
}
GPIOx->CRL = tmpreg;
}
/*---------------------------- GPIO CRH Configuration ------------------------*/
/* Configure the four high port pins */
if (GPIO_InitStruct->GPIO_Pin > 0x0F)
{
tmpreg = GPIOx->CRH;
for (pinpos = 0x00; pinpos < 0x04; pinpos++)
{
pos = (((uint32_t)0x01) << (pinpos + 0x04));
/* Get the port pins position */
currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
if (currentpin == pos)
{
pos = pinpos << 2;
/* Clear the corresponding high control register bits */
pinmask = ((uint32_t)0x0F) << pos;
tmpreg &= ~pinmask;
/* Write the mode configuration in the corresponding bits */
tmpreg |= (currentmode << pos);
}
}
GPIOx->CRH = tmpreg;
}
}
/**
* @brief Fills each GPIO_InitStruct member with its default value.
* @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will
* be initialized.
* @retval None
*/
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
{
/* Reset GPIO init structure parameters values */
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
}
/**
* @}
*/
/** @defgroup GPIO_Group2 GPIO Read and Write
* @brief GPIO Read and Write
*
@verbatim
===============================================================================
GPIO Read and Write
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Reads the specified input port pin.
* @param GPIOx: where x can be (A, B or C) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_Pin_x where x can be (0..7).
* @retval The input port pin value.
*/
uint32_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin)
{
uint32_t bitstatus = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
{
bitstatus = (uint32_t)Bit_SET;
}
else
{
bitstatus = (uint32_t)Bit_RESET;
}
return bitstatus;
}
/**
* @brief Reads the specified GPIO input data port.
* @param GPIOx: where x can be (A..C) to select the GPIO peripheral.
* @retval GPIO input data port value.
*/
uint32_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
return ((uint32_t)GPIOx->IDR);
}
/**
* @brief Reads the specified output data port bit.
* @param GPIOx: where x can be (A, B or C) to select the GPIO peripheral.
* @param GPIO_Pin: Specifies the port bit to read.
* This parameter can be GPIO_Pin_x where x can be (0..7).
* @retval The output port pin value.
*/
uint32_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin)
{
uint32_t bitstatus = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
{
bitstatus = (uint32_t)Bit_SET;
}
else
{
bitstatus = (uint32_t)Bit_RESET;
}
return bitstatus;
}
/**
* @brief Reads the specified GPIO output data port.
* @param GPIOx: where x can be (A, B or C) to select the GPIO peripheral.
* @retval GPIO output data port value.
*/
uint32_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
return ((uint32_t)GPIOx->ODR);
}
/**
* @brief Sets the selected data port bits.
* @param GPIOx: where x can be (A, B or C) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bits to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..7).
* @note This functions uses GPIOx_SET register to allow atomic read/modify
* accesses. In this way, there is no risk of an IRQ occurring between
* the read and the modify access.
* @retval None
*/
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
GPIOx->BSR = GPIO_Pin;
}
/**
* @brief Clears the selected data port bits.
* @param GPIOx: where x can be (A, B or C) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bits to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..7).
* @note This functions uses GPIOx_CLR register to allow atomic read/modify
* accesses. In this way, there is no risk of an IRQ occurring between
* the read and the modify access.
* @retval None
*/
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
GPIOx->BRR = GPIO_Pin;
}
/**
* @brief Sets or clears the selected data port bit.
* @param GPIOx: where x can be (A, B or C) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be one of GPIO_Pin_x where x can be (0..7).
* @param BitVal: specifies the value to be written to the selected bit.
* This parameter can be one of the BitAction enum values:
* @arg Bit_RESET: to clear the port pin
* @arg Bit_SET: to set the port pin
* @retval None
*/
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin, BitAction BitVal)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_BIT_ACTION(BitVal));
if (BitVal != Bit_RESET)
{
GPIOx->BSR = GPIO_Pin;
}
else
{
GPIOx->BRR = GPIO_Pin ;
}
}
/**
* @brief Writes data to the specified GPIO data port.
* @param GPIOx: where x can be (A, B or C) to select the GPIO peripheral.
* @param PortVal: specifies the value to be written to the port output data
* register.
* @retval None
*/
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
GPIOx->ODR = PortVal;
}
/**
* @}
*/
/** @defgroup GPIO_Group3 GPIO Wake and Debug Configuration
* @brief GPIO Wake and Debug Configuration
*
@verbatim
===============================================================================
Debug Configuration
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Selects PC_TRACE source on bb_debug GPIO pins.
* @param PCTRACE_SEL: specifies the PC_TRACE source on bb_debug GPIO pins.
* This parameter can be :
* @arg GPIO_BBDEBUG: bb debug.
* @arg GPIO_PCTRACE: pc trace.
* @retval None.
*/
void GPIO_PCTraceConfig(uint32_t PCTRACE_SEL)
{
/* Check the parameters */
assert_param(IS_GPIO_PCTRACE(PCTRACE_SEL));
GPIO_DBG->PCTRACECR = PCTRACE_SEL;
}
/**
* @brief Enables or disables the debug interface.
* @param NewState: new state of the debug interface.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void GPIO_DebugInterfaceCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Clear the DEBUGDIS bit to Enable the debug interface */
GPIO_DBG->DBGCR &= (uint32_t)~GPIO_DBGCR_DBGDIS;
}
else
{
/* Set the DEBUGDIS bit to Disable the debug interface */
GPIO_DBG->DBGCR |= (uint32_t)GPIO_DBGCR_DBGDIS;
}
}
/**
* @brief Enables or Disable REG_EN override of PA7's normal GPIO configuration.
* @param NewState: new state of the REG_EN.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void GPIO_ExternalOverrideCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Clear the GPIO_EXTREGEN bit to Enable the debug interface */
GPIO_DBG->DBGCR &= (uint32_t)~GPIO_DBGCR_EXTREGEN;
}
else
{
/* Set the GPIO_EXTREGEN bit to Disable the debug interface */
GPIO_DBG->DBGCR |= (uint32_t)GPIO_DBGCR_EXTREGEN;
}
}
/**
* @brief Checks whether the specified GPIO debug flag is set or not.
* @param GPIO_DBGFLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg GPIO_DBGSR_SWEN: Serial Wire interface flag
* @arg GPIO_DBGSR_FORCEDBG: Debugger interface flag
* @arg GPIO_DBGSR_BOOTMODE: nBOOTMODE signal sampled at the end of reset flag
* @retval The new state of GPIO_DBGFLAG (SET or RESET).
*/
FlagStatus GPIO_GetDebugFlagStatus(uint16_t GPIO_DBGFLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_GPIO_GET_DBGFLAG(GPIO_DBGFLAG));
/* Check the status of the specified GPIO debug flag */
if ((GPIO_DBG->DBGSR & GPIO_DBGFLAG) != (uint32_t)RESET)
{
/* GPIO_DBGFLAG is set */
bitstatus = SET;
}
else
{
/* GPIO_DBGFLAG is reset */
bitstatus = RESET;
}
/* Return the GPIO_DBGFLAG status */
return bitstatus;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

229
libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_misc.c
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@ -1,229 +0,0 @@
/**
******************************************************************************
* @file stm32w108xx_misc.c
* @author MCD Application Team
* @version V1.0.1
* @date 30-November-2012
* @brief This file provides all the miscellaneous firmware functions (add-on
* to CMSIS functions).
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32w108xx_misc.h"
/** @addtogroup STM32W108xx_StdPeriph_Driver
* @{
*/
/** @defgroup MISC
* @brief MISC driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup MISC_Private_Functions
* @{
*/
/**
*
@verbatim
*******************************************************************************
##### Interrupts configuration functions #####
*******************************************************************************
[..] This section provide functions allowing to configure the NVIC interrupts
(IRQ).The Cortex-M3 exceptions are managed by CMSIS functions.
(#) Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig()
function according to the following table.
The table below gives the allowed values of the preemption priority
and subpriority according to the Priority Grouping configuration
performed by NVIC_PriorityGroupConfig function.
============================================================================================================================
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
============================================================================================================================
NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for preemption priority
| | | 4 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for preemption priority
| | | 3 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for preemption priority
| | | 2 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for preemption priority
| | | 1 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for preemption priority
| | | 0 bits for subpriority
============================================================================================================================
(#) Enable and Configure the priority of the selected IRQ Channels.
-@- When the NVIC_PriorityGroup_0 is selected, it will no any nested interrupt,
the IRQ priority will be managed only by subpriority.
The sub-priority is only used to sort pending exception priorities,
and does not affect active exceptions.
-@- Lower priority values gives higher priority.
-@- Priority Order:
(#@) Lowest Preemption priority.
(#@) Lowest Subpriority.
(#@) Lowest hardware priority (IRQn position).
@endverbatim
*/
/**
* @brief Configures the priority grouping: preemption priority and subpriority.
* @param NVIC_PriorityGroup: specifies the priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PriorityGroup_0: 0 bits for preemption priority
* 4 bits for subpriority.
* @note When NVIC_PriorityGroup_0 is selected, it will no be any nested
* interrupt. This interrupts priority is managed only with subpriority.
* @arg NVIC_PriorityGroup_1: 1 bits for preemption priority.
* 3 bits for subpriority.
* @arg NVIC_PriorityGroup_2: 2 bits for preemption priority.
* 2 bits for subpriority.
* @arg NVIC_PriorityGroup_3: 3 bits for preemption priority.
* 1 bits for subpriority.
* @arg NVIC_PriorityGroup_4: 4 bits for preemption priority.
* 0 bits for subpriority.
* @retval None
*/
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
{
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
}
/**
* @brief Initializes the NVIC peripheral according to the specified
* parameters in the NVIC_InitStruct.
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
* function should be called before.
* @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
* the configuration information for the specified NVIC peripheral.
* @retval None
*/
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
{
uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
{
/* Compute the Corresponding IRQ Priority --------------------------------*/
tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
tmppre = (0x4 - tmppriority);
tmpsub = tmpsub >> tmppriority;
tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
tmppriority |= (uint8_t)((NVIC_InitStruct->NVIC_IRQChannelSubPriority) & tmpsub);
tmppriority = tmppriority << 0x04;
NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
/* Enable the Selected IRQ Channels --------------------------------------*/
NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
}
else
{
/* Disable the Selected IRQ Channels -------------------------------------*/
NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
}
}
/**
* @brief Sets the vector table location and Offset.
* @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
* This parameter can be one of the following values:
* @arg NVIC_VectTab_RAM: Vector Table in internal SRAM.
* @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH.
* @param Offset: Vector Table base offset field. This value must be a multiple of 0x200.
* @retval None
*/
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
{
/* Check the parameters */
assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
assert_param(IS_NVIC_OFFSET(Offset));
SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
}
/**
* @brief Selects the condition for the system to enter low power mode.
* @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
* This parameter can be one of the following values:
* @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend.
* @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.
* @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.
* @param NewState: new state of LP condition.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_NVIC_LP(LowPowerMode));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
SCB->SCR |= LowPowerMode;
}
else
{
SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

548
libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_pwr.c
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/**
******************************************************************************
* @file stm32w108xx_pwr.c
* @author MCD Application Team
* @version V1.0.1
* @date 30-November-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the power management (PWR):
* + Voltage Regulator control
* + WakeUp Pin/Source Configuration
* + DeepSleep mode
* + WakeUp status
*
* @verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..] This driver provides the Low level functions to manage the low level power
registers. These functions are split in 4 groups
(#) Voltage Regulator control functions: this group includes the
management of following features using PWR_VREGInit() function:
(++) Configure the regulator Trim values
(++) Enable/Disable VREF, V1.8 and V1.2 voltage regulators
(#) WakeUp Pin/Source Configuration functions: this group includes all
needed to configure an interrupt as WakeUp source:
(++) To control the GPIO pin to WakeUp the system from low power mode use the
PWR_GPIOWakeUpPinCmd() function.
(++) To configure the WakeUp method to wake the system from low power mode use
the PWR_WakeUpSourceConfig() function.
(++) To command the WakeUp source filter use PWR_WakeUpFilterConfig() function.
(#) DeepSleep mode functions: this group includes the deep sleep feature
configuration:
(++) To freeze the GPIO state before entering in low power mode use
the PWR_FreezestateLVoutput() function.
(++) To control the deep sleep mode 0 when debugger is attached use
the PWR_DeepSleepMode0Cmd() function.
(++) To Wake the core from deep sleep 0 the WakeUp source filter use
PWR_CoreWake() function.
(++) To Disable the system access to the ACK bit in the CSYSPWRUPACKSR use
PWR_InhibitCSYSPWRUPACK() function.
(#) WakeUp Status functions: this group includes the required functions to
manage the WakeUp interrupt status:
(++) When the system wake up from low power mode use PWR_GetFlagStatus()
to check witch interrupt is the source for WakeUp.
(++) After check the user should clear the WakeUp source in the low power
status register using PWR_ClearFlag() function.
@endverbatim
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32w108xx_pwr.h"
/** @addtogroup STM32W108xx_StdPeriph_Driver
* @{
*/
/** @defgroup POWER_MANAGEMENT
* @brief PWR driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup PWR_Private_Functions
* @{
*/
/** @defgroup PWR_Group1 Voltage Regulator control
* @brief Voltage regulator VREF, V1.8 and V1.2 control
*
@verbatim
===============================================================================
##### Voltage Regulator control function #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Deinitializes the PWR peripheral registers to their default reset values.
* @param None
* @retval None
*/
void PWR_DeInit(void)
{
PWR->DSLEEPCR1 = 0x00000000;
PWR->DSLEEPCR2 = 0x00000001;
PWR->VREGCR = 0x00000207;
PWR->WAKECR1 = 0x00000200;
PWR->WAKECR2 = 0x00000000;
PWR->WAKESR = 0x000003FF;
PWR->CSYSPWRUPACKCR = 0x00000000;
PWR->WAKEPAR = 0x00000000;
PWR->WAKEPBR = 0x00000000;
PWR->WAKEPCR = 0x00000000;
PWR->WAKEFILTR = 0x00000000;
}
/**
* @brief Fills each VREG_InitStruct member with its default value.
* @param VREG_InitStruct: pointer to a PWR_VREG_InitTypeDef structure
* which will be initialized.
* @retval None
*/
void PWR_VREGStructInit(PWR_VREG_InitTypeDef* VREG_InitStruct)
{
/* VREG_InitStruct members default value */
VREG_InitStruct->PWR_VREFCmd = POWER_ENABLE; /* by default enable */
VREG_InitStruct->PWR_1V8Cmd = POWER_ENABLE; /* by default enable */
VREG_InitStruct->PWR_1V8TRIM = 4;
VREG_InitStruct->PWR_1V2Cmd = POWER_ENABLE; /* by default enable */
VREG_InitStruct->PWR_1V2TRIM = 7;
}
/**
* @brief Initializes the VREG peripheral according to the specified
* parameters in the VREG_InitStruct.
* @param VREG_InitStruct: pointer to a PWR_VREG_InitTypeDef structure
* that contains the configuration information for the specified VREG.
* @retval None
*/
void PWR_VREGInit(PWR_VREG_InitTypeDef* VREG_InitStruct)
{
uint32_t temp = 0;
/* Check the parameters */
assert_param(IS_POWER_FUNCTIONAL_STATE(VREG_InitStruct->PWR_VREFCmd));
assert_param(IS_POWER_FUNCTIONAL_STATE(VREG_InitStruct->PWR_1V8Cmd));
assert_param(IS_TRIM_VALUE(VREG_InitStruct->PWR_1V8TRIM));
assert_param(IS_POWER_FUNCTIONAL_STATE(VREG_InitStruct->PWR_1V2Cmd));
assert_param(IS_TRIM_VALUE(VREG_InitStruct->PWR_1V2TRIM));
temp = (uint32_t)(((VREG_InitStruct->PWR_1V8TRIM) << 7) | (VREG_InitStruct->PWR_1V2TRIM));
/* Check the new VREF status */
if (VREG_InitStruct->PWR_VREFCmd == POWER_DISABLE)
{
/* Disable VREF */
temp |= PWR_VREGCR_VREFEN;
}
/* Check the new 1V8 status */
if (VREG_InitStruct->PWR_1V8Cmd == POWER_DISABLE)
{
/* Disable 1V8 */
temp |= PWR_VREGCR_1V8EN;
}
/* Check the new 1V2 status */
if (VREG_InitStruct->PWR_1V2Cmd == POWER_DISABLE)
{
/* Disable 1V2 */
temp |= PWR_VREGCR_1V2EN;
}
/* Set the new VREG configuration */
PWR->VREGCR = temp;
}
/**
* @}
*/
/** @defgroup PWR_Group2 WakeUp Pin/Source Configuration
* @brief Low Power mode source WakeUp and method configuration
*
@verbatim
===============================================================================
##### WakeUp Pin-Source Configuration function #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables or disables the GPIO WakeUp pin.
* @param GPIOx: where x can be (A, B or C) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be one of GPIO_Pin_x where x can be (0..7).
* @param NewState: new state of the GPIO WakeUp pin source.
* This parameter can be: ENABLE or DISABLE.
* @note The GPIO WakeUp monitoring should be enabled before enabling the GPIO WakeUp pin.
* To enable the GPIO WakeUp monitoring use PWR_WakeUpSourceConfig() function.
* @retval None
*/
void PWR_GPIOWakeUpPinCmd(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (GPIOx == GPIOA)
{
if (NewState != DISABLE)
{
PWR->WAKEPAR |= (uint32_t)GPIO_Pin;
}
else
{
PWR->WAKEPAR &= (uint32_t)~GPIO_Pin;
}
}
else if (GPIOx == GPIOB)
{
if (NewState != DISABLE)
{
PWR->WAKEPBR |= (uint32_t)GPIO_Pin;
}
else
{
PWR->WAKEPBR &= (uint32_t)~GPIO_Pin;
}
}
else
{
if (GPIOx == GPIOC)
{
if (NewState != DISABLE)
{
PWR->WAKEPCR |= (uint32_t)GPIO_Pin;
}
else
{
PWR->WAKEPCR &= (uint32_t)~GPIO_Pin;
}
}
}
}
/**
* @brief Enables or disables the WakeUp source filter.
* @param PWR_WakeUpSource: specifies the selected PWR WakeUp source.
* This parameter can be one of the following values:
* @arg PWR_WAKEFILTER_GPIO: filter active on GPIO monitoring.
* @arg PWR_WAKEFILTER_SC1: filter active on SC1.
* @arg PWR_WAKEFILTER_SC2: filter active on SC2.
* @arg PWR_WAKEFILTER_IRQD: filter active on IRQD.
* @param NewState: new state of the WakeUp source.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void PWR_WakeUpFilterConfig(uint32_t PWR_WakeUpSource, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_PWR_WAKEUPFILTERSOURCE(PWR_WakeUpSource));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the dedicated WakeUp filter by setting the dedicated bit in the
WAKEFILTR register */
PWR->WAKEFILTR |= PWR_WakeUpSource;
}
else
{
/* Disable the dedicated WakeUp filter by clearing the dedicated bit in the WAKEFILTR register */
PWR->WAKEFILTR &= (uint32_t)~((uint32_t)PWR_WakeUpSource);
}
}
/**
* @brief Enables or disables the WakeUp method form low power mode.
* @param PWR_WakeUpSource: specifies the selected PWR wakeup method.
* This parameter can be one of the following values:
* @arg PWR_WAKEUP_CSYSPWRRUPREQ: Wake up active on CSYSPWRUPREQ event.
* @arg PWR_WAKEUP_CPWRRUPREQ: Wake up active on CPWRRUPREQ event.
* @arg PWR_WAKEUP_CORE: Wake up active on COREWAKE event.
* @arg PWR_WAKEUP_WRAP: Wake up active on sleep timer compare wrap/overflow event.
* @arg PWR_WAKEUP_COMPB: Wake up active on sleep timer compare B event.
* @arg PWR_WAKEUP_COMPA: Wake up active on sleep timer compare A event.
* @arg PWR_WAKEUP_IRQD: Wake up active on falling/rising edge of pin PC0.
* @arg PWR_WAKEUP_SC2: Wake up active on falling/rising edge of pin PA2 for SC2.
* @arg PWR_WAKEUP_SC1: Wake up active on falling/rising edge of pin PB2 for SC12.
* @arg PWR_WAKEUP_MON: Wake up active on GPIO monitoring.
* @param NewState: new state of the WakeUp source.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void PWR_WakeUpSourceConfig(uint32_t PWR_WakeUpSource, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_PWR_WAKEUPSOURCE(PWR_WakeUpSource));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the WakeUp from low power method by setting the dedicated bit in the WAKECR1 register */
PWR->WAKECR1 |= PWR_WakeUpSource;
}
else
{
/* Disable the WakeUp from low power method by clearing the dedicated bit in the WAKECR1 register */
PWR->WAKECR1 &= (uint32_t)~((uint32_t)PWR_WakeUpSource);
}
}
/**
* @}
*/
/** @defgroup PWR_Group3 DeepSleep mode
* @brief control the DeepSleep mode features
*
@verbatim
===============================================================================
##### DeepSleep mode function #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables or disables the freeze GPIO state LV output.
* @param NewState: new freeze state of the GPIO state LV output.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void PWR_FreezestateLVoutput(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable freeze GPIO state LV output by setting the LVFREEZE bit in the DSLEEPCR1 register */
PWR->DSLEEPCR1 |= PWR_DSLEEPCR1_LVFREEZE;
}
else
{
/* Disable freeze GPIO state LV output from low power method by clearing the LVFREEZE bit in the DSLEEPCR1 register */
PWR->DSLEEPCR1 &= (uint32_t)~((uint32_t)PWR_DSLEEPCR1_LVFREEZE);
}
}
/**
* @brief Enables or disables the deep sleep mode 0 when debugger is attached.
* @param NewState: new freeze state of the GPIO state LV output.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void PWR_DeepSleepMode0Cmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable deep sleep mode 0 if debugger attached by setting the MODE bit in the DSLEEPCR2 register */
PWR->DSLEEPCR2 |= PWR_DSLEEPCR2_MODE;
}
else
{
/* Disable deep sleep mode 0 if debugger by clearing the MODE bit in the DSLEEPCR2 register */
PWR->DSLEEPCR2 &= (uint32_t)~((uint32_t)PWR_DSLEEPCR2_MODE);
}
}
/**
* @brief Wake core form a deep sleep 0.
* @param None
* @retval None
*/
void PWR_CoreWake(void)
{
/* Wake core from deep sleep 0 by setting the COREWAKE bit in the WAKECR2 register */
PWR->WAKECR2 |= PWR_WAKECR2_COREWAKE;
}
/**
* @brief Disables the cortex-M3 system access to the ACK bit in the CSYSPWRUPACKSR register.
* @param None
* @retval None
*/
void PWR_InhibitCSYSPWRUPACK(void)
{
/* Disable the system access to the ACK bit in the CSYSPWRUPACKSR by setting
the INHIBIT bit in the CSYSPWRUPACKCR register */
PWR->CSYSPWRUPACKCR |= PWR_CSYSPWRUPACKCR_INHIBIT;
}
/**
* @}
*/
/** @defgroup PWR_Group4 WakeUp status
* @brief Control the low power WakeUp source status
*
@verbatim
===============================================================================
##### WakeUp status function #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Checks whether the specified PWR flag is set or not.
* @param PWR_FLAG: specifies the low power wake up flag to check.
* This parameter can be one of the following values:
* @arg PWR_FLAG_CSYSPWRRUPREQ: Wake up done using the DAP access to SYS registers flag
* @arg PWR_FLAG_CPWRRUPREQ: Wake up done using the DAP access to DBG registers flag
* @arg PWR_FLAG_CORE: Wake up done using debug port activity flag
* @arg PWR_FLAG_WRAP: Wake up done using sleep timer wrap flag
* @arg PWR_FLAG_COMPB: Wake up done using sleep timer compare B flag
* @arg PWR_FLAG_COMPA: Wake up done using sleep timer compare A flag
* @arg PWR_FLAG_IRQD: Wake up done using external interrupt IRQD flag
* @arg PWR_FLAG_SC2: Wake up done using serial controller 2 (PA2) flag
* @arg PWR_FLAG_SC1: Wake up done using serial controller 1 (PB2) flag
* @arg PWR_FLAG_MON: Wake up done using GPIO monitoring flag
* @arg PWR_FLAG_CPWRUPREQ: REQ flag in the CPWRUPREQSR register
* @arg PWR_FLAG_CSYSPWRUPREQ: REQ flag in the CSYSPWRUPREQSR register
* @arg PWR_FLAG_CSYSPWRUPREQ: ACK flag in the CSYSPWRUPREQSR register
* @retval The new state of PWR_FLAG (SET or RESET).
*/
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
/* Check the REQ flag in the CPWRUPREQSR register */
if (PWR_FLAG == PWR_FLAG_CPWRUPREQ)
{
if ((PWR->CPWRUPREQSR & 0x00000001) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
}
/* Check the REQ flag in the CSYSPWRUPREQSR register */
else if (PWR_FLAG == PWR_FLAG_CSYSPWRUPREQ)
{
if ((PWR->CSYSPWRUPREQSR & 0x00000001) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
}
/* Check the ACK flag in the CSYSPWRUPACKSR register */
else if (PWR_FLAG == PWR_FLAG_CSYSPWRUPREQ)
{
if ((PWR->CSYSPWRUPACKSR & 0x00000001) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
}
/* Check the Wake up flag in the WAKESR register */
else
{
if ((PWR->WAKESR & PWR_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
}
return bitstatus;
}
/**
* @brief Clears the PWR pending flags.
* @param PWR_FLAG: specifies the low power wake up flag to clear.
* This parameter can be one of the following values:
* @arg PWR_FLAG_CSYSPWRRUPREQ: Wake up done using the DAP access to SYS registers flag
* @arg PWR_FLAG_CPWRRUPREQ: Wake up done using the DAP access to DBG registers flag
* @arg PWR_FLAG_CORE: Wake up done using debug port activity flag
* @arg PWR_FLAG_WRAP: Wake up done using sleep timer wrap flag
* @arg PWR_FLAG_COMPB: Wake up done using sleep timer compare B flag
* @arg PWR_FLAG_COMPA: Wake up done using sleep timer compare A flag
* @arg PWR_FLAG_IRQD: Wake up done using external interrupt IRQD flag
* @arg PWR_FLAG_SC2: Wake up done using serial controller 2 (PA2) flag
* @arg PWR_FLAG_SC1: Wake up done using serial controller 1 (PB2) flag
* @arg PWR_FLAG_MON: Wake up done using GPIO monitoring flag
* @retval The new state of PWR_FLAG (SET or RESET).
*/
void PWR_ClearFlag(uint32_t PWR_FLAG)
{
/* Check the parameters */
assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
PWR->WAKESR = PWR_FLAG;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_rst.c
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@ -1,134 +0,0 @@
/**
******************************************************************************
* @file stm32w108xx_rst.c
* @author MCD Application Team
* @version V1.0.1
* @date 30-November-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the RST peripheral
*
* @verbatim
*
===============================================================================
##### RST specific features #####
===============================================================================
[..] This driver provide the information about reset source
[..] The reset can be due to:
(#) Core lockup
(#) Option byte load failure (may be set with other bits
(#) Wake-up from Deep Sleep
(#) Software reset
(#) Watchdog expiration
(#) External reset pin signal
(#) The application of a Core power supply (or previously failed)
(#) Normal power applied
@endverbatim
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32w108xx_rst.h"
/** @addtogroup STM32W108xx_StdPeriph_Driver
* @{
*/
/** @defgroup RESET
* @brief RST driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup RST_Private_Functions
* @{
*/
/** @defgroup RST_Group1
* @brief Reset event sources
*
@verbatim
===============================================================================
##### RST EVENT SOURCES #####
===============================================================================
[..] This section provides function allowing to get reset event source
@endverbatim
* @{
*/
/**
* @brief Checks whether the specified RST flag is set or not.
* @param RST_FLAG: specifies the RST_FLAG flag to check.
* This parameter can be one of the following values:
* @arg RST_FLAG_PWRHV: Normal power applied
* @arg RST_FLAG_PWRLV: The application of a Core power supply (or previously failed)
* @arg RST_FLAG_PIN: External reset pin signal.
* @arg RST_FLAG_WDG: Watchdog expiration
* @arg RST_FLAG_SWRST: Software reset.
* @arg RST_FLAG_WKUP: Wake-up from Deep Sleep
* @arg RST_FLAG_OBFAIL: Option byte load failure (may be set with other bits)
* @arg RST_FLAG_LKUP: Core lockup
*
* @retval The new state of RST_FLAG (SET or RESET)
*/
FlagStatus RST_GetFlagStatus(uint32_t RST_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_RST_FLAG(RST_FLAG));
if ((RST->SR & RST_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_sc.c
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libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_slptim.c
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/**
******************************************************************************
* @file stm32w108xx_slptim.c
* @author MCD Application Team
* @version V1.0.1
* @date 30-November-2012
* @brief This file provides firmware functions to manage the Sleep Timer
* peripheral.
*
* @verbatim
*
===============================================================================
##### SLPTIM features #####
===============================================================================
[..] The sleep timer is dedicated to system timing and waking from sleep at
specific times.
[..] The sleep timer can use either the calibrated 1 kHz reference(CLK1K),
or the 32 kHz crystal clock (CLK32K). The default clock source is
the internal 1 kHz clock.
[..] The sleep timer has a prescaler that allows for very long periods of
sleep to be timed.
[..] The timer provides two compare outputs and wrap detection, all of which
can be used to generate an interrupt or a wake up event.
[..] The sleep timer is paused when the debugger halts the ARM Cortex-M3.
##### How to use this driver #####
===============================================================================
[..] This driver provides functions to configure and program the Sleep Timer
These functions are split in 2 groups:
(#) SLPTIM management functions: this group includes all needed functions
to configure the Sleep Timer.
(++) Enable/Disable the counter.
(++) Get counter.
(++) Select clock to be used as reference.
(++) Set/Get compare (A or B) values.
(#) Interrupts and flags management functions: this group includes all needed
functions to manage interrupts:
(++) Enables or disables the specified SLPTIM interrupts.
(++) Checks whether the specified SLPTIM flag is set or not.
(++) Clears the specified SLPTIM flag.
@endverbatim
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32w108xx_slptim.h"
/** @addtogroup STM32W108xx_StdPeriph_Driver
* @{
*/
/** @defgroup SLPTIM
* @brief SLPTIM driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup SLPTIM_Private_Functions
* @{
*/
/** @defgroup SLPTIM_Group1 SLPTIM management functions
* @brief SLPTIM management functions
*
@verbatim
===============================================================================
##### SLPTIM management functions #####
===============================================================================
[..] To use the Sleep Timer:
(#) Fill the SLPTIM_InitStruct with the desired parameters.
This must be done while the sleep timer is disabled.
(#) Call the SLPTIM_Cmd(ENABLE) function to enable the TIM counter.
(#) Enable the clock to be used as reference by calling SLPTIM_ClockConfig()
function.
[..]
(@) All other functions can be used seperatly to set compareA or compareB value,
to get counter value...
@endverbatim
* @{
*/
/**
* @brief Deinitializes the SLPTIM peripheral registers to their default reset values.
* @retval None
*
*/
void SLPTIM_DeInit(void)
{
SLPTMR->CR = 0x00000400;
SLPTMR->CMPAL = 0x0000FFFF;
SLPTMR->CMPAH = 0x0000FFFF;
SLPTMR->CMPBL = 0x0000FFFF;
SLPTMR->CMPBH = 0x0000FFFF;
SLPTMR->ISR = 0x00000007;
SLPTMR->IER = 0x00000000;
}
/**
* @brief Initializes the SLPTIM Time peripheral according to
* the specified parameters in the SLPTIM_InitStruct.
* @param SLPTIM_InitStruct: pointer to a SLPTIM_InitTypeDef
* structure that contains the configuration information for
* the specified TIM peripheral.
* @retval None
*/
void SLPTIM_Init(SLPTIM_InitTypeDef* SLPTIM_InitStruct)
{
uint32_t tmpcr = 0;
/* Check the parameters */
assert_param(IS_SLPTIM_COUNTER_MODE(SLPTIM_InitStruct->SLPTIM_CounterMode));
assert_param(IS_SLPTIM_GET_CLKSEL(SLPTIM_InitStruct->SLPTIM_Clock));
assert_param(IS_SLPTIM_CLKDIV(SLPTIM_InitStruct->SLPTIM_Prescaler));
assert_param(IS_SLPTIM_DBGMODE(SLPTIM_InitStruct->SLPTIM_DebugMode));
tmpcr = SLPTMR->CR;
/* Set the Sleep Timer Clock */
tmpcr &= (uint32_t)~SLPTMR_CR_CLKSEL;
tmpcr |= (uint32_t)SLPTIM_InitStruct->SLPTIM_Clock;
/* Set the Prescaler value */
tmpcr &= (uint32_t)~SLPTMR_CR_PSC;
tmpcr |= (uint32_t)SLPTIM_InitStruct->SLPTIM_Prescaler;
/* Selects the timer's mode during debug */
tmpcr &= (uint32_t)~SLPTMR_CR_DBGP;
tmpcr |= (uint32_t)SLPTIM_InitStruct->SLPTIM_DebugMode;
/* Selects the Counter Mode */
tmpcr &= (uint32_t)~SLPTMR_CR_REVERSE;
tmpcr |= (uint32_t)SLPTIM_InitStruct->SLPTIM_CounterMode;
SLPTMR->CR = tmpcr;
}
/**
* @brief Fills each SLPTIM_InitStruct member with its default value.
* @param SLPTIM_InitStruct : pointer to a SLPTIM_InitTypeDef
* structure which will be initialized.
* @retval None
*/
void SLPTIM_StructInit(SLPTIM_InitTypeDef* SLPTIM_InitStruct)
{
/* Set the default configuration */
SLPTIM_InitStruct->SLPTIM_Clock = SLPTIM_CLK_1KHZ;
SLPTIM_InitStruct->SLPTIM_Prescaler = SLPTIM_CLK_DIV0;
SLPTIM_InitStruct->SLPTIM_DebugMode = SLPTIM_DBGRUN;
SLPTIM_InitStruct->SLPTIM_CounterMode = SLPTIM_CountForward;
}
/**
* @brief Enables or disables the Sleep Timer.
* @param NewState: new state of the Sleep Timer.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void SLPTIM_Cmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the Sleep Timer */
SLPTMR->CR |= (uint32_t)SLPTMR_CR_EN;
}
else
{
/* Disable the clock */
SLPTMR->CR &= (uint32_t)~SLPTMR_CR_EN;
}
}
/**
* @brief Sets the SLPTIM Compare A Register value
* @param CompareA: specifies the Compare A register new value.
* @retval None
*/
void SLPTIM_SetCompareA(uint32_t CompareA)
{
/* Set the Compare A Register value */
SLPTMR->CMPAL = (uint32_t)(CompareA & 0x0000FFFF);
SLPTMR->CMPAH = (uint32_t)((CompareA >> 16) & 0x0000FFFF);
}
/**
* @brief Sets the SLPTIM Compare B Register value
* @param CompareB: specifies the Compare B register new value.
* @retval None
*/
void SLPTIM_SetCompareB(uint32_t CompareB)
{
/* Set the Compare B Register value */
SLPTMR->CMPBL = (uint32_t)(CompareB & 0x0000FFFF);
SLPTMR->CMPBH = (uint32_t)((CompareB >> 16) & 0x0000FFFF);
}
/**
* @brief Gets the SLPTIM Counter value.
* @retval Counter Register value.
*/
uint32_t SLPTIM_GetCounter(void)
{
uint32_t counter = 0;
/* Get the Counter Register value */
counter = (uint32_t)(SLPTMR->CNTH << 16);
counter |= (uint32_t)SLPTMR->CNTL;
return counter;
}
/**
* @brief Gets the SLPTIM Counter high value.
* @retval Counter Register high value.
*/
uint32_t SLPTIM_GetCounterHigh(void)
{
__IO uint32_t counter = 0;
/* Get the Counter Register value */
counter = (uint32_t)SLPTMR->CNTH;
return counter;
}
/**
* @brief Gets the SLPTIM Counter low value.
* @retval Counter Register low value.
*/
uint32_t SLPTIM_GetCounterLow(void)
{
__IO uint32_t counter = 0;
/* Get the Counter Register value */
counter = (uint32_t)SLPTMR->CNTH;
counter = (uint32_t)SLPTMR->CNTL;
return counter;
}
/**
* @}
*/
/** @defgroup SLPTIM_Group2 Interrupts and flags management functions
* @brief Interrupts and flags management functions
*
@verbatim
===============================================================================
##### Interrupts and flags management functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Forces the specified SLPTIM interrupts.
* @param SLPTIM_IT: specifies the SLPTIM interrupts sources to be generated.
* This parameter can be any combination of the following values:
* @arg SLPTIM_IT_WRAP: Sleep timer overflow
* @arg SLPTIM_IT_CMPA: Sleep timer compare A
* @arg SLPTIM_IT_CMPB: Sleep timer compare B
* @retval None
*/
void SLPTIM_ForceIT(uint32_t SLPTIM_IT)
{
/* Check the parameters */
assert_param(IS_SLPTIM_IT(SLPTIM_IT));
/* Force the Interrupt by setting the dedicated interrupt in the IFR register */
SLPTMR->IFR |= SLPTIM_IT;
}
/**
* @brief Enables or disables the specified SLPTIM interrupts.
* @param SLPTIM_IT: specifies the SLPTIM interrupts sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg SLPTIM_IT_WRAP: Sleep timer overflow
* @arg SLPTIM_IT_CMPA: Sleep timer compare A
* @arg SLPTIM_IT_CMPB: Sleep timer compare B
* @param NewState: new state of the SLPTIM interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void SLPTIM_ITConfig(uint32_t SLPTIM_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_SLPTIM_IT(SLPTIM_IT));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the Interrupt sources */
SLPTMR->IER |= SLPTIM_IT;
}
else
{
/* Disable the Interrupt sources */
SLPTMR->IER &= (uint32_t)~SLPTIM_IT;
}
}
/**
* @brief Checks whether the specified SLPTIM flag is set or not.
* @param SLPTIM_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg SLPTIM_FLAG_WRAP: Sleep timer overflow
* @arg SLPTIM_FLAG_CMPA: Sleep timer compare A
* @arg SLPTIM_FLAG_CMPB: Sleep timer compare B
* @note
* @retval The new state of SLPTIM_FLAG (SET or RESET).
*/
FlagStatus SLPTIM_GetFlagStatus(uint32_t SLPTIM_FLAG)
{
ITStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_SLPTIM_FLAG(SLPTIM_FLAG));
if ((SLPTMR->ISR & SLPTIM_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/**
* @brief Clears the specified SLPTIM flag.
* @param SLPTIM_FLAG: specifies the flag to clear.
* This parameter can be one of the following values:
* @arg SLPTIM_FLAG_WRAP: Sleep timer overflow
* @arg SLPTIM_FLAG_CMPA: Sleep timer compare A
* @arg SLPTIM_FLAG_CMPB: Sleep timer compare B
* @note
* @retval The new state of SLPTIM_FLAG (SET or RESET).
*/
void SLPTIM_ClearFlag(uint32_t SLPTIM_FLAG)
{
/* Check the parameters */
assert_param(IS_SLPTIM_FLAG(SLPTIM_FLAG));
/* Clear the flags */
SLPTMR->ISR |= (uint32_t)SLPTIM_FLAG;
}
/**
* @brief Checks whether the specified SLPTMR pending interrupt has occurred or not
* @param SLPTIM_IT: specifies the flag to check.
* This parameter can be one of the following values:
* This parameter can be one of the following values:
* @arg SLPTIM_FLAG_WRAP: Sleep timer overflow
* @arg SLPTIM_FLAG_CMPA: Sleep timer compare A
* @arg SLPTIM_FLAG_CMPB: Sleep timer compare B
* @retval The new state of SLPTIM_IT (SET or RESET).
*/
ITStatus SLPTIM_GetITStatus(uint32_t SLPTIM_IT)
{
ITStatus bitstatus = RESET;
uint32_t enablestatus = 0;
/* Check the parameters */
assert_param(IS_SLPTIM_IT(SLPTIM_IT));
enablestatus = (uint32_t)(SLPTMR->IER & SLPTIM_IT);
if (((SLPTMR->ISR & SLPTIM_IT) != (uint32_t)RESET) && enablestatus)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/**
* @brief Clears the specified SLPTIM flag.
* @param SLPTIM_IT: specifies the flag to clear.
* This parameter can be one of the following values:
* @arg SLPTIM_FLAG_WRAP: Sleep timer overflow
* @arg SLPTIM_FLAG_CMPA: Sleep timer compare A
* @arg SLPTIM_FLAG_CMPB: Sleep timer compare B
* @note
* @retval The new state of SLPTIM_FLAG (SET or RESET).
*/
void SLPTIM_ClearITPendingBit(uint32_t SLPTIM_IT)
{
/* Check the parameters */
assert_param(IS_SLPTIM_IT(SLPTIM_IT));
/* Clear the pending interrupt */
SLPTMR->ISR |= (uint32_t)SLPTIM_IT;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_tim.c
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libs/STM32W108xx_StdPeriph_Driver/src/stm32w108xx_wdg.c
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/**
******************************************************************************
* @file stm32w108xx_wdg.c
* @author MCD Application Team
* @version V1.0.1
* @date 30-November-2012
* @brief This file provides firmware functions to use the watchdog (WDG) peripheral
*
* @verbatim
*
================================================================================
##### WDG features #####
================================================================================
[..] The watchdog timer uses the calibrated 1 kHz clock (CLK1K) as its reference
and provides a nominal 2.048 s timeout. A low water mark interrupt occurs
at 1.760 s and triggers an NMI to the Cortex-M3 NVIC as an early warning.
When enabled, periodically reset the watchdog timer before it expires.
[..] By default, the WDG is disabled at power up of the always-on power domain.
[..] The watchdog timer can be paused when the debugger halts the core.
##### How to use this driver #####
================================================================================
[..] This driver allows to use WDG peripheral.
[..] Start the WDG using WDG_Cmd() function.
[..] Restart the WDG timer using WDG_ReloadCounter() function.
[..] Specifies the staus of WDG timer during debug mode using WDG_DebugConfig() function.
@endverbatim
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32w108xx_wdg.h"
/** @addtogroup STM32W108xx_StdPeriph_Driver
* @{
*/
/** @defgroup WDG
* @brief WDG driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* ---------------------- WDG registers bit mask -----------------------------*/
#define KICKSR_KEY_RELOAD ((uint32_t)0xAAAAAAAA)
#define KR_KEY_ENABLE ((uint32_t)0x0000EABE)
#define KR_KEY_DISABLE ((uint32_t)0x0000DEAD)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup WDG_Private_Functions
* @{
*/
/** @defgroup WDG_Group1 WDG activation function
* @brief WDG activation function
*
@verbatim
==============================================================================
##### WDG activation function #####
==============================================================================
@endverbatim
* @{
*/
/**
* @brief Deinitializes the WDG peripheral registers to their default reset values.
* @param None
* @retval None
*/
void WDG_DeInit(void)
{
WDG->CR = 0x00000002;
WDG->KR = 0x00000000;
WDG->KICKSR = 0x00000000;
}
/**
* @brief Reloads WDG counter with value defined in the restart register
* @param None
* @retval None
*/
void WDG_ReloadCounter(void)
{
WDG->KICKSR = KICKSR_KEY_RELOAD;
}
/**
* @brief Enables/Disables WDG.
* @param NewState: new state of the WDG timer.
* This parameter can be: ENABLE or DISABLE.
* @retval None.
*/
void WDG_Cmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
WDG->KR = 0x00000000;
WDG->KR |= KR_KEY_ENABLE;
WDG->CR = WDG_CR_WDGEN;
}
else
{
WDG->KR = 0x00000000;
WDG->KR |= KR_KEY_DISABLE;
WDG->CR = WDG_CR_WDGDIS;
}
}
/**
* @brief Status of WDG timer while in debug mode.
* @param DBG_STATUS: specifies the staus of WDG timer during debug mode.
* This parameter can be one of the following values:
* @arg WDG_DBG_RUN: The timer continues working in Debug mode.
* @arg WDG_DBG_PAUSE: The timer is paused in Debug mode when the CPU is halted.
* @retval None.
*/
void WDG_DebugConfig(uint32_t DBG_STATUS)
{
/* Check the parameters */
assert_param(IS_WDG_DEBUG_STATUS(DBG_STATUS));
SLPTMR->CR = DBG_STATUS;
}
/**
* @brief Returns the status of WDG timer.
* @param None
* @retval None
*/
FunctionalState WDG_GetStatus(void)
{
FunctionalState wdgstatus = DISABLE;
if ((WDG->CR & WDG_CR_WDGEN) == WDG_CR_WDGEN)
{
wdgstatus = ENABLE;
}
else
{
wdgstatus = DISABLE;
}
return wdgstatus;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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libs/stm32w108xx.ld.in
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stm32f10x.ld.in

29
libs/stm32w108xx.mk
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# The processor!
MCU_CORE=cm3
# Set up include paths
MCU_INCLUDE += -I$(LIBDIR)/CMSIS/Device/ST/STM32W108xx/Include
MCU_INCLUDE += -I$(LIBDIR)/STM32W108xx_StdPeriph_Driver/inc
# Set up CFLAGS
MCU_CPPFLAGS += -D$(shell echo -n $(MCU_SUBTYPE) | tr a-z A-Z )
MCU_CPPFLAGS += -D"assert_param(expr)=((void)0)"
MCU_CFLAGS += -mcpu=cortex-m3 -mthumb -Wa,-mthumb
MCU_CXXFLAGS += -mcpu=cortex-m3 -mthumb -Wa,-mthumb
# CMSIS
STM32W108xx_OBJS = $(LIBDIR)/CMSIS/Device/ST/STM32W108xx/Source/Templates/system_stm32w108xx.o
# Standard Peripheral Library
STM32W108xx_OBJSR = stm32w108xx_adc.o stm32w108xx_gpio.o stm32w108xx_sc.o \
stm32w108xx_clk.o stm32w108xx_misc.o stm32w108xx_slptim.o \
stm32w108xx_exti.o stm32w108xx_pwr.o stm32w108xx_tim.o \
stm32w108xx_flash.o stm32w108xx_rst.o stm32w108xx_wdg.o
STM32W108xx_OBJS += $(addprefix $(LIBDIR)/STM32W108xx_StdPeriph_Driver/src/,$(STM32W108xx_OBJSR))
# Bookkeeping
MCU_LIBS_OBJS += $(STM32W108xx_OBJS) $(LIBDIR)/startup_$(MCU).o
# Build Rules
$(LIBDIR)/startup_$(MCU).o: $(LIBDIR)/CMSIS/Device/ST/STM32W108xx/Source/Templates/gcc_ride7/startup_$(MCU).s
@$(E) " AS " $@
$(Q)$(AS) -c -o $@ $<