Update STM32LXXX library from 1.2.2 to 1.3.0
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@ -2,12 +2,12 @@
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******************************************************************************
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* @file stm32l1xx.h
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* @author MCD Application Team
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* @version V1.2.0
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* @date 22-February-2013
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* @version V1.3.3
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* @date 20-April-2015
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
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* This file contains all the peripheral register's definitions, bits
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* definitions and memory mapping for STM32L1xx High-density, Medium-density
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* and Medium-density Plus devices.
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* definitions and memory mapping for STM32L1xx High-density, Medium-density,
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* Medium-density and XL-density Plus devices.
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*
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* The file is the unique include file that the application programmer
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* is using in the C source code, usually in main.c. This file contains:
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@ -26,7 +26,7 @@
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
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* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
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*
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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@ -66,26 +66,60 @@
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application
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*/
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#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD)
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#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD) && !defined (STM32L1XX_XL)
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/* #define STM32L1XX_MD */ /*!< - Ultra Low Power Medium-density devices: STM32L151x6xx, STM32L151x8xx,
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STM32L151xBxx, STM32L152x6xx, STM32L152x8xx and STM32L152xBxx.
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STM32L151xBxx, STM32L152x6xx, STM32L152x8xx, STM32L152xBxx,
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STM32L151x6xxA, STM32L151x8xxA, STM32L151xBxxA, STM32L152x6xxA,
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STM32L152x8xxA and STM32L152xBxxA.
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- Ultra Low Power Medium-density Value Line devices: STM32L100x6xx,
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STM32L100x8xx and STM32L100xBxx. */
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/* #define STM32L1XX_MDP */ /*!< - Ultra Low Power Medium-density Plus devices: STM32L151xCxx, STM32L152xCxx and STM32L162xCxx
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- Ultra Low Power Medium-density Plus Value Line devices: STM32L100xCxx */
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#define STM32L1XX_HD /*!< Ultra Low Power High-density devices: STM32L151xDxx, STM32L152xDxx and STM32L162xDxx */
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/* #define STM32L1XX_HD */ /*!< Ultra Low Power High-density devices: STM32L151xDxx, STM32L152xDxx and STM32L162xDxx */
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/* #define STM32L1XX_XL */ /*!< Ultra Low Power XL-density devices: STM32L151xExx, STM32L152xExx and STM32L162xExx */
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#endif
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/* Tip: To avoid modifying this file each time you need to switch between these
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devices, you can define the device in your toolchain compiler preprocessor.
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*/
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#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD)
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#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD) && !defined (STM32L1XX_XL)
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#error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)"
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#endif
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/*
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The table below provides the list of available part numbers per category, and the corresponding preprocessor
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switch to be defined in the StdLib.
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==============================================================================================================+
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Memory density level | RPNs | StdLib switch | Cat.1 | Cat.2 | Cat.3 | Cat.4 | Cat.5 |
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==============================================================================================================+
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| STM32L100x6xx, STM32L151x6xx, | | | | | | |
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32KB | STM32L152x6xx, STM32L151x6xxA | STM32L1XX_MD | X | X | | | |
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| and STM32L152x6xxA | | | | | | |
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--------------------------------------------------------------------------------------------------------------+
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| STM32L100x8xx, STM32L151x8xx, | | | | | | |
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64KB | STM32L152x8xx, STM32L151x8xxA | STM32L1XX_MD | X | X | | | |
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| and STM32L152x8xxA | | | | | | |
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--------------------------------------------------------------------------------------------------------------+
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| STM32L100xBxx, STM32L151xBxx, | | | | | | |
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128KB | STM32L152xBxx, STM32L151xBxxA | STM32L1XX_MD | X | X | | | |
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| and STM32L152xBxxA | | | | | | |
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--------------------------------------------------------------------------------------------------------------+
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| STM32L100xCxx, STM32L151xCxx, | | | | | | |
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256KB | STM32L152xCxx and | STM32L1XX_MDP | | | X | X | |
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| STM32L162xCxx | | | | | | |
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--------------------------------------------------------------------------------------------------------------+
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| STM32L151xDxx, STM32L152xDxx | | | | | | |
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384KB | and STM32L162xDxx | STM32L1XX_HD | | | | X | |
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--------------------------------------------------------------------------------------------------------------+
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| STM32L151xExx, STM32L152xExx | | | | | | |
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512KB | and STM32L162xExx | STM32L1XX_XL | | | | | X |
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==============================================================================================================+
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*/
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#if !defined USE_STDPERIPH_DRIVER
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/**
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* @brief Comment the line below if you will not use the peripherals drivers.
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@ -111,7 +145,7 @@
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Timeout value
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*/
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#if !defined (HSE_STARTUP_TIMEOUT)
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#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */
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#define HSE_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSE start up */
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#endif
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/**
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@ -119,7 +153,7 @@
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Timeout value
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*/
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#if !defined (HSI_STARTUP_TIMEOUT)
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#define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */
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#define HSI_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSI start up */
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#endif
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#if !defined (HSI_VALUE)
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@ -139,11 +173,11 @@
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#endif
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/**
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* @brief STM32L1xx Standard Peripheral Library version number V1.2.0
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* @brief STM32L1xx Standard Peripheral Library version number V1.3.3
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*/
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#define __STM32L1XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
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#define __STM32L1XX_STDPERIPH_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
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#define __STM32L1XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
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#define __STM32L1XX_STDPERIPH_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
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#define __STM32L1XX_STDPERIPH_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
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#define __STM32L1XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
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#define __STM32L1XX_STDPERIPH_VERSION ( (__STM32L1XX_STDPERIPH_VERSION_MAIN << 24)\
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|(__STM32L1XX_STDPERIPH_VERSION_SUB1 << 16)\
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@ -225,6 +259,7 @@ typedef enum IRQn
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RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
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USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */
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TIM6_IRQn = 43, /*!< TIM6 global Interrupt */
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#ifdef STM32L1XX_MD
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TIM7_IRQn = 44 /*!< TIM7 global Interrupt */
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#endif /* STM32L1XX_MD */
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@ -257,6 +292,21 @@ typedef enum IRQn
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AES_IRQn = 55, /*!< AES global Interrupt */
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COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */
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#endif /* STM32L1XX_HD */
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#ifdef STM32L1XX_XL
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TIM7_IRQn = 44, /*!< TIM7 global Interrupt */
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TIM5_IRQn = 46, /*!< TIM5 global Interrupt */
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SPI3_IRQn = 47, /*!< SPI3 global Interrupt */
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UART4_IRQn = 48, /*!< UART4 global Interrupt */
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UART5_IRQn = 49, /*!< UART5 global Interrupt */
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DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */
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DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */
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DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */
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DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */
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DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */
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AES_IRQn = 55, /*!< AES global Interrupt */
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COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */
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#endif /* STM32L1XX_XL */
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} IRQn_Type;
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/**
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@ -304,9 +354,9 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
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/* GNU Compiler
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------------
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RAM functions are defined using a specific toolchain attribute
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"__attribute__((section(".data")))".
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"__attribute__((section(".RamFunc")))".
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*/
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#define __RAM_FUNC FLASH_Status __attribute__((section(".data")))
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#define __RAM_FUNC FLASH_Status __attribute__((section(".RamFunc")))
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#elif defined ( __TASKING__ )
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/* TASKING Compiler
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@ -488,10 +538,19 @@ typedef struct
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__IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
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__IO uint32_t OBR; /*!< Option byte register, Address offset: 0x1c */
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__IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
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uint32_t RESERVED[23]; /*!< Reserved, 0x24 */
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__IO uint32_t WRPR1; /*!< Write protection register 1, Address offset: 0x28 */
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__IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x2C */
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uint32_t RESERVED[23]; /*!< Reserved, 0x24-0x7C */
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__IO uint32_t WRPR1; /*!< Write protection register 1, Address offset: 0x80 */
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__IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x84 */
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__IO uint32_t WRPR3; /*!< Write protection register 3, Address offset: 0x88 */
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} FLASH_TypeDef;
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/* IMPORTANT NOTE
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==============
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In the StdLib, the naming of WRP registers is shifted vs. the Reference Manual:
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- WRPR correspond to WRPR1
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- WRPR1 correspond to WRPR2
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- WRPR2 correspond to WRPR3
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- WRPR3 correspond to WRPR4
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*/
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/**
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* @brief Option Bytes Registers
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@ -507,6 +566,9 @@ typedef struct
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__IO uint32_t WRP67; /*!< write protection register 6 7, Address offset: 0x14 */
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__IO uint32_t WRP89; /*!< write protection register 8 9, Address offset: 0x18 */
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__IO uint32_t WRP1011; /*!< write protection register 10 11, Address offset: 0x1C */
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uint32_t RESERVED[24]; /*!< Reserved, 0x20-0x7C */
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__IO uint32_t WRP1213; /*!< write protection register 12 13, Address offset: 0x80 */
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__IO uint32_t WRP1415; /*!< write protection register 14 15, Address offset: 0x84 */
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} OB_TypeDef;
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/**
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@ -557,8 +619,10 @@ typedef struct
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__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high registerBSRR, Address offset: 0x1A */
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__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
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__IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
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#if defined (STM32L1XX_HD) || defined (STM32L1XX_XL)
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__IO uint16_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
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uint16_t RESERVED3; /*!< Reserved, 0x2A */
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#endif
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} GPIO_TypeDef;
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/**
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@ -663,13 +727,28 @@ typedef struct
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typedef struct
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{
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__IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */
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__IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
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__IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
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__IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */
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__IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
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__IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */
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__IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */
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__IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x04 */
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__IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x08 */
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__IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x0C */
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__IO uint32_t HYSCR1; /*!< RI hysteresis control register 1, Address offset: 0x10 */
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__IO uint32_t HYSCR2; /*!< RI Hysteresis control register 2, Address offset: 0x14 */
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__IO uint32_t HYSCR3; /*!< RI Hysteresis control register 3, Address offset: 0x18 */
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__IO uint32_t HYSCR4; /*!< RI Hysteresis control register 4, Address offset: 0x1C */
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__IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x20 */
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__IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x24 */
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__IO uint32_t CICR1; /*!< RI Channel identification for capture register 1, Address offset: 0x28 */
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__IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x2C */
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__IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x30 */
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__IO uint32_t CICR2; /*!< RI Channel identification for capture register 2, Address offset: 0x34 */
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__IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x38 */
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__IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x3C */
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__IO uint32_t CICR3; /*!< RI Channel identification for capture register3 , Address offset: 0x40 */
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__IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x44 */
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__IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x48 */
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__IO uint32_t CICR4; /*!< RI Channel identification for capture register 4, Address offset: 0x4C */
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__IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x50 */
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__IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x54 */
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__IO uint32_t CICR5; /*!< RI Channel identification for capture register 5, Address offset: 0x58 */
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} RI_TypeDef;
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/**
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#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
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/*!< Unique device ID registers */
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#if defined (STM32L1XX_MD)
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#define UID1 ((uint32_t)0x1FF80050)
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#define UID2 ((uint32_t)0x1FF80054)
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#define UID3 ((uint32_t)0x1FF80064)
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#elif defined (STM32L1XX_MDP) || defined (STM32L1XX_HD) || defined (STM32L1XX_XL)
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#define UID1 ((uint32_t)0x1FF800D0)
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#define UID2 ((uint32_t)0x1FF800D4)
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#define UID3 ((uint32_t)0x1FF800E4)
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#endif
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/**
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* @}
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*/
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#define RI_HYSCR4_PG_14 ((uint32_t)0x00004000) /*!< Bit 14 */
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#define RI_HYSCR4_PG_15 ((uint32_t)0x00008000) /*!< Bit 15 */
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/******************** Bit definition for RI_ASMR1 register ********************/
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#define RI_ASMR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A analog switch mode selection */
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#define RI_ASMR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
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#define RI_ASMR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
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#define RI_ASMR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
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#define RI_ASMR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
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#define RI_ASMR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */
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#define RI_ASMR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */
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#define RI_ASMR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */
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#define RI_ASMR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */
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#define RI_ASMR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */
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#define RI_ASMR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */
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#define RI_ASMR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */
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#define RI_ASMR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */
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#define RI_ASMR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */
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#define RI_ASMR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */
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#define RI_ASMR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */
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#define RI_ASMR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */
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/******************** Bit definition for RI_CMR1 register ********************/
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#define RI_CMR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A channel masking */
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#define RI_CMR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
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#define RI_CMR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
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#define RI_CMR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
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#define RI_CMR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
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#define RI_CMR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */
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#define RI_CMR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */
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#define RI_CMR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */
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#define RI_CMR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */
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#define RI_CMR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */
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#define RI_CMR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */
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#define RI_CMR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */
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#define RI_CMR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */
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#define RI_CMR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */
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#define RI_CMR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */
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#define RI_CMR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */
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#define RI_CMR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */
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/******************** Bit definition for RI_CICR1 register ********************/
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#define RI_CICR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A channel identification for capture */
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#define RI_CICR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
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#define RI_CICR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
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#define RI_CICR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
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#define RI_CICR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
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#define RI_CICR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */
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#define RI_CICR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */
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#define RI_CICR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */
|
||||
#define RI_CICR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */
|
||||
#define RI_CICR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */
|
||||
#define RI_CICR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */
|
||||
#define RI_CICR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */
|
||||
#define RI_CICR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */
|
||||
#define RI_CICR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */
|
||||
#define RI_CICR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */
|
||||
#define RI_CICR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */
|
||||
#define RI_CICR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */
|
||||
|
||||
/******************** Bit definition for RI_ASMR2 register ********************/
|
||||
#define RI_ASMR2_PB ((uint32_t)0x0000FFFF) /*!< PB[15:0] Port B analog switch mode selection */
|
||||
#define RI_ASMR2_PB_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define RI_ASMR2_PB_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
#define RI_ASMR2_PB_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
||||
#define RI_ASMR2_PB_3 ((uint32_t)0x00000008) /*!< Bit 3 */
|
||||
#define RI_ASMR2_PB_4 ((uint32_t)0x00000010) /*!< Bit 4 */
|
||||
#define RI_ASMR2_PB_5 ((uint32_t)0x00000020) /*!< Bit 5 */
|
||||
#define RI_ASMR2_PB_6 ((uint32_t)0x00000040) /*!< Bit 6 */
|
||||
#define RI_ASMR2_PB_7 ((uint32_t)0x00000080) /*!< Bit 7 */
|
||||
#define RI_ASMR2_PB_8 ((uint32_t)0x00000100) /*!< Bit 8 */
|
||||
#define RI_ASMR2_PB_9 ((uint32_t)0x00000200) /*!< Bit 9 */
|
||||
#define RI_ASMR2_PB_10 ((uint32_t)0x00000400) /*!< Bit 10 */
|
||||
#define RI_ASMR2_PB_11 ((uint32_t)0x00000800) /*!< Bit 11 */
|
||||
#define RI_ASMR2_PB_12 ((uint32_t)0x00001000) /*!< Bit 12 */
|
||||
#define RI_ASMR2_PB_13 ((uint32_t)0x00002000) /*!< Bit 13 */
|
||||
#define RI_ASMR2_PB_14 ((uint32_t)0x00004000) /*!< Bit 14 */
|
||||
#define RI_ASMR2_PB_15 ((uint32_t)0x00008000) /*!< Bit 15 */
|
||||
|
||||
/******************** Bit definition for RI_CMR2 register ********************/
|
||||
#define RI_CMR2_PB ((uint32_t)0x0000FFFF) /*!< PB[15:0] Port B channel masking */
|
||||
#define RI_CMR2_PB_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define RI_CMR2_PB_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
#define RI_CMR2_PB_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
||||
#define RI_CMR2_PB_3 ((uint32_t)0x00000008) /*!< Bit 3 */
|
||||
#define RI_CMR2_PB_4 ((uint32_t)0x00000010) /*!< Bit 4 */
|
||||
#define RI_CMR2_PB_5 ((uint32_t)0x00000020) /*!< Bit 5 */
|
||||
#define RI_CMR2_PB_6 ((uint32_t)0x00000040) /*!< Bit 6 */
|
||||
#define RI_CMR2_PB_7 ((uint32_t)0x00000080) /*!< Bit 7 */
|
||||
#define RI_CMR2_PB_8 ((uint32_t)0x00000100) /*!< Bit 8 */
|
||||
#define RI_CMR2_PB_9 ((uint32_t)0x00000200) /*!< Bit 9 */
|
||||
#define RI_CMR2_PB_10 ((uint32_t)0x00000400) /*!< Bit 10 */
|
||||
#define RI_CMR2_PB_11 ((uint32_t)0x00000800) /*!< Bit 11 */
|
||||
#define RI_CMR2_PB_12 ((uint32_t)0x00001000) /*!< Bit 12 */
|
||||
#define RI_CMR2_PB_13 ((uint32_t)0x00002000) /*!< Bit 13 */
|
||||
#define RI_CMR2_PB_14 ((uint32_t)0x00004000) /*!< Bit 14 */
|
||||
#define RI_CMR2_PB_15 ((uint32_t)0x00008000) /*!< Bit 15 */
|
||||
|
||||
/******************** Bit definition for RI_CICR2 register ********************/
|
||||
#define RI_CICR2_PB ((uint32_t)0x0000FFFF) /*!< PB[15:0] Port B channel identification for capture */
|
||||
#define RI_CICR2_PB_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define RI_CICR2_PB_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
#define RI_CICR2_PB_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
||||
#define RI_CICR2_PB_3 ((uint32_t)0x00000008) /*!< Bit 3 */
|
||||
#define RI_CICR2_PB_4 ((uint32_t)0x00000010) /*!< Bit 4 */
|
||||
#define RI_CICR2_PB_5 ((uint32_t)0x00000020) /*!< Bit 5 */
|
||||
#define RI_CICR2_PB_6 ((uint32_t)0x00000040) /*!< Bit 6 */
|
||||
#define RI_CICR2_PB_7 ((uint32_t)0x00000080) /*!< Bit 7 */
|
||||
#define RI_CICR2_PB_8 ((uint32_t)0x00000100) /*!< Bit 8 */
|
||||
#define RI_CICR2_PB_9 ((uint32_t)0x00000200) /*!< Bit 9 */
|
||||
#define RI_CICR2_PB_10 ((uint32_t)0x00000400) /*!< Bit 10 */
|
||||
#define RI_CICR2_PB_11 ((uint32_t)0x00000800) /*!< Bit 11 */
|
||||
#define RI_CICR2_PB_12 ((uint32_t)0x00001000) /*!< Bit 12 */
|
||||
#define RI_CICR2_PB_13 ((uint32_t)0x00002000) /*!< Bit 13 */
|
||||
#define RI_CICR2_PB_14 ((uint32_t)0x00004000) /*!< Bit 14 */
|
||||
#define RI_CICR2_PB_15 ((uint32_t)0x00008000) /*!< Bit 15 */
|
||||
|
||||
/******************** Bit definition for RI_ASMR3 register ********************/
|
||||
#define RI_ASMR3_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C analog switch mode selection */
|
||||
#define RI_ASMR3_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define RI_ASMR3_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
#define RI_ASMR3_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
||||
#define RI_ASMR3_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
|
||||
#define RI_ASMR3_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
|
||||
#define RI_ASMR3_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
|
||||
#define RI_ASMR3_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
|
||||
#define RI_ASMR3_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
|
||||
#define RI_ASMR3_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */
|
||||
#define RI_ASMR3_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */
|
||||
#define RI_ASMR3_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */
|
||||
#define RI_ASMR3_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */
|
||||
#define RI_ASMR3_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */
|
||||
#define RI_ASMR3_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */
|
||||
#define RI_ASMR3_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */
|
||||
#define RI_ASMR3_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */
|
||||
|
||||
/******************** Bit definition for RI_CMR3 register ********************/
|
||||
#define RI_CMR3_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C channel masking */
|
||||
#define RI_CMR3_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define RI_CMR3_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
#define RI_CMR3_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
||||
#define RI_CMR3_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
|
||||
#define RI_CMR3_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
|
||||
#define RI_CMR3_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
|
||||
#define RI_CMR3_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
|
||||
#define RI_CMR3_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
|
||||
#define RI_CMR3_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */
|
||||
#define RI_CMR3_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */
|
||||
#define RI_CMR3_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */
|
||||
#define RI_CMR3_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */
|
||||
#define RI_CMR3_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */
|
||||
#define RI_CMR3_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */
|
||||
#define RI_CMR3_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */
|
||||
#define RI_CMR3_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */
|
||||
|
||||
/******************** Bit definition for RI_CICR3 register ********************/
|
||||
#define RI_CICR3_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C channel identification for capture */
|
||||
#define RI_CICR3_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define RI_CICR3_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
#define RI_CICR3_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
||||
#define RI_CICR3_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
|
||||
#define RI_CICR3_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
|
||||
#define RI_CICR3_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
|
||||
#define RI_CICR3_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
|
||||
#define RI_CICR3_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
|
||||
#define RI_CICR3_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */
|
||||
#define RI_CICR3_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */
|
||||
#define RI_CICR3_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */
|
||||
#define RI_CICR3_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */
|
||||
#define RI_CICR3_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */
|
||||
#define RI_CICR3_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */
|
||||
#define RI_CICR3_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */
|
||||
#define RI_CICR3_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */
|
||||
|
||||
/******************** Bit definition for RI_ASMR4 register ********************/
|
||||
#define RI_ASMR4_PF ((uint32_t)0x0000FFFF) /*!< PF[15:0] Port F analog switch mode selection */
|
||||
#define RI_ASMR4_PF_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define RI_ASMR4_PF_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
#define RI_ASMR4_PF_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
||||
#define RI_ASMR4_PF_3 ((uint32_t)0x00000008) /*!< Bit 3 */
|
||||
#define RI_ASMR4_PF_4 ((uint32_t)0x00000010) /*!< Bit 4 */
|
||||
#define RI_ASMR4_PF_5 ((uint32_t)0x00000020) /*!< Bit 5 */
|
||||
#define RI_ASMR4_PF_6 ((uint32_t)0x00000040) /*!< Bit 6 */
|
||||
#define RI_ASMR4_PF_7 ((uint32_t)0x00000080) /*!< Bit 7 */
|
||||
#define RI_ASMR4_PF_8 ((uint32_t)0x00000100) /*!< Bit 8 */
|
||||
#define RI_ASMR4_PF_9 ((uint32_t)0x00000200) /*!< Bit 9 */
|
||||
#define RI_ASMR4_PF_10 ((uint32_t)0x00000400) /*!< Bit 10 */
|
||||
#define RI_ASMR4_PF_11 ((uint32_t)0x00000800) /*!< Bit 11 */
|
||||
#define RI_ASMR4_PF_12 ((uint32_t)0x00001000) /*!< Bit 12 */
|
||||
#define RI_ASMR4_PF_13 ((uint32_t)0x00002000) /*!< Bit 13 */
|
||||
#define RI_ASMR4_PF_14 ((uint32_t)0x00004000) /*!< Bit 14 */
|
||||
#define RI_ASMR4_PF_15 ((uint32_t)0x00008000) /*!< Bit 15 */
|
||||
|
||||
/******************** Bit definition for RI_CMR4 register ********************/
|
||||
#define RI_CMR4_PF ((uint32_t)0x0000FFFF) /*!< PF[15:0] Port F channel masking */
|
||||
#define RI_CMR4_PF_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define RI_CMR4_PF_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
#define RI_CMR4_PF_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
||||
#define RI_CMR4_PF_3 ((uint32_t)0x00000008) /*!< Bit 3 */
|
||||
#define RI_CMR4_PF_4 ((uint32_t)0x00000010) /*!< Bit 4 */
|
||||
#define RI_CMR4_PF_5 ((uint32_t)0x00000020) /*!< Bit 5 */
|
||||
#define RI_CMR4_PF_6 ((uint32_t)0x00000040) /*!< Bit 6 */
|
||||
#define RI_CMR4_PF_7 ((uint32_t)0x00000080) /*!< Bit 7 */
|
||||
#define RI_CMR4_PF_8 ((uint32_t)0x00000100) /*!< Bit 8 */
|
||||
#define RI_CMR4_PF_9 ((uint32_t)0x00000200) /*!< Bit 9 */
|
||||
#define RI_CMR4_PF_10 ((uint32_t)0x00000400) /*!< Bit 10 */
|
||||
#define RI_CMR4_PF_11 ((uint32_t)0x00000800) /*!< Bit 11 */
|
||||
#define RI_CMR4_PF_12 ((uint32_t)0x00001000) /*!< Bit 12 */
|
||||
#define RI_CMR4_PF_13 ((uint32_t)0x00002000) /*!< Bit 13 */
|
||||
#define RI_CMR4_PF_14 ((uint32_t)0x00004000) /*!< Bit 14 */
|
||||
#define RI_CMR4_PF_15 ((uint32_t)0x00008000) /*!< Bit 15 */
|
||||
|
||||
/******************** Bit definition for RI_CICR4 register ********************/
|
||||
#define RI_CICR4_PF ((uint32_t)0x0000FFFF) /*!< PF[15:0] Port F channel identification for capture */
|
||||
#define RI_CICR4_PF_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define RI_CICR4_PF_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
#define RI_CICR4_PF_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
||||
#define RI_CICR4_PF_3 ((uint32_t)0x00000008) /*!< Bit 3 */
|
||||
#define RI_CICR4_PF_4 ((uint32_t)0x00000010) /*!< Bit 4 */
|
||||
#define RI_CICR4_PF_5 ((uint32_t)0x00000020) /*!< Bit 5 */
|
||||
#define RI_CICR4_PF_6 ((uint32_t)0x00000040) /*!< Bit 6 */
|
||||
#define RI_CICR4_PF_7 ((uint32_t)0x00000080) /*!< Bit 7 */
|
||||
#define RI_CICR4_PF_8 ((uint32_t)0x00000100) /*!< Bit 8 */
|
||||
#define RI_CICR4_PF_9 ((uint32_t)0x00000200) /*!< Bit 9 */
|
||||
#define RI_CICR4_PF_10 ((uint32_t)0x00000400) /*!< Bit 10 */
|
||||
#define RI_CICR4_PF_11 ((uint32_t)0x00000800) /*!< Bit 11 */
|
||||
#define RI_CICR4_PF_12 ((uint32_t)0x00001000) /*!< Bit 12 */
|
||||
#define RI_CICR4_PF_13 ((uint32_t)0x00002000) /*!< Bit 13 */
|
||||
#define RI_CICR4_PF_14 ((uint32_t)0x00004000) /*!< Bit 14 */
|
||||
#define RI_CICR4_PF_15 ((uint32_t)0x00008000) /*!< Bit 15 */
|
||||
|
||||
/******************** Bit definition for RI_ASMR5 register ********************/
|
||||
#define RI_ASMR5_PG ((uint32_t)0x0000FFFF) /*!< PG[15:0] Port G analog switch mode selection */
|
||||
#define RI_ASMR5_PG_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define RI_ASMR5_PG_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
#define RI_ASMR5_PG_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
||||
#define RI_ASMR5_PG_3 ((uint32_t)0x00000008) /*!< Bit 3 */
|
||||
#define RI_ASMR5_PG_4 ((uint32_t)0x00000010) /*!< Bit 4 */
|
||||
#define RI_ASMR5_PG_5 ((uint32_t)0x00000020) /*!< Bit 5 */
|
||||
#define RI_ASMR5_PG_6 ((uint32_t)0x00000040) /*!< Bit 6 */
|
||||
#define RI_ASMR5_PG_7 ((uint32_t)0x00000080) /*!< Bit 7 */
|
||||
#define RI_ASMR5_PG_8 ((uint32_t)0x00000100) /*!< Bit 8 */
|
||||
#define RI_ASMR5_PG_9 ((uint32_t)0x00000200) /*!< Bit 9 */
|
||||
#define RI_ASMR5_PG_10 ((uint32_t)0x00000400) /*!< Bit 10 */
|
||||
#define RI_ASMR5_PG_11 ((uint32_t)0x00000800) /*!< Bit 11 */
|
||||
#define RI_ASMR5_PG_12 ((uint32_t)0x00001000) /*!< Bit 12 */
|
||||
#define RI_ASMR5_PG_13 ((uint32_t)0x00002000) /*!< Bit 13 */
|
||||
#define RI_ASMR5_PG_14 ((uint32_t)0x00004000) /*!< Bit 14 */
|
||||
#define RI_ASMR5_PG_15 ((uint32_t)0x00008000) /*!< Bit 15 */
|
||||
|
||||
/******************** Bit definition for RI_CMR5 register ********************/
|
||||
#define RI_CMR5_PG ((uint32_t)0x0000FFFF) /*!< PG[15:0] Port G channel masking */
|
||||
#define RI_CMR5_PG_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define RI_CMR5_PG_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
#define RI_CMR5_PG_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
||||
#define RI_CMR5_PG_3 ((uint32_t)0x00000008) /*!< Bit 3 */
|
||||
#define RI_CMR5_PG_4 ((uint32_t)0x00000010) /*!< Bit 4 */
|
||||
#define RI_CMR5_PG_5 ((uint32_t)0x00000020) /*!< Bit 5 */
|
||||
#define RI_CMR5_PG_6 ((uint32_t)0x00000040) /*!< Bit 6 */
|
||||
#define RI_CMR5_PG_7 ((uint32_t)0x00000080) /*!< Bit 7 */
|
||||
#define RI_CMR5_PG_8 ((uint32_t)0x00000100) /*!< Bit 8 */
|
||||
#define RI_CMR5_PG_9 ((uint32_t)0x00000200) /*!< Bit 9 */
|
||||
#define RI_CMR5_PG_10 ((uint32_t)0x00000400) /*!< Bit 10 */
|
||||
#define RI_CMR5_PG_11 ((uint32_t)0x00000800) /*!< Bit 11 */
|
||||
#define RI_CMR5_PG_12 ((uint32_t)0x00001000) /*!< Bit 12 */
|
||||
#define RI_CMR5_PG_13 ((uint32_t)0x00002000) /*!< Bit 13 */
|
||||
#define RI_CMR5_PG_14 ((uint32_t)0x00004000) /*!< Bit 14 */
|
||||
#define RI_CMR5_PG_15 ((uint32_t)0x00008000) /*!< Bit 15 */
|
||||
|
||||
/******************** Bit definition for RI_CICR5 register ********************/
|
||||
#define RI_CICR5_PG ((uint32_t)0x0000FFFF) /*!< PG[15:0] Port G channel identification for capture */
|
||||
#define RI_CICR5_PG_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||
#define RI_CICR5_PG_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||
#define RI_CICR5_PG_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
||||
#define RI_CICR5_PG_3 ((uint32_t)0x00000008) /*!< Bit 3 */
|
||||
#define RI_CICR5_PG_4 ((uint32_t)0x00000010) /*!< Bit 4 */
|
||||
#define RI_CICR5_PG_5 ((uint32_t)0x00000020) /*!< Bit 5 */
|
||||
#define RI_CICR5_PG_6 ((uint32_t)0x00000040) /*!< Bit 6 */
|
||||
#define RI_CICR5_PG_7 ((uint32_t)0x00000080) /*!< Bit 7 */
|
||||
#define RI_CICR5_PG_8 ((uint32_t)0x00000100) /*!< Bit 8 */
|
||||
#define RI_CICR5_PG_9 ((uint32_t)0x00000200) /*!< Bit 9 */
|
||||
#define RI_CICR5_PG_10 ((uint32_t)0x00000400) /*!< Bit 10 */
|
||||
#define RI_CICR5_PG_11 ((uint32_t)0x00000800) /*!< Bit 11 */
|
||||
#define RI_CICR5_PG_12 ((uint32_t)0x00001000) /*!< Bit 12 */
|
||||
#define RI_CICR5_PG_13 ((uint32_t)0x00002000) /*!< Bit 13 */
|
||||
#define RI_CICR5_PG_14 ((uint32_t)0x00004000) /*!< Bit 14 */
|
||||
#define RI_CICR5_PG_15 ((uint32_t)0x00008000) /*!< Bit 15 */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* Timers (TIM) */
|
||||
|
|
|
|||
|
|
@ -2,13 +2,13 @@
|
|||
******************************************************************************
|
||||
* @file system_stm32l1xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 22-February-2013
|
||||
* @version V1.3.3
|
||||
* @date 20-April-2015
|
||||
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
|
||||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
|
||||
<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns="http://www.w3.org/TR/REC-html40"><head>
|
||||
|
||||
|
||||
|
|
@ -10,6 +10,13 @@
|
|||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
|
||||
<link rel="File-List" href="Release_Notes%20%28package%29_files/filelist.xml">
|
||||
<link rel="Edit-Time-Data" href="Release_Notes%20%28package%29_files/editdata.mso"><!--[if !mso]> <style> v\:* {behavior:url(#default#VML);} o\:* {behavior:url(#default#VML);} w\:* {behavior:url(#default#VML);} .shape {behavior:url(#default#VML);} </style> <![endif]--><title>Release Notes for STM32L1xx CMSIS</title><!--[if gte mso 9]><xml> <o:DocumentProperties> <o:Author>STMicroelectronics</o:Author> <o:LastAuthor>tguilhot</o:LastAuthor> <o:Revision>145</o:Revision> <o:TotalTime>461</o:TotalTime> <o:Created>2009-02-27T19:26:00Z</o:Created> <o:LastSaved>2010-12-13T14:14:00Z</o:LastSaved> <o:Pages>1</o:Pages> <o:Words>358</o:Words> <o:Characters>2045</o:Characters> <o:Company>STMicroelectronics</o:Company> <o:Lines>17</o:Lines> <o:Paragraphs>4</o:Paragraphs> <o:CharactersWithSpaces>2399</o:CharactersWithSpaces> <o:Version>11.9999</o:Version> </o:DocumentProperties> </xml><![endif]--><!--[if gte mso 9]><xml> <w:WordDocument> <w:View>Normal</w:View> <w:SpellingState>Clean</w:SpellingState> <w:GrammarState>Clean</w:GrammarState> <w:ValidateAgainstSchemas/> <w:SaveIfXMLInvalid>false</w:SaveIfXMLInvalid> <w:IgnoreMixedContent>false</w:IgnoreMixedContent> <w:AlwaysShowPlaceholderText>false</w:AlwaysShowPlaceholderText> <w:Compatibility> <w:UseFELayout/> </w:Compatibility> <w:BrowserLevel>MicrosoftInternetExplorer4</w:BrowserLevel> </w:WordDocument> </xml><![endif]--><!--[if gte mso 9]><xml> <w:LatentStyles DefLockedState="false" LatentStyleCount="156"> </w:LatentStyles> </xml><![endif]-->
|
||||
|
|
@ -278,7 +285,7 @@ ul
|
|||
Notes for<o:p></o:p> STM32L1xx CMSIS<br>
|
||||
</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
|
||||
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright
|
||||
© 2013 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
|
||||
© 2015 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
|
||||
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt;"><img style="border: 0px solid ; width: 86px; height: 65px;" alt="" id="_x0000_i1025" src="../../../../../_htmresc/logo.bmp"></span></p>
|
||||
</td>
|
||||
</tr>
|
||||
|
|
@ -289,12 +296,173 @@ Notes for<o:p></o:p> STM32L1xx CMSIS<br>
|
|||
<tbody>
|
||||
<tr style="">
|
||||
<td style="padding: 0cm;" valign="top">
|
||||
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>
|
||||
<ol style="margin-top: 0cm;" start="1" type="1">
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32L1xx CMSIS update history</a><o:p></o:p></span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>
|
||||
</ol>
|
||||
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32L1xx CMSIS update history</span></h2><br>
|
||||
|
||||
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update history</span></h2>
|
||||
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.3.3 / 20-April-2015<o:p></o:p></span></h3>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<ul style="margin-top: 0cm;" type="square">
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">V1.3.3 official release</span>, no changes vs. release candidate version (V1.3.3RC1)<br>
|
||||
</span></li>
|
||||
</ul>
|
||||
|
||||
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.3.3RC1 / 15-July-2014<o:p></o:p></span></h3>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<ul style="margin-top: 0cm;" type="square">
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx.h</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add UID registers mapping</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add product categories information</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add FLASH WRPR4 register definition <br>
|
||||
</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">IMPORTANT NOTE: In the StdLib, the naming of WRP registers is shifted vs. the Reference Manual:</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">WRPR correspond to WRPR1</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">WRPR1 correspond to WRPR2</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">WRPR2 correspond to WRPR3</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">WRPR3 correspond to WRPR4</span></li>
|
||||
</ul>
|
||||
</ul>
|
||||
</ul>
|
||||
</ul>
|
||||
|
||||
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.3.2 / 10-April-2014<o:p></o:p></span></h3>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<ul style="margin-top: 0cm;" type="square">
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update startup files for EWARM toolchain to cope with compiler enhancement of the V7.10 version.</span></li>
|
||||
</ul>
|
||||
|
||||
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.3.1 / 06-March-2014<o:p></o:p></span></h3>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<ul style="margin-top: 0cm;" type="square">
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx.h</span><span style="font-size: 10pt; font-family: Verdana;">: update RAM functions attribute definition for GNU compiler</span></li>
|
||||
</ul>
|
||||
|
||||
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.3.0 / 31-January-2014<o:p></o:p></span></h3>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<ul style="margin-top: 0cm;" type="square">
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add support for <span style="font-weight: bold; font-style: italic;">STM32L1xx XL-density</span> devices </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">"Ultra Low Power XL-density devices: STM32L151x<span style="font-weight: bold;">E</span>xx, STM32L152x<span style="font-weight: bold;">E</span>xx and STM32L162x<span style="font-weight: bold;">E</span>xx"</span></span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new startup file <span style="font-style: italic;">startup_stm32l1xx_xl.s</span> for all toolchains</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx.h</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new macro <span style="font-style: italic;">STM32L1XX_XL</span> for XL-density devices<span style="font-style: italic;"></span></span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update <span style="font-style: italic;">IRQn</span> enumeration for <span style="font-style: italic;">STM32L1XX_XL</span></span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">GPIO BRR register is declared only for STM32L1XX_HD and STM32L1XX_XL devices</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">All devices </span><span style="font-size: 10pt; font-family: Verdana;">definition </span><span style="font-size: 10pt; font-family: Verdana;">(i.e. STM32L1XX_xx) are commented out, user need to define the right STM32L1xx device in the toolchain compiler preprocessor</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Extend <span style="font-style: italic;">HSE_STARTUP_TIMEOUT</span> and <span style="font-style: italic;">HSI_STARTUP_TIMEOUT</span> values to 0x5000</span></li>
|
||||
</ul>
|
||||
</ul>
|
||||
|
||||
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.1 / 19-June-2013<o:p></o:p></span></h3>
|
||||
|
||||
|
||||
|
||||
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<ul style="margin-top: 0cm;" type="square">
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx.h</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update <span style="font-style: italic;">RI_TypeDef</span> structure by adding registers <span style="font-style: italic;">RI_ASMRx</span>, <span style="font-style: italic;">RI_CMRx</span> and <span style="font-style: italic;">RI_CICRx</span> (x=1..5)</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add bits definition for </span><span style="font-size: 10pt; font-family: Verdana;">registers <span style="font-style: italic;">RI_ASMRx</span>, <span style="font-style: italic;">RI_CMRx</span> and <span style="font-style: italic;">RI_CICRx</span> (x=1..5)</span></li>
|
||||
</ul>
|
||||
</ul>
|
||||
|
||||
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.0 / 22-February-2013<o:p></o:p></span></h3>
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file startup_stm32l1xx_hd.s
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 22-February-2013
|
||||
* @version V1.3.3
|
||||
* @date 20-April-2015
|
||||
* @brief STM32L1xx Ultra Low Power High-density Devices vector table for
|
||||
* Atollic toolchain.
|
||||
* This module performs:
|
||||
|
|
@ -18,7 +18,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file startup_stm32l1xx_md.s
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 22-February-2013
|
||||
* @version V1.3.3
|
||||
* @date 20-April-2015
|
||||
* @brief STM32L1xx Ultra Low Power Medium-density Devices vector table for
|
||||
* Atollic toolchain.
|
||||
* This module performs:
|
||||
|
|
@ -18,7 +18,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file startup_stm32l1xx_mdp.s
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 22-February-2013
|
||||
* @version V1.3.3
|
||||
* @date 20-April-2015
|
||||
* @brief STM32L1xx Ultra Low Power Medium-density Plus Devices vector table
|
||||
* for Atollic toolchain.
|
||||
* This module performs:
|
||||
|
|
@ -18,7 +18,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,421 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32l1xx_xl.s
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.3
|
||||
* @date 20-April-2015
|
||||
* @brief STM32L1xx Ultra Low Power XL-density Devices vector table for
|
||||
* Atollic toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address
|
||||
* - Configure the clock system
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m3
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
|
||||
.equ BootRAM, 0xF108F85F
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
movs r1, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r3, =_sidata
|
||||
ldr r3, [r3, r1]
|
||||
str r3, [r0, r1]
|
||||
adds r1, r1, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
ldr r0, =_sdata
|
||||
ldr r3, =_edata
|
||||
adds r2, r0, r1
|
||||
cmp r2, r3
|
||||
bcc CopyDataInit
|
||||
ldr r2, =_sbss
|
||||
b LoopFillZerobss
|
||||
/* Zero fill the bss segment. */
|
||||
FillZerobss:
|
||||
movs r3, #0
|
||||
str r3, [r2], #4
|
||||
|
||||
LoopFillZerobss:
|
||||
ldr r3, = _ebss
|
||||
cmp r2, r3
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
bl main
|
||||
bx lr
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
.word WWDG_IRQHandler
|
||||
.word PVD_IRQHandler
|
||||
.word TAMPER_STAMP_IRQHandler
|
||||
.word RTC_WKUP_IRQHandler
|
||||
.word FLASH_IRQHandler
|
||||
.word RCC_IRQHandler
|
||||
.word EXTI0_IRQHandler
|
||||
.word EXTI1_IRQHandler
|
||||
.word EXTI2_IRQHandler
|
||||
.word EXTI3_IRQHandler
|
||||
.word EXTI4_IRQHandler
|
||||
.word DMA1_Channel1_IRQHandler
|
||||
.word DMA1_Channel2_IRQHandler
|
||||
.word DMA1_Channel3_IRQHandler
|
||||
.word DMA1_Channel4_IRQHandler
|
||||
.word DMA1_Channel5_IRQHandler
|
||||
.word DMA1_Channel6_IRQHandler
|
||||
.word DMA1_Channel7_IRQHandler
|
||||
.word ADC1_IRQHandler
|
||||
.word USB_HP_IRQHandler
|
||||
.word USB_LP_IRQHandler
|
||||
.word DAC_IRQHandler
|
||||
.word COMP_IRQHandler
|
||||
.word EXTI9_5_IRQHandler
|
||||
.word LCD_IRQHandler
|
||||
.word TIM9_IRQHandler
|
||||
.word TIM10_IRQHandler
|
||||
.word TIM11_IRQHandler
|
||||
.word TIM2_IRQHandler
|
||||
.word TIM3_IRQHandler
|
||||
.word TIM4_IRQHandler
|
||||
.word I2C1_EV_IRQHandler
|
||||
.word I2C1_ER_IRQHandler
|
||||
.word I2C2_EV_IRQHandler
|
||||
.word I2C2_ER_IRQHandler
|
||||
.word SPI1_IRQHandler
|
||||
.word SPI2_IRQHandler
|
||||
.word USART1_IRQHandler
|
||||
.word USART2_IRQHandler
|
||||
.word USART3_IRQHandler
|
||||
.word EXTI15_10_IRQHandler
|
||||
.word RTC_Alarm_IRQHandler
|
||||
.word USB_FS_WKUP_IRQHandler
|
||||
.word TIM6_IRQHandler
|
||||
.word TIM7_IRQHandler
|
||||
.word 0
|
||||
.word TIM5_IRQHandler
|
||||
.word SPI3_IRQHandler
|
||||
.word UART4_IRQHandler
|
||||
.word UART5_IRQHandler
|
||||
.word DMA2_Channel1_IRQHandler
|
||||
.word DMA2_Channel2_IRQHandler
|
||||
.word DMA2_Channel3_IRQHandler
|
||||
.word DMA2_Channel4_IRQHandler
|
||||
.word DMA2_Channel5_IRQHandler
|
||||
.word AES_IRQHandler
|
||||
.word COMP_ACQ_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word BootRAM /* @0x108. This is for boot in RAM mode for
|
||||
STM32L15x ULtra Low Power High-density devices. */
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_IRQHandler
|
||||
.thumb_set PVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMPER_STAMP_IRQHandler
|
||||
.thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_IRQHandler
|
||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel1_IRQHandler
|
||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel2_IRQHandler
|
||||
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel3_IRQHandler
|
||||
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel4_IRQHandler
|
||||
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel5_IRQHandler
|
||||
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel6_IRQHandler
|
||||
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel7_IRQHandler
|
||||
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC1_IRQHandler
|
||||
.thumb_set ADC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USB_HP_IRQHandler
|
||||
.thumb_set USB_HP_IRQHandler,Default_Handler
|
||||
|
||||
.weak USB_LP_IRQHandler
|
||||
.thumb_set USB_LP_IRQHandler,Default_Handler
|
||||
|
||||
.weak DAC_IRQHandler
|
||||
.thumb_set DAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak COMP_IRQHandler
|
||||
.thumb_set COMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak LCD_IRQHandler
|
||||
.thumb_set LCD_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM9_IRQHandler
|
||||
.thumb_set TIM9_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM10_IRQHandler
|
||||
.thumb_set TIM10_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM11_IRQHandler
|
||||
.thumb_set TIM11_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM4_IRQHandler
|
||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handl | ||||