efm32: Add support for the EMF32 family.
I'm still hunting down one linker problem; when I fix it I'll commit the rest.
This commit is contained in:
parent
3625ad37c1
commit
d22848b96b
|
|
@ -0,0 +1,14 @@
|
|||
#ifndef __EFM32G_HW_H
|
||||
#define __EFM32G_HW_H
|
||||
|
||||
/* Configuration */
|
||||
#define MCU_SRAM_SIZE (64*1024)
|
||||
#define MCU_SRAM_BASE (0x20000000)
|
||||
#define MCU_EXTSRAM_SIZE (0)
|
||||
#define MCU_EXTSRAM_BASE (0x68000000)
|
||||
#define MCU_FLASH_BASE (0x08000000)
|
||||
#define MCU_FLASH_SIZE (512*1024)
|
||||
#define MCU_FLASH_PAGE_SIZE 2048
|
||||
#define MCU_FLASH_IMAGE_SIZE (510*1024)
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1 @@
|
|||
efm32g_hw.h
|
||||
|
|
@ -0,0 +1 @@
|
|||
efm32g_hw.h
|
||||
|
|
@ -0,0 +1 @@
|
|||
efm32g_hw.h
|
||||
|
|
@ -0,0 +1 @@
|
|||
efm32g_hw.h
|
||||
|
|
@ -0,0 +1,273 @@
|
|||
================ Revision history ============================================
|
||||
3.20.0:
|
||||
- Part header files: Added EFM32 Wonder Gecko support.
|
||||
- Part header files: FLASH_PAGE_SIZE macro added to all part files.
|
||||
- emlib: LEUART: Added LEUART_TxDmaInEM2Enable and LEUART_RxDmaInEM2Enable for
|
||||
enabling and disabling DMA LEUART RX and Tx in EM2 support.
|
||||
- usb: Documentation changes only.
|
||||
|
||||
3.0.3:
|
||||
- Internal release for testing Wonder Gecko support.
|
||||
|
||||
3.0.2:
|
||||
- Part header files: New header file em_device.h replace previous efm32.h.
|
||||
efm32.h is kept for backward compatibility.
|
||||
- Part startup files: system_efm32*.c files now handle CMU HFRCO frequencies
|
||||
correct for Production Revision 19 and higher.
|
||||
IAR startup_efm32*.c files now includes em_device.h.
|
||||
- emlib: Changes in MSC, CMU, BITBAND, DMA, BURTC and SYSTEM modules.
|
||||
Refer to emlib changes file for details.
|
||||
- usb: Bugfix, USBD_Init() may now be called when USB peripheral is in partial
|
||||
powerdown mode.
|
||||
New function USBD_EpIsBusy( int epAddr ) added to API.
|
||||
Changed USBD_AbortTransfer() from USBD_AbortTransfer( uint8_t ) to
|
||||
USBD_AbortTransfer( int ).
|
||||
Added configuration of which hw TIMER the stack will use.
|
||||
|
||||
3.0.1:
|
||||
- Part header files: Corrected resetvalue for CMU CTRL register
|
||||
- Part header files: Added missing DMA channel registers for Giant family
|
||||
- emlib: LFXO fix for Giant family.
|
||||
- usb: Added more flexibility for taking advantage of energymodes in USB applications.
|
||||
|
||||
3.0.0:
|
||||
- WARNING: This is a major update which reorganizes Energy Micro software.
|
||||
Peripheral APIs are kept intact, but you must update project-/makefiles
|
||||
and source files to use this version. PLEASE READ THE INSTRUCTIONS BELOW
|
||||
CAREFULLY.
|
||||
|
||||
- Updated to CMSIS-SP-00300-r3p1-00rel0 delivery from ARM Inc, including
|
||||
DSP_Lib, RTOS abstraction layer, support for Cortex-M4, Cortex-M0+
|
||||
(Flycatcher) and more. For a detailed overview see
|
||||
CMSIS/Documentation/General/html/index.html
|
||||
|
||||
- New file structure of part specific header files deployed according to
|
||||
CMSIS_V3 requirements. These are the most important changes, that must be
|
||||
changed in project files/Makefiles to update to this new release.
|
||||
|
||||
Cortex-Mx Core header files
|
||||
CMSIS/CM3/CoreSupport -> CMSIS/Include
|
||||
Gecko part specific header files
|
||||
CMSIS/CM3/DeviceSupport/EFM32/ -> Device/EnergyMicro/EFM32G/Include
|
||||
Tiny Gecko part specific header files
|
||||
CMSIS/CM3/DeviceSupport/EFM32/ -> Device/EnergyMicro/EFM32TG/Include
|
||||
Giant Gecko part specific header files
|
||||
CMSIS/CM3/DeviceSupport/EFM32/ -> Device/EnergyMicro/EFM32GG/Include
|
||||
Leopard Gecko part specific header files
|
||||
CMSIS/CM3/DeviceSupport/EFM32/ -> Device/EnergyMicro/EFM32LG/Include
|
||||
|
||||
- The earlier "core_cm3.c" file is now gone and can be deleted from projects,
|
||||
the functionality has moved into "core_cm3.h" (this header file is included
|
||||
in the part specific header file)
|
||||
|
||||
- Part specific header file size reduction has been implemented. The most common
|
||||
peripheral definitions have been moved into separate files, for instance a
|
||||
standard CMU implementation will be in defined in the file
|
||||
-> Device/EnergyMicro/EFM32<FAMILY>/Include/efm32<family>_cmu.h
|
||||
For devices without a full configuration of the peripheral, the definitions
|
||||
are kept in the part specific header file.
|
||||
|
||||
- System files moved to family specific "Source" folder
|
||||
CMSIS/CM3/DeviceSupport/EFM32/system_efm32.c
|
||||
-> Device/EnergyMicro/EFM32<FAMILY>/Source/system_efm32<family>.c
|
||||
|
||||
- Startup files moved to family specific "Source" folder
|
||||
CMSIS/CM3/DeviceSupport/EFM32/startup/iar/
|
||||
-> Device/EnergyMicro/EFM32<FAMILY>/Source/IAR
|
||||
CMSIS/CM3/DeviceSupport/EFM32/startup/arm/
|
||||
-> Device/EnergyMicro/EFM32<FAMILY>/Source/ARM
|
||||
CMSIS/CM3/DeviceSupport/EFM32/startup/cs3/
|
||||
-> Device/EnergyMicro/EFM32<FAMILY>/Source/G++
|
||||
|
||||
- Additional "generic GCC" (such as https://launchpad.net/gcc-arm-embedded or
|
||||
http://www.yagarto.de) target startup/linker files
|
||||
-> Device/EnergyMicro/EFM32<FAMILY>/Source/GCC
|
||||
|
||||
- Gecko startup file has got a "g" (for Gecko family) appended to filename,
|
||||
i.e. startup_efm32g.s, not startup_efm32.s as earlier. Similar for linker
|
||||
files.
|
||||
|
||||
- "efm32lib" has been renamed "emlib" as it will support future Energy Micro
|
||||
devices that are not in the EFM32 families. You will need to change all
|
||||
include files starting with
|
||||
#include "efm32_<peripheral>.h" -> #include "em_<peripheral>.h"
|
||||
in your source code. APIs within peripherals are compatible with earlier
|
||||
"efm32lib" releases.
|
||||
Also see emlib/Changes_emlib.txt file for further updates.
|
||||
|
||||
- "efm32usb" folder has been renamed to just "usb" for the same reasons as
|
||||
the peripheral library, and all files are now prefixed em_usb.
|
||||
Change all header file references from
|
||||
efm32_usb<component>.h -> em_usb<component.h>
|
||||
Also see usb/Changes_usb.txt for further updates.
|
||||
|
||||
2.4.1:
|
||||
- New, open source friendly license for all core support files in CMSIS
|
||||
and efm32lib (efm32usb keeps original license)
|
||||
- Giant/Leopard Gecko Removed USBC_PRESENT from devices not having USB
|
||||
- Giant/Leopard Gecko EMU BOD calibration registers for Backup Domain
|
||||
- Giant/Leopard Gecko USB VBUSENCAP/DMPUAP_LOW and HIGH was inverted
|
||||
- Giant/Leopard Gecko MSC BUSSTRATEGY_DMAEM2 define corrected to DMAEM1
|
||||
- Giant/Leopard Gecko CMU, added HFXO boost constants
|
||||
- Giant/Leopard Gecko CMU changed naming of HFCLK for USBC to HFCLKNODIV
|
||||
- Updated efm32lib with fixes, see Changes file in efm32lib folder
|
||||
|
||||
2.4.0:
|
||||
- Removed unused OPAMP_TypeDef for Tiny Gecko
|
||||
- Added OPAMP_PRESENT/COUNT for Giant Gecko
|
||||
- efm32lib updates, see Changes file in efm32lib folder
|
||||
- efm32usb updates, see Changes filr in efm32usb folder
|
||||
|
||||
2.3.2:
|
||||
- Fixed IAR startup files, corrected alignment of interrupt vector table
|
||||
- Updated efm32usb library with fixes
|
||||
- Updated efm32lib with new Tiny Gecko and Giant Gecko features
|
||||
|
||||
2.3.0:
|
||||
- Added DEVICE_FAMILY defines to identify Gecko/Tiny/Leopard/Giant parts
|
||||
- Fixed missing EMU_IRQ definitions in Leopard Gecko startup files
|
||||
- Added USART location to Tiny Gecko parts
|
||||
- Added LEUART locations to Tiny Gecko parts
|
||||
- Updated efm32lib with new Giant Gecko features (see separate readme)
|
||||
- Updated efm32usb with USB Host stack support (see separate readme)
|
||||
|
||||
2.2.2:
|
||||
- Removed huge AF_PORT, AF_PIN macros from header files, only peripheral
|
||||
specific alternate function defines are included
|
||||
- Updated efm32usb library with fixes
|
||||
- Updated efm32lib library with fixes
|
||||
|
||||
2.2.1:
|
||||
- Added interleave to all Giant Gecko parts
|
||||
- Updated efm32lib with more Giant Gecko features
|
||||
- Added efm32usb, USB Device stack for Giant Gecko USB parts
|
||||
- Added LOCATION defines for all I2C alternate locations on Tiny Gecko
|
||||
|
||||
2.1.1:
|
||||
- Added header files for Giant Gecko and Leopard Gecko devices
|
||||
- Minor fix for Gecko devices, EMU_CTRL_MASK was wrong
|
||||
- Fix for linker issue alignment of .data section in codesourcery .ld files
|
||||
|
||||
2.0.1:
|
||||
- DAC_OPAnMUX_POSSEL_OPAnIN changed to DAC_OPAnMUX_POSSEL_OPAnINP for Tiny
|
||||
Gecko
|
||||
- Added CMU_ROUTE_LOCATION, LOC2 for Tiny Gecko
|
||||
- PRS #define fixes, remove extra IRDA fields only available on USART0
|
||||
|
||||
2.0.0:
|
||||
- This release based on CMSIS_2_00, includes DSP_Lib (for Keil MDKARM, IAR has
|
||||
a port included with EWARM)
|
||||
- Removed "shadow" example that used to be in CMSIS directory earlier, use
|
||||
"blink" from board examples as starting point instead
|
||||
- Restructured header files to comply with CMSIS_2_00
|
||||
- CMU_CALCTRL_REFSEL is renamed to CMU_CALCTRL_UPSEL to match reference
|
||||
manual and clearify new DOWNSEL calibrartion features for Tiny Gecko
|
||||
- Added header files for new package types for Gecko devices
|
||||
- Added header files for Tiny Gecko devices
|
||||
|
||||
1.3.0:
|
||||
- DMA register WAITSTATUS changed to CHWAITSTATUS for consistency
|
||||
DMA test req/sreq registers added, CHSREQSTATUS and CHREQSTATUS
|
||||
- IFS and IFC interrupt registers are now marked as readable for several
|
||||
peripherals
|
||||
- TIMER, CCC renamed to CDTI
|
||||
- TIMER, QEM has been renamed to QDM
|
||||
- AF_DBG_SWV/TCLK/TDIO renamed to more commonly used AF_DBG_SWD/SWDIO/SWDCLK
|
||||
- AF_EBI_ADDRDAT renamed to AF_EBI_AD
|
||||
- Removed bit fields for extra LCD segment registers for Gecko parts
|
||||
- Fixed LCD_SEGEN_MASK, bit width was too narrow in version 1.2.x
|
||||
- Fixed LCD_SYNCBUSY bit fields
|
||||
- CMU_PCNTCTRL reset values corrected
|
||||
- PCNT_TOP and PCNT_TOPB reset values corrected
|
||||
- ADC_LPFMODE_RCFILT and LPFMOD_DECAP definitions corrected (they were
|
||||
reversed)
|
||||
- USART_RXDATAFULLRIGHT and USART_RXDATAVRIGHT removed for Gecko parts
|
||||
- GPIO, renamed INSENSE_PRSSENSE to INSENSE_PRS, similar for INT
|
||||
to be consistent with updated documentation (Reference Manual)
|
||||
|
||||
1.2.1:
|
||||
- Fixed DEVINFO calibration shift and mask value for temperature sensor
|
||||
fixed in rev.C Gecko devices
|
||||
|
||||
1.2.0:
|
||||
- Added new subgroup "Parts" for all part definitions in doxygen format
|
||||
- Removed unused _PARAM_ type definitions, less clutter in header files
|
||||
- _CMU_PCNTCTRL_RESETVALUE corrected
|
||||
- Added C startup file for IAR, can be used as replacement for assembly file
|
||||
- Use #defines instead of "numeric values reentered" in bit field definitions
|
||||
- TIMER_PARAM_CCNUM(i) changed to TIMER_PARAM_CC_NUM(i)
|
||||
- DPI_CHAN_COUNT changed to PRS_CHAN_COUNT
|
||||
|
||||
1.1.4:
|
||||
- TIMER_INIT_DEFAULT fix to efm32lib
|
||||
|
||||
1.1.3:
|
||||
- Removed ADC ROUTE register
|
||||
- Renamed DEVINFO DACCAL -> DAC0CAL for all 3 calibration registers and bit
|
||||
fields
|
||||
- Updated efm32lib with new peripherals
|
||||
|
||||
1.1.2:
|
||||
- Added support for CodeSourcery Sourcery G++ compiler and startup files
|
||||
- Device Information page (DEVINFO_TypeDef) - fixed several issues with
|
||||
endianness, and other changes to support test revision 4 and above parts.
|
||||
This has led to a small incompatibilty with test rev <= 4 and rev A parts,
|
||||
in that the flash and sram size bit fields has changed location.
|
||||
- DMA_CONTROL_TypeDef changed name to DMA_DESCRIPTOR_TypeDef to be better
|
||||
aligned with PL230 manual and code
|
||||
- DMA bit fields not supported on EFM32 was removed for the PL230 controller
|
||||
- DMA CTRL bit fields renamed to be more consistent with PL230 TRM manual
|
||||
- Added additional volatile statements to pointers in DMA Control structure
|
||||
- Fixed several registers that were readable, and was marked as __O (output
|
||||
only)
|
||||
|
||||
1.1.1:
|
||||
- Fixed startup code, CMSIS SystemInit cannot update global variable
|
||||
|
||||
1.1.0:
|
||||
- Note - some register bit field updates in this release are _not_ backward
|
||||
compatible
|
||||
- Updated register bit fields to comply with documentation updates, i.e.
|
||||
reference manual version > 0.83
|
||||
- Apply patch to CMSIS core for GCC issues
|
||||
- Added DMA_CONTROL_TypeDef control block for PrimeCell PL230 DMA controller
|
||||
- Added ROMTABLE PID / CHIP revision table and masks
|
||||
- Revised and updated Device Information page structure "DEVINFO page"
|
||||
This structure is ONLY valid for rev.B production devices
|
||||
- GPIO EXTIPSEL bit field marked "16" changed to 15 (bug correction)
|
||||
- Added more bit fields to TIMER_ROUTE registers
|
||||
- Cosmetic updates in doxygen comments and copyright statements
|
||||
|
||||
1.0.4:
|
||||
- ACMP INPUTSEL bit fields changed from ohm rating to res-n,
|
||||
- Added bit-band base addresses for peripherals and sram
|
||||
|
||||
1.0.3:
|
||||
- ADC SCANMODE and SCANCTRL bit field updates and corrections
|
||||
- Moved Readme.txt and Changes.txt to CMSIS/Readme-EFM32.txt and
|
||||
CMSIS/Changes-EFM32.txt
|
||||
- CCPEN and CDTIPEN splitted in TIMER_ROUTE
|
||||
- EMVREG in EMU_CTRL enumeration changed
|
||||
- LCD DISPCTRL volatage levels are part specific, changed settings changed to
|
||||
reflect this
|
||||
- Added "UL" (unsigned long) to some bit fields giving warnings due to sign
|
||||
conversion
|
||||
|
||||
1.0.2:
|
||||
- Corrected revision numbers in file headers
|
||||
- Removed example code that was moved into BSP/DVK installer package
|
||||
|
||||
1.0.1:
|
||||
- Updated to use official CMSIS1V30 release
|
||||
- Corrected IRQ vector table in assembly startup files, IMEM to MSC,
|
||||
UDMA to DMA
|
||||
- DMA peripheral/signal names corrected
|
||||
- Example Blinky application updated to work on all EFM32 MCU-Modules on DVK
|
||||
- Added "simple" board support package to example
|
||||
- Added "UL" (unsigned long) tag to several fields
|
||||
|
||||
1.0.0:
|
||||
- Initial release
|
||||
- Includes CMSIS1V30 2nd PreRelease
|
||||
- Now requires two include paths, CMSIS/CM3/DeviceSupport/EnergyMicro/EFM32 and
|
||||
CMSIS/CM3/CoreSupport
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief CMSIS Cortex Peripheral Access Layer for EFM32 device series
|
||||
*
|
||||
* This is a convenience header file for defining the EFM32 part number on the
|
||||
* build command line, instead of specifying the part specific header file.
|
||||
* @verbatim
|
||||
* Example: Add "-DEFM32G890F128" to your build options, to define part
|
||||
* Add "#include "efm32.h" to your source files
|
||||
* @endverbatim
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __EFM32_H
|
||||
#define __EFM32_H
|
||||
|
||||
/* This file is kept for backwards compability. */
|
||||
|
||||
#include "em_device.h"
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,416 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G880F128
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __EFM32G880F128_H
|
||||
#define __EFM32G880F128_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128 EFM32G880F128
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers *******************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
|
||||
|
||||
/****** EFM32G Peripheral Interrupt Numbers **********************************************/
|
||||
DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */
|
||||
ACMP0_IRQn = 5, /*!< 16+5 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 6, /*!< 16+6 EFM32 ADC0 Interrupt */
|
||||
DAC0_IRQn = 7, /*!< 16+7 EFM32 DAC0 Interrupt */
|
||||
I2C0_IRQn = 8, /*!< 16+8 EFM32 I2C0 Interrupt */
|
||||
GPIO_ODD_IRQn = 9, /*!< 16+9 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 10, /*!< 16+10 EFM32 TIMER1 Interrupt */
|
||||
TIMER2_IRQn = 11, /*!< 16+11 EFM32 TIMER2 Interrupt */
|
||||
USART1_RX_IRQn = 12, /*!< 16+12 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 13, /*!< 16+13 EFM32 USART1_TX Interrupt */
|
||||
USART2_RX_IRQn = 14, /*!< 16+14 EFM32 USART2_RX Interrupt */
|
||||
USART2_TX_IRQn = 15, /*!< 16+15 EFM32 USART2_TX Interrupt */
|
||||
UART0_RX_IRQn = 16, /*!< 16+16 EFM32 UART0_RX Interrupt */
|
||||
UART0_TX_IRQn = 17, /*!< 16+17 EFM32 UART0_TX Interrupt */
|
||||
LEUART0_IRQn = 18, /*!< 16+18 EFM32 LEUART0 Interrupt */
|
||||
LEUART1_IRQn = 19, /*!< 16+19 EFM32 LEUART1 Interrupt */
|
||||
LETIMER0_IRQn = 20, /*!< 16+20 EFM32 LETIMER0 Interrupt */
|
||||
PCNT0_IRQn = 21, /*!< 16+21 EFM32 PCNT0 Interrupt */
|
||||
PCNT1_IRQn = 22, /*!< 16+22 EFM32 PCNT1 Interrupt */
|
||||
PCNT2_IRQn = 23, /*!< 16+23 EFM32 PCNT2 Interrupt */
|
||||
RTC_IRQn = 24, /*!< 16+24 EFM32 RTC Interrupt */
|
||||
CMU_IRQn = 25, /*!< 16+25 EFM32 CMU Interrupt */
|
||||
VCMP_IRQn = 26, /*!< 16+26 EFM32 VCMP Interrupt */
|
||||
LCD_IRQn = 27, /*!< 16+27 EFM32 LCD Interrupt */
|
||||
MSC_IRQn = 28, /*!< 16+28 EFM32 MSC Interrupt */
|
||||
AES_IRQn = 29, /*!< 16+29 EFM32 AES Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_Core EFM32G880F128 Core
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
|
||||
|
||||
/** @} End of group EFM32G880F128_Core */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_Part EFM32G880F128 Part
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/** Part family */
|
||||
#define _EFM32_GECKO_FAMILY 1 /**< Gecko EFM32G MCU Family */
|
||||
#define _EFM_DEVICE /**< Energy Micro EFM-type microcontroller */
|
||||
|
||||
/* If part number is not defined as compiler option, define it */
|
||||
#if !defined(EFM32G880F128)
|
||||
#define EFM32G880F128 1 /**< Gecko Part */
|
||||
#endif
|
||||
|
||||
/** Configure part number */
|
||||
#define PART_NUMBER "EFM32G880F128" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G880F128 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
#define FLASH_SIZE (0x00020000UL) /**< Available Flash Memory */
|
||||
#define FLASH_PAGE_SIZE 512 /**< Flash Memory page size */
|
||||
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
|
||||
#define SRAM_SIZE (0x00004000UL) /**< Available SRAM Memory */
|
||||
#define __CM3_REV 0x200 /**< Cortex-M3 Core revision r2p0 */
|
||||
#define PRS_CHAN_COUNT 8 /**< Number of PRS channels */
|
||||
#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
|
||||
|
||||
/** AF channels connect the different on-chip peripherals with the af-mux */
|
||||
#define AFCHAN_MAX 79
|
||||
#define AFCHANLOC_MAX 4
|
||||
/** Analog AF channels */
|
||||
#define AFACHAN_MAX 37
|
||||
|
||||
/* Part number capabilities */
|
||||
|
||||
#define TIMER_PRESENT /**< TIMER is available in this part */
|
||||
#define TIMER_COUNT 3 /**< 3 TIMERs available */
|
||||
#define USART_PRESENT /**< USART is available in this part */
|
||||
#define USART_COUNT 3 /**< 3 USARTs available */
|
||||
#define UART_PRESENT /**< UART is available in this part */
|
||||
#define UART_COUNT 1 /**< 1 UARTs available */
|
||||
#define LEUART_PRESENT /**< LEUART is available in this part */
|
||||
#define LEUART_COUNT 2 /**< 2 LEUARTs available */
|
||||
#define LETIMER_PRESENT /**< LETIMER is available in this part */
|
||||
#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
|
||||
#define PCNT_PRESENT /**< PCNT is available in this part */
|
||||
#define PCNT_COUNT 3 /**< 3 PCNTs available */
|
||||
#define I2C_PRESENT /**< I2C is available in this part */
|
||||
#define I2C_COUNT 1 /**< 1 I2Cs available */
|
||||
#define ADC_PRESENT /**< ADC is available in this part */
|
||||
#define ADC_COUNT 1 /**< 1 ADCs available */
|
||||
#define DAC_PRESENT /**< DAC is available in this part */
|
||||
#define DAC_COUNT 1 /**< 1 DACs available */
|
||||
#define ACMP_PRESENT /**< ACMP is available in this part */
|
||||
#define ACMP_COUNT 2 /**< 2 ACMPs available */
|
||||
#define LE_PRESENT
|
||||
#define LE_COUNT 1
|
||||
#define MSC_PRESENT
|
||||
#define MSC_COUNT 1
|
||||
#define EMU_PRESENT
|
||||
#define EMU_COUNT 1
|
||||
#define RMU_PRESENT
|
||||
#define RMU_COUNT 1
|
||||
#define CMU_PRESENT
|
||||
#define CMU_COUNT 1
|
||||
#define AES_PRESENT
|
||||
#define AES_COUNT 1
|
||||
#define EBI_PRESENT
|
||||
#define EBI_COUNT 1
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
#define PRS_PRESENT
|
||||
#define PRS_COUNT 1
|
||||
#define DMA_PRESENT
|
||||
#define DMA_COUNT 1
|
||||
#define VCMP_PRESENT
|
||||
#define VCMP_COUNT 1
|
||||
#define LCD_PRESENT
|
||||
#define LCD_COUNT 1
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 1
|
||||
#define HFXTAL_PRESENT
|
||||
#define HFXTAL_COUNT 1
|
||||
#define LFXTAL_PRESENT
|
||||
#define LFXTAL_COUNT 1
|
||||
#define WDOG_PRESENT
|
||||
#define WDOG_COUNT 1
|
||||
#define DBG_PRESENT
|
||||
#define DBG_COUNT 1
|
||||
|
||||
#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
|
||||
#include "system_efm32g.h" /* System Header */
|
||||
|
||||
/** @} End of group EFM32G880F128_Part */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_Peripheral_TypeDefs EFM32G880F128 Peripheral TypeDefs
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32g_msc.h"
|
||||
#include "efm32g_emu.h"
|
||||
#include "efm32g_rmu.h"
|
||||
#include "efm32g_cmu.h"
|
||||
#include "efm32g_aes.h"
|
||||
#include "efm32g_ebi.h"
|
||||
#include "efm32g_gpio_p.h"
|
||||
#include "efm32g_gpio.h"
|
||||
#include "efm32g_prs_ch.h"
|
||||
#include "efm32g_prs.h"
|
||||
#include "efm32g_dma_ch.h"
|
||||
#include "efm32g_dma.h"
|
||||
#include "efm32g_timer_cc.h"
|
||||
#include "efm32g_timer.h"
|
||||
#include "efm32g_usart.h"
|
||||
#include "efm32g_leuart.h"
|
||||
#include "efm32g_letimer.h"
|
||||
#include "efm32g_pcnt.h"
|
||||
#include "efm32g_i2c.h"
|
||||
#include "efm32g_adc.h"
|
||||
#include "efm32g_dac.h"
|
||||
#include "efm32g_acmp.h"
|
||||
#include "efm32g_vcmp.h"
|
||||
#include "efm32g_lcd.h"
|
||||
#include "efm32g_rtc.h"
|
||||
#include "efm32g_wdog.h"
|
||||
#include "efm32g_dma_descriptor.h"
|
||||
#include "efm32g_devinfo.h"
|
||||
#include "efm32g_romtable.h"
|
||||
#include "efm32g_calibrate.h"
|
||||
|
||||
/** @} End of group EFM32G880F128_Peripheral_TypeDefs */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_Peripheral_Base EFM32G880F128 Peripheral Memory Map
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC_BASE (0x400C0000UL) /**< MSC base address */
|
||||
#define EMU_BASE (0x400C6000UL) /**< EMU base address */
|
||||
#define RMU_BASE (0x400CA000UL) /**< RMU base address */
|
||||
#define CMU_BASE (0x400C8000UL) /**< CMU base address */
|
||||
#define AES_BASE (0x400E0000UL) /**< AES base address */
|
||||
#define EBI_BASE (0x40008000UL) /**< EBI base address */
|
||||
#define GPIO_BASE (0x40006000UL) /**< GPIO base address */
|
||||
#define PRS_BASE (0x400CC000UL) /**< PRS base address */
|
||||
#define DMA_BASE (0x400C2000UL) /**< DMA base address */
|
||||
#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
|
||||
#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
|
||||
#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
|
||||
#define USART0_BASE (0x4000C000UL) /**< USART0 base address */
|
||||
#define USART1_BASE (0x4000C400UL) /**< USART1 base address */
|
||||
#define USART2_BASE (0x4000C800UL) /**< USART2 base address */
|
||||
#define UART0_BASE (0x4000E000UL) /**< UART0 base address */
|
||||
#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
|
||||
#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
|
||||
#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
|
||||
#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
|
||||
#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
|
||||
#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
|
||||
#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
|
||||
#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
|
||||
#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
|
||||
#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
|
||||
#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
|
||||
#define VCMP_BASE (0x40000000UL) /**< VCMP base address */
|
||||
#define LCD_BASE (0x4008A000UL) /**< LCD base address */
|
||||
#define RTC_BASE (0x40080000UL) /**< RTC base address */
|
||||
#define WDOG_BASE (0x40088000UL) /**< WDOG base address */
|
||||
#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
|
||||
#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
|
||||
#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
|
||||
|
||||
/** @} End of group EFM32G880F128_Peripheral_Base */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_Peripheral_Declaration EFM32G880F128 Peripheral Declarations
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G880F128_Peripheral_Declaration */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_BitFields EFM32G880F128 Bit Fields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32g_prs_signals.h"
|
||||
#include "efm32g_dmareq.h"
|
||||
#include "efm32g_dmactrl.h"
|
||||
#include "efm32g_uart.h"
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_UNLOCK EFM32G880F128 Unlock Codes
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
||||
/** @} End of group EFM32G880F128_UNLOCK */
|
||||
|
||||
/** @} End of group EFM32G880F128_BitFields */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F128_Alternate_Function EFM32G880F128 Alternate Function
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32g_af_ports.h"
|
||||
#include "efm32g_af_pins.h"
|
||||
|
||||
/** @} End of group EFM32G880F128_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @brief Set the value of a bit field within a register.
|
||||
*
|
||||
* @param REG
|
||||
* The register to update
|
||||
* @param MASK
|
||||
* The mask for the bit field to update
|
||||
* @param VALUE
|
||||
* The value to write to the bit field
|
||||
* @param OFFSET
|
||||
* The number of bits that the field is offset within the register.
|
||||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G880F128 */
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __EFM32G880F128_H */
|
||||
|
|
@ -0,0 +1,416 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G880F32
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __EFM32G880F32_H
|
||||
#define __EFM32G880F32_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32 EFM32G880F32
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers *******************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
|
||||
|
||||
/****** EFM32G Peripheral Interrupt Numbers **********************************************/
|
||||
DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */
|
||||
ACMP0_IRQn = 5, /*!< 16+5 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 6, /*!< 16+6 EFM32 ADC0 Interrupt */
|
||||
DAC0_IRQn = 7, /*!< 16+7 EFM32 DAC0 Interrupt */
|
||||
I2C0_IRQn = 8, /*!< 16+8 EFM32 I2C0 Interrupt */
|
||||
GPIO_ODD_IRQn = 9, /*!< 16+9 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 10, /*!< 16+10 EFM32 TIMER1 Interrupt */
|
||||
TIMER2_IRQn = 11, /*!< 16+11 EFM32 TIMER2 Interrupt */
|
||||
USART1_RX_IRQn = 12, /*!< 16+12 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 13, /*!< 16+13 EFM32 USART1_TX Interrupt */
|
||||
USART2_RX_IRQn = 14, /*!< 16+14 EFM32 USART2_RX Interrupt */
|
||||
USART2_TX_IRQn = 15, /*!< 16+15 EFM32 USART2_TX Interrupt */
|
||||
UART0_RX_IRQn = 16, /*!< 16+16 EFM32 UART0_RX Interrupt */
|
||||
UART0_TX_IRQn = 17, /*!< 16+17 EFM32 UART0_TX Interrupt */
|
||||
LEUART0_IRQn = 18, /*!< 16+18 EFM32 LEUART0 Interrupt */
|
||||
LEUART1_IRQn = 19, /*!< 16+19 EFM32 LEUART1 Interrupt */
|
||||
LETIMER0_IRQn = 20, /*!< 16+20 EFM32 LETIMER0 Interrupt */
|
||||
PCNT0_IRQn = 21, /*!< 16+21 EFM32 PCNT0 Interrupt */
|
||||
PCNT1_IRQn = 22, /*!< 16+22 EFM32 PCNT1 Interrupt */
|
||||
PCNT2_IRQn = 23, /*!< 16+23 EFM32 PCNT2 Interrupt */
|
||||
RTC_IRQn = 24, /*!< 16+24 EFM32 RTC Interrupt */
|
||||
CMU_IRQn = 25, /*!< 16+25 EFM32 CMU Interrupt */
|
||||
VCMP_IRQn = 26, /*!< 16+26 EFM32 VCMP Interrupt */
|
||||
LCD_IRQn = 27, /*!< 16+27 EFM32 LCD Interrupt */
|
||||
MSC_IRQn = 28, /*!< 16+28 EFM32 MSC Interrupt */
|
||||
AES_IRQn = 29, /*!< 16+29 EFM32 AES Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_Core EFM32G880F32 Core
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
|
||||
|
||||
/** @} End of group EFM32G880F32_Core */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_Part EFM32G880F32 Part
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/** Part family */
|
||||
#define _EFM32_GECKO_FAMILY 1 /**< Gecko EFM32G MCU Family */
|
||||
#define _EFM_DEVICE /**< Energy Micro EFM-type microcontroller */
|
||||
|
||||
/* If part number is not defined as compiler option, define it */
|
||||
#if !defined(EFM32G880F32)
|
||||
#define EFM32G880F32 1 /**< Gecko Part */
|
||||
#endif
|
||||
|
||||
/** Configure part number */
|
||||
#define PART_NUMBER "EFM32G880F32" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G880F32 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
#define FLASH_SIZE (0x00008000UL) /**< Available Flash Memory */
|
||||
#define FLASH_PAGE_SIZE 512 /**< Flash Memory page size */
|
||||
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
|
||||
#define SRAM_SIZE (0x00002000UL) /**< Available SRAM Memory */
|
||||
#define __CM3_REV 0x200 /**< Cortex-M3 Core revision r2p0 */
|
||||
#define PRS_CHAN_COUNT 8 /**< Number of PRS channels */
|
||||
#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
|
||||
|
||||
/** AF channels connect the different on-chip peripherals with the af-mux */
|
||||
#define AFCHAN_MAX 79
|
||||
#define AFCHANLOC_MAX 4
|
||||
/** Analog AF channels */
|
||||
#define AFACHAN_MAX 37
|
||||
|
||||
/* Part number capabilities */
|
||||
|
||||
#define TIMER_PRESENT /**< TIMER is available in this part */
|
||||
#define TIMER_COUNT 3 /**< 3 TIMERs available */
|
||||
#define USART_PRESENT /**< USART is available in this part */
|
||||
#define USART_COUNT 3 /**< 3 USARTs available */
|
||||
#define UART_PRESENT /**< UART is available in this part */
|
||||
#define UART_COUNT 1 /**< 1 UARTs available */
|
||||
#define LEUART_PRESENT /**< LEUART is available in this part */
|
||||
#define LEUART_COUNT 2 /**< 2 LEUARTs available */
|
||||
#define LETIMER_PRESENT /**< LETIMER is available in this part */
|
||||
#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
|
||||
#define PCNT_PRESENT /**< PCNT is available in this part */
|
||||
#define PCNT_COUNT 3 /**< 3 PCNTs available */
|
||||
#define I2C_PRESENT /**< I2C is available in this part */
|
||||
#define I2C_COUNT 1 /**< 1 I2Cs available */
|
||||
#define ADC_PRESENT /**< ADC is available in this part */
|
||||
#define ADC_COUNT 1 /**< 1 ADCs available */
|
||||
#define DAC_PRESENT /**< DAC is available in this part */
|
||||
#define DAC_COUNT 1 /**< 1 DACs available */
|
||||
#define ACMP_PRESENT /**< ACMP is available in this part */
|
||||
#define ACMP_COUNT 2 /**< 2 ACMPs available */
|
||||
#define LE_PRESENT
|
||||
#define LE_COUNT 1
|
||||
#define MSC_PRESENT
|
||||
#define MSC_COUNT 1
|
||||
#define EMU_PRESENT
|
||||
#define EMU_COUNT 1
|
||||
#define RMU_PRESENT
|
||||
#define RMU_COUNT 1
|
||||
#define CMU_PRESENT
|
||||
#define CMU_COUNT 1
|
||||
#define AES_PRESENT
|
||||
#define AES_COUNT 1
|
||||
#define EBI_PRESENT
|
||||
#define EBI_COUNT 1
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
#define PRS_PRESENT
|
||||
#define PRS_COUNT 1
|
||||
#define DMA_PRESENT
|
||||
#define DMA_COUNT 1
|
||||
#define VCMP_PRESENT
|
||||
#define VCMP_COUNT 1
|
||||
#define LCD_PRESENT
|
||||
#define LCD_COUNT 1
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 1
|
||||
#define HFXTAL_PRESENT
|
||||
#define HFXTAL_COUNT 1
|
||||
#define LFXTAL_PRESENT
|
||||
#define LFXTAL_COUNT 1
|
||||
#define WDOG_PRESENT
|
||||
#define WDOG_COUNT 1
|
||||
#define DBG_PRESENT
|
||||
#define DBG_COUNT 1
|
||||
|
||||
#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
|
||||
#include "system_efm32g.h" /* System Header */
|
||||
|
||||
/** @} End of group EFM32G880F32_Part */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_Peripheral_TypeDefs EFM32G880F32 Peripheral TypeDefs
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32g_msc.h"
|
||||
#include "efm32g_emu.h"
|
||||
#include "efm32g_rmu.h"
|
||||
#include "efm32g_cmu.h"
|
||||
#include "efm32g_aes.h"
|
||||
#include "efm32g_ebi.h"
|
||||
#include "efm32g_gpio_p.h"
|
||||
#include "efm32g_gpio.h"
|
||||
#include "efm32g_prs_ch.h"
|
||||
#include "efm32g_prs.h"
|
||||
#include "efm32g_dma_ch.h"
|
||||
#include "efm32g_dma.h"
|
||||
#include "efm32g_timer_cc.h"
|
||||
#include "efm32g_timer.h"
|
||||
#include "efm32g_usart.h"
|
||||
#include "efm32g_leuart.h"
|
||||
#include "efm32g_letimer.h"
|
||||
#include "efm32g_pcnt.h"
|
||||
#include "efm32g_i2c.h"
|
||||
#include "efm32g_adc.h"
|
||||
#include "efm32g_dac.h"
|
||||
#include "efm32g_acmp.h"
|
||||
#include "efm32g_vcmp.h"
|
||||
#include "efm32g_lcd.h"
|
||||
#include "efm32g_rtc.h"
|
||||
#include "efm32g_wdog.h"
|
||||
#include "efm32g_dma_descriptor.h"
|
||||
#include "efm32g_devinfo.h"
|
||||
#include "efm32g_romtable.h"
|
||||
#include "efm32g_calibrate.h"
|
||||
|
||||
/** @} End of group EFM32G880F32_Peripheral_TypeDefs */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_Peripheral_Base EFM32G880F32 Peripheral Memory Map
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC_BASE (0x400C0000UL) /**< MSC base address */
|
||||
#define EMU_BASE (0x400C6000UL) /**< EMU base address */
|
||||
#define RMU_BASE (0x400CA000UL) /**< RMU base address */
|
||||
#define CMU_BASE (0x400C8000UL) /**< CMU base address */
|
||||
#define AES_BASE (0x400E0000UL) /**< AES base address */
|
||||
#define EBI_BASE (0x40008000UL) /**< EBI base address */
|
||||
#define GPIO_BASE (0x40006000UL) /**< GPIO base address */
|
||||
#define PRS_BASE (0x400CC000UL) /**< PRS base address */
|
||||
#define DMA_BASE (0x400C2000UL) /**< DMA base address */
|
||||
#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
|
||||
#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
|
||||
#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
|
||||
#define USART0_BASE (0x4000C000UL) /**< USART0 base address */
|
||||
#define USART1_BASE (0x4000C400UL) /**< USART1 base address */
|
||||
#define USART2_BASE (0x4000C800UL) /**< USART2 base address */
|
||||
#define UART0_BASE (0x4000E000UL) /**< UART0 base address */
|
||||
#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
|
||||
#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
|
||||
#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
|
||||
#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
|
||||
#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
|
||||
#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
|
||||
#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
|
||||
#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
|
||||
#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
|
||||
#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
|
||||
#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
|
||||
#define VCMP_BASE (0x40000000UL) /**< VCMP base address */
|
||||
#define LCD_BASE (0x4008A000UL) /**< LCD base address */
|
||||
#define RTC_BASE (0x40080000UL) /**< RTC base address */
|
||||
#define WDOG_BASE (0x40088000UL) /**< WDOG base address */
|
||||
#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
|
||||
#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
|
||||
#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
|
||||
|
||||
/** @} End of group EFM32G880F32_Peripheral_Base */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_Peripheral_Declaration EFM32G880F32 Peripheral Declarations
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G880F32_Peripheral_Declaration */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_BitFields EFM32G880F32 Bit Fields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32g_prs_signals.h"
|
||||
#include "efm32g_dmareq.h"
|
||||
#include "efm32g_dmactrl.h"
|
||||
#include "efm32g_uart.h"
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_UNLOCK EFM32G880F32 Unlock Codes
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
||||
/** @} End of group EFM32G880F32_UNLOCK */
|
||||
|
||||
/** @} End of group EFM32G880F32_BitFields */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F32_Alternate_Function EFM32G880F32 Alternate Function
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32g_af_ports.h"
|
||||
#include "efm32g_af_pins.h"
|
||||
|
||||
/** @} End of group EFM32G880F32_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @brief Set the value of a bit field within a register.
|
||||
*
|
||||
* @param REG
|
||||
* The register to update
|
||||
* @param MASK
|
||||
* The mask for the bit field to update
|
||||
* @param VALUE
|
||||
* The value to write to the bit field
|
||||
* @param OFFSET
|
||||
* The number of bits that the field is offset within the register.
|
||||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G880F32 */
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __EFM32G880F32_H */
|
||||
|
|
@ -0,0 +1,416 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G880F64
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __EFM32G880F64_H
|
||||
#define __EFM32G880F64_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64 EFM32G880F64
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers *******************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
|
||||
|
||||
/****** EFM32G Peripheral Interrupt Numbers **********************************************/
|
||||
DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */
|
||||
ACMP0_IRQn = 5, /*!< 16+5 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 6, /*!< 16+6 EFM32 ADC0 Interrupt */
|
||||
DAC0_IRQn = 7, /*!< 16+7 EFM32 DAC0 Interrupt */
|
||||
I2C0_IRQn = 8, /*!< 16+8 EFM32 I2C0 Interrupt */
|
||||
GPIO_ODD_IRQn = 9, /*!< 16+9 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 10, /*!< 16+10 EFM32 TIMER1 Interrupt */
|
||||
TIMER2_IRQn = 11, /*!< 16+11 EFM32 TIMER2 Interrupt */
|
||||
USART1_RX_IRQn = 12, /*!< 16+12 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 13, /*!< 16+13 EFM32 USART1_TX Interrupt */
|
||||
USART2_RX_IRQn = 14, /*!< 16+14 EFM32 USART2_RX Interrupt */
|
||||
USART2_TX_IRQn = 15, /*!< 16+15 EFM32 USART2_TX Interrupt */
|
||||
UART0_RX_IRQn = 16, /*!< 16+16 EFM32 UART0_RX Interrupt */
|
||||
UART0_TX_IRQn = 17, /*!< 16+17 EFM32 UART0_TX Interrupt */
|
||||
LEUART0_IRQn = 18, /*!< 16+18 EFM32 LEUART0 Interrupt */
|
||||
LEUART1_IRQn = 19, /*!< 16+19 EFM32 LEUART1 Interrupt */
|
||||
LETIMER0_IRQn = 20, /*!< 16+20 EFM32 LETIMER0 Interrupt */
|
||||
PCNT0_IRQn = 21, /*!< 16+21 EFM32 PCNT0 Interrupt */
|
||||
PCNT1_IRQn = 22, /*!< 16+22 EFM32 PCNT1 Interrupt */
|
||||
PCNT2_IRQn = 23, /*!< 16+23 EFM32 PCNT2 Interrupt */
|
||||
RTC_IRQn = 24, /*!< 16+24 EFM32 RTC Interrupt */
|
||||
CMU_IRQn = 25, /*!< 16+25 EFM32 CMU Interrupt */
|
||||
VCMP_IRQn = 26, /*!< 16+26 EFM32 VCMP Interrupt */
|
||||
LCD_IRQn = 27, /*!< 16+27 EFM32 LCD Interrupt */
|
||||
MSC_IRQn = 28, /*!< 16+28 EFM32 MSC Interrupt */
|
||||
AES_IRQn = 29, /*!< 16+29 EFM32 AES Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_Core EFM32G880F64 Core
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
|
||||
|
||||
/** @} End of group EFM32G880F64_Core */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_Part EFM32G880F64 Part
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/** Part family */
|
||||
#define _EFM32_GECKO_FAMILY 1 /**< Gecko EFM32G MCU Family */
|
||||
#define _EFM_DEVICE /**< Energy Micro EFM-type microcontroller */
|
||||
|
||||
/* If part number is not defined as compiler option, define it */
|
||||
#if !defined(EFM32G880F64)
|
||||
#define EFM32G880F64 1 /**< Gecko Part */
|
||||
#endif
|
||||
|
||||
/** Configure part number */
|
||||
#define PART_NUMBER "EFM32G880F64" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G880F64 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
#define FLASH_SIZE (0x00010000UL) /**< Available Flash Memory */
|
||||
#define FLASH_PAGE_SIZE 512 /**< Flash Memory page size */
|
||||
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
|
||||
#define SRAM_SIZE (0x00004000UL) /**< Available SRAM Memory */
|
||||
#define __CM3_REV 0x200 /**< Cortex-M3 Core revision r2p0 */
|
||||
#define PRS_CHAN_COUNT 8 /**< Number of PRS channels */
|
||||
#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
|
||||
|
||||
/** AF channels connect the different on-chip peripherals with the af-mux */
|
||||
#define AFCHAN_MAX 79
|
||||
#define AFCHANLOC_MAX 4
|
||||
/** Analog AF channels */
|
||||
#define AFACHAN_MAX 37
|
||||
|
||||
/* Part number capabilities */
|
||||
|
||||
#define TIMER_PRESENT /**< TIMER is available in this part */
|
||||
#define TIMER_COUNT 3 /**< 3 TIMERs available */
|
||||
#define USART_PRESENT /**< USART is available in this part */
|
||||
#define USART_COUNT 3 /**< 3 USARTs available */
|
||||
#define UART_PRESENT /**< UART is available in this part */
|
||||
#define UART_COUNT 1 /**< 1 UARTs available */
|
||||
#define LEUART_PRESENT /**< LEUART is available in this part */
|
||||
#define LEUART_COUNT 2 /**< 2 LEUARTs available */
|
||||
#define LETIMER_PRESENT /**< LETIMER is available in this part */
|
||||
#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
|
||||
#define PCNT_PRESENT /**< PCNT is available in this part */
|
||||
#define PCNT_COUNT 3 /**< 3 PCNTs available */
|
||||
#define I2C_PRESENT /**< I2C is available in this part */
|
||||
#define I2C_COUNT 1 /**< 1 I2Cs available */
|
||||
#define ADC_PRESENT /**< ADC is available in this part */
|
||||
#define ADC_COUNT 1 /**< 1 ADCs available */
|
||||
#define DAC_PRESENT /**< DAC is available in this part */
|
||||
#define DAC_COUNT 1 /**< 1 DACs available */
|
||||
#define ACMP_PRESENT /**< ACMP is available in this part */
|
||||
#define ACMP_COUNT 2 /**< 2 ACMPs available */
|
||||
#define LE_PRESENT
|
||||
#define LE_COUNT 1
|
||||
#define MSC_PRESENT
|
||||
#define MSC_COUNT 1
|
||||
#define EMU_PRESENT
|
||||
#define EMU_COUNT 1
|
||||
#define RMU_PRESENT
|
||||
#define RMU_COUNT 1
|
||||
#define CMU_PRESENT
|
||||
#define CMU_COUNT 1
|
||||
#define AES_PRESENT
|
||||
#define AES_COUNT 1
|
||||
#define EBI_PRESENT
|
||||
#define EBI_COUNT 1
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
#define PRS_PRESENT
|
||||
#define PRS_COUNT 1
|
||||
#define DMA_PRESENT
|
||||
#define DMA_COUNT 1
|
||||
#define VCMP_PRESENT
|
||||
#define VCMP_COUNT 1
|
||||
#define LCD_PRESENT
|
||||
#define LCD_COUNT 1
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 1
|
||||
#define HFXTAL_PRESENT
|
||||
#define HFXTAL_COUNT 1
|
||||
#define LFXTAL_PRESENT
|
||||
#define LFXTAL_COUNT 1
|
||||
#define WDOG_PRESENT
|
||||
#define WDOG_COUNT 1
|
||||
#define DBG_PRESENT
|
||||
#define DBG_COUNT 1
|
||||
|
||||
#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
|
||||
#include "system_efm32g.h" /* System Header */
|
||||
|
||||
/** @} End of group EFM32G880F64_Part */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_Peripheral_TypeDefs EFM32G880F64 Peripheral TypeDefs
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32g_msc.h"
|
||||
#include "efm32g_emu.h"
|
||||
#include "efm32g_rmu.h"
|
||||
#include "efm32g_cmu.h"
|
||||
#include "efm32g_aes.h"
|
||||
#include "efm32g_ebi.h"
|
||||
#include "efm32g_gpio_p.h"
|
||||
#include "efm32g_gpio.h"
|
||||
#include "efm32g_prs_ch.h"
|
||||
#include "efm32g_prs.h"
|
||||
#include "efm32g_dma_ch.h"
|
||||
#include "efm32g_dma.h"
|
||||
#include "efm32g_timer_cc.h"
|
||||
#include "efm32g_timer.h"
|
||||
#include "efm32g_usart.h"
|
||||
#include "efm32g_leuart.h"
|
||||
#include "efm32g_letimer.h"
|
||||
#include "efm32g_pcnt.h"
|
||||
#include "efm32g_i2c.h"
|
||||
#include "efm32g_adc.h"
|
||||
#include "efm32g_dac.h"
|
||||
#include "efm32g_acmp.h"
|
||||
#include "efm32g_vcmp.h"
|
||||
#include "efm32g_lcd.h"
|
||||
#include "efm32g_rtc.h"
|
||||
#include "efm32g_wdog.h"
|
||||
#include "efm32g_dma_descriptor.h"
|
||||
#include "efm32g_devinfo.h"
|
||||
#include "efm32g_romtable.h"
|
||||
#include "efm32g_calibrate.h"
|
||||
|
||||
/** @} End of group EFM32G880F64_Peripheral_TypeDefs */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_Peripheral_Base EFM32G880F64 Peripheral Memory Map
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC_BASE (0x400C0000UL) /**< MSC base address */
|
||||
#define EMU_BASE (0x400C6000UL) /**< EMU base address */
|
||||
#define RMU_BASE (0x400CA000UL) /**< RMU base address */
|
||||
#define CMU_BASE (0x400C8000UL) /**< CMU base address */
|
||||
#define AES_BASE (0x400E0000UL) /**< AES base address */
|
||||
#define EBI_BASE (0x40008000UL) /**< EBI base address */
|
||||
#define GPIO_BASE (0x40006000UL) /**< GPIO base address */
|
||||
#define PRS_BASE (0x400CC000UL) /**< PRS base address */
|
||||
#define DMA_BASE (0x400C2000UL) /**< DMA base address */
|
||||
#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
|
||||
#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
|
||||
#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
|
||||
#define USART0_BASE (0x4000C000UL) /**< USART0 base address */
|
||||
#define USART1_BASE (0x4000C400UL) /**< USART1 base address */
|
||||
#define USART2_BASE (0x4000C800UL) /**< USART2 base address */
|
||||
#define UART0_BASE (0x4000E000UL) /**< UART0 base address */
|
||||
#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
|
||||
#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
|
||||
#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
|
||||
#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
|
||||
#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
|
||||
#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
|
||||
#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
|
||||
#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
|
||||
#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
|
||||
#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
|
||||
#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
|
||||
#define VCMP_BASE (0x40000000UL) /**< VCMP base address */
|
||||
#define LCD_BASE (0x4008A000UL) /**< LCD base address */
|
||||
#define RTC_BASE (0x40080000UL) /**< RTC base address */
|
||||
#define WDOG_BASE (0x40088000UL) /**< WDOG base address */
|
||||
#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
|
||||
#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
|
||||
#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
|
||||
|
||||
/** @} End of group EFM32G880F64_Peripheral_Base */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_Peripheral_Declaration EFM32G880F64 Peripheral Declarations
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G880F64_Peripheral_Declaration */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_BitFields EFM32G880F64 Bit Fields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32g_prs_signals.h"
|
||||
#include "efm32g_dmareq.h"
|
||||
#include "efm32g_dmactrl.h"
|
||||
#include "efm32g_uart.h"
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_UNLOCK EFM32G880F64 Unlock Codes
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
||||
/** @} End of group EFM32G880F64_UNLOCK */
|
||||
|
||||
/** @} End of group EFM32G880F64_BitFields */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G880F64_Alternate_Function EFM32G880F64 Alternate Function
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32g_af_ports.h"
|
||||
#include "efm32g_af_pins.h"
|
||||
|
||||
/** @} End of group EFM32G880F64_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @brief Set the value of a bit field within a register.
|
||||
*
|
||||
* @param REG
|
||||
* The register to update
|
||||
* @param MASK
|
||||
* The mask for the bit field to update
|
||||
* @param VALUE
|
||||
* The value to write to the bit field
|
||||
* @param OFFSET
|
||||
* The number of bits that the field is offset within the register.
|
||||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G880F64 */
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __EFM32G880F64_H */
|
||||
|
|
@ -0,0 +1,416 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G890F128
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __EFM32G890F128_H
|
||||
#define __EFM32G890F128_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128 EFM32G890F128
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers *******************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
|
||||
|
||||
/****** EFM32G Peripheral Interrupt Numbers **********************************************/
|
||||
DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */
|
||||
ACMP0_IRQn = 5, /*!< 16+5 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 6, /*!< 16+6 EFM32 ADC0 Interrupt */
|
||||
DAC0_IRQn = 7, /*!< 16+7 EFM32 DAC0 Interrupt */
|
||||
I2C0_IRQn = 8, /*!< 16+8 EFM32 I2C0 Interrupt */
|
||||
GPIO_ODD_IRQn = 9, /*!< 16+9 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 10, /*!< 16+10 EFM32 TIMER1 Interrupt */
|
||||
TIMER2_IRQn = 11, /*!< 16+11 EFM32 TIMER2 Interrupt */
|
||||
USART1_RX_IRQn = 12, /*!< 16+12 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 13, /*!< 16+13 EFM32 USART1_TX Interrupt */
|
||||
USART2_RX_IRQn = 14, /*!< 16+14 EFM32 USART2_RX Interrupt */
|
||||
USART2_TX_IRQn = 15, /*!< 16+15 EFM32 USART2_TX Interrupt */
|
||||
UART0_RX_IRQn = 16, /*!< 16+16 EFM32 UART0_RX Interrupt */
|
||||
UART0_TX_IRQn = 17, /*!< 16+17 EFM32 UART0_TX Interrupt */
|
||||
LEUART0_IRQn = 18, /*!< 16+18 EFM32 LEUART0 Interrupt */
|
||||
LEUART1_IRQn = 19, /*!< 16+19 EFM32 LEUART1 Interrupt */
|
||||
LETIMER0_IRQn = 20, /*!< 16+20 EFM32 LETIMER0 Interrupt */
|
||||
PCNT0_IRQn = 21, /*!< 16+21 EFM32 PCNT0 Interrupt */
|
||||
PCNT1_IRQn = 22, /*!< 16+22 EFM32 PCNT1 Interrupt */
|
||||
PCNT2_IRQn = 23, /*!< 16+23 EFM32 PCNT2 Interrupt */
|
||||
RTC_IRQn = 24, /*!< 16+24 EFM32 RTC Interrupt */
|
||||
CMU_IRQn = 25, /*!< 16+25 EFM32 CMU Interrupt */
|
||||
VCMP_IRQn = 26, /*!< 16+26 EFM32 VCMP Interrupt */
|
||||
LCD_IRQn = 27, /*!< 16+27 EFM32 LCD Interrupt */
|
||||
MSC_IRQn = 28, /*!< 16+28 EFM32 MSC Interrupt */
|
||||
AES_IRQn = 29, /*!< 16+29 EFM32 AES Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_Core EFM32G890F128 Core
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
|
||||
|
||||
/** @} End of group EFM32G890F128_Core */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_Part EFM32G890F128 Part
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/** Part family */
|
||||
#define _EFM32_GECKO_FAMILY 1 /**< Gecko EFM32G MCU Family */
|
||||
#define _EFM_DEVICE /**< Energy Micro EFM-type microcontroller */
|
||||
|
||||
/* If part number is not defined as compiler option, define it */
|
||||
#if !defined(EFM32G890F128)
|
||||
#define EFM32G890F128 1 /**< Gecko Part */
|
||||
#endif
|
||||
|
||||
/** Configure part number */
|
||||
#define PART_NUMBER "EFM32G890F128" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G890F128 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
#define FLASH_SIZE (0x00020000UL) /**< Available Flash Memory */
|
||||
#define FLASH_PAGE_SIZE 512 /**< Flash Memory page size */
|
||||
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
|
||||
#define SRAM_SIZE (0x00004000UL) /**< Available SRAM Memory */
|
||||
#define __CM3_REV 0x200 /**< Cortex-M3 Core revision r2p0 */
|
||||
#define PRS_CHAN_COUNT 8 /**< Number of PRS channels */
|
||||
#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
|
||||
|
||||
/** AF channels connect the different on-chip peripherals with the af-mux */
|
||||
#define AFCHAN_MAX 79
|
||||
#define AFCHANLOC_MAX 4
|
||||
/** Analog AF channels */
|
||||
#define AFACHAN_MAX 37
|
||||
|
||||
/* Part number capabilities */
|
||||
|
||||
#define TIMER_PRESENT /**< TIMER is available in this part */
|
||||
#define TIMER_COUNT 3 /**< 3 TIMERs available */
|
||||
#define USART_PRESENT /**< USART is available in this part */
|
||||
#define USART_COUNT 3 /**< 3 USARTs available */
|
||||
#define UART_PRESENT /**< UART is available in this part */
|
||||
#define UART_COUNT 1 /**< 1 UARTs available */
|
||||
#define LEUART_PRESENT /**< LEUART is available in this part */
|
||||
#define LEUART_COUNT 2 /**< 2 LEUARTs available */
|
||||
#define LETIMER_PRESENT /**< LETIMER is available in this part */
|
||||
#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
|
||||
#define PCNT_PRESENT /**< PCNT is available in this part */
|
||||
#define PCNT_COUNT 3 /**< 3 PCNTs available */
|
||||
#define I2C_PRESENT /**< I2C is available in this part */
|
||||
#define I2C_COUNT 1 /**< 1 I2Cs available */
|
||||
#define ADC_PRESENT /**< ADC is available in this part */
|
||||
#define ADC_COUNT 1 /**< 1 ADCs available */
|
||||
#define DAC_PRESENT /**< DAC is available in this part */
|
||||
#define DAC_COUNT 1 /**< 1 DACs available */
|
||||
#define ACMP_PRESENT /**< ACMP is available in this part */
|
||||
#define ACMP_COUNT 2 /**< 2 ACMPs available */
|
||||
#define LE_PRESENT
|
||||
#define LE_COUNT 1
|
||||
#define MSC_PRESENT
|
||||
#define MSC_COUNT 1
|
||||
#define EMU_PRESENT
|
||||
#define EMU_COUNT 1
|
||||
#define RMU_PRESENT
|
||||
#define RMU_COUNT 1
|
||||
#define CMU_PRESENT
|
||||
#define CMU_COUNT 1
|
||||
#define AES_PRESENT
|
||||
#define AES_COUNT 1
|
||||
#define EBI_PRESENT
|
||||
#define EBI_COUNT 1
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
#define PRS_PRESENT
|
||||
#define PRS_COUNT 1
|
||||
#define DMA_PRESENT
|
||||
#define DMA_COUNT 1
|
||||
#define VCMP_PRESENT
|
||||
#define VCMP_COUNT 1
|
||||
#define LCD_PRESENT
|
||||
#define LCD_COUNT 1
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 1
|
||||
#define HFXTAL_PRESENT
|
||||
#define HFXTAL_COUNT 1
|
||||
#define LFXTAL_PRESENT
|
||||
#define LFXTAL_COUNT 1
|
||||
#define WDOG_PRESENT
|
||||
#define WDOG_COUNT 1
|
||||
#define DBG_PRESENT
|
||||
#define DBG_COUNT 1
|
||||
|
||||
#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
|
||||
#include "system_efm32g.h" /* System Header */
|
||||
|
||||
/** @} End of group EFM32G890F128_Part */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_Peripheral_TypeDefs EFM32G890F128 Peripheral TypeDefs
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32g_msc.h"
|
||||
#include "efm32g_emu.h"
|
||||
#include "efm32g_rmu.h"
|
||||
#include "efm32g_cmu.h"
|
||||
#include "efm32g_aes.h"
|
||||
#include "efm32g_ebi.h"
|
||||
#include "efm32g_gpio_p.h"
|
||||
#include "efm32g_gpio.h"
|
||||
#include "efm32g_prs_ch.h"
|
||||
#include "efm32g_prs.h"
|
||||
#include "efm32g_dma_ch.h"
|
||||
#include "efm32g_dma.h"
|
||||
#include "efm32g_timer_cc.h"
|
||||
#include "efm32g_timer.h"
|
||||
#include "efm32g_usart.h"
|
||||
#include "efm32g_leuart.h"
|
||||
#include "efm32g_letimer.h"
|
||||
#include "efm32g_pcnt.h"
|
||||
#include "efm32g_i2c.h"
|
||||
#include "efm32g_adc.h"
|
||||
#include "efm32g_dac.h"
|
||||
#include "efm32g_acmp.h"
|
||||
#include "efm32g_vcmp.h"
|
||||
#include "efm32g_lcd.h"
|
||||
#include "efm32g_rtc.h"
|
||||
#include "efm32g_wdog.h"
|
||||
#include "efm32g_dma_descriptor.h"
|
||||
#include "efm32g_devinfo.h"
|
||||
#include "efm32g_romtable.h"
|
||||
#include "efm32g_calibrate.h"
|
||||
|
||||
/** @} End of group EFM32G890F128_Peripheral_TypeDefs */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_Peripheral_Base EFM32G890F128 Peripheral Memory Map
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC_BASE (0x400C0000UL) /**< MSC base address */
|
||||
#define EMU_BASE (0x400C6000UL) /**< EMU base address */
|
||||
#define RMU_BASE (0x400CA000UL) /**< RMU base address */
|
||||
#define CMU_BASE (0x400C8000UL) /**< CMU base address */
|
||||
#define AES_BASE (0x400E0000UL) /**< AES base address */
|
||||
#define EBI_BASE (0x40008000UL) /**< EBI base address */
|
||||
#define GPIO_BASE (0x40006000UL) /**< GPIO base address */
|
||||
#define PRS_BASE (0x400CC000UL) /**< PRS base address */
|
||||
#define DMA_BASE (0x400C2000UL) /**< DMA base address */
|
||||
#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
|
||||
#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
|
||||
#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
|
||||
#define USART0_BASE (0x4000C000UL) /**< USART0 base address */
|
||||
#define USART1_BASE (0x4000C400UL) /**< USART1 base address */
|
||||
#define USART2_BASE (0x4000C800UL) /**< USART2 base address */
|
||||
#define UART0_BASE (0x4000E000UL) /**< UART0 base address */
|
||||
#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
|
||||
#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
|
||||
#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
|
||||
#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
|
||||
#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
|
||||
#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
|
||||
#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
|
||||
#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
|
||||
#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
|
||||
#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
|
||||
#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
|
||||
#define VCMP_BASE (0x40000000UL) /**< VCMP base address */
|
||||
#define LCD_BASE (0x4008A000UL) /**< LCD base address */
|
||||
#define RTC_BASE (0x40080000UL) /**< RTC base address */
|
||||
#define WDOG_BASE (0x40088000UL) /**< WDOG base address */
|
||||
#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
|
||||
#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
|
||||
#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
|
||||
|
||||
/** @} End of group EFM32G890F128_Peripheral_Base */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_Peripheral_Declaration EFM32G890F128 Peripheral Declarations
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G890F128_Peripheral_Declaration */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_BitFields EFM32G890F128 Bit Fields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32g_prs_signals.h"
|
||||
#include "efm32g_dmareq.h"
|
||||
#include "efm32g_dmactrl.h"
|
||||
#include "efm32g_uart.h"
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_UNLOCK EFM32G890F128 Unlock Codes
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
||||
/** @} End of group EFM32G890F128_UNLOCK */
|
||||
|
||||
/** @} End of group EFM32G890F128_BitFields */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F128_Alternate_Function EFM32G890F128 Alternate Function
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32g_af_ports.h"
|
||||
#include "efm32g_af_pins.h"
|
||||
|
||||
/** @} End of group EFM32G890F128_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @brief Set the value of a bit field within a register.
|
||||
*
|
||||
* @param REG
|
||||
* The register to update
|
||||
* @param MASK
|
||||
* The mask for the bit field to update
|
||||
* @param VALUE
|
||||
* The value to write to the bit field
|
||||
* @param OFFSET
|
||||
* The number of bits that the field is offset within the register.
|
||||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G890F128 */
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __EFM32G890F128_H */
|
||||
|
|
@ -0,0 +1,416 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G890F32
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __EFM32G890F32_H
|
||||
#define __EFM32G890F32_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32 EFM32G890F32
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers *******************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
|
||||
|
||||
/****** EFM32G Peripheral Interrupt Numbers **********************************************/
|
||||
DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */
|
||||
ACMP0_IRQn = 5, /*!< 16+5 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 6, /*!< 16+6 EFM32 ADC0 Interrupt */
|
||||
DAC0_IRQn = 7, /*!< 16+7 EFM32 DAC0 Interrupt */
|
||||
I2C0_IRQn = 8, /*!< 16+8 EFM32 I2C0 Interrupt */
|
||||
GPIO_ODD_IRQn = 9, /*!< 16+9 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 10, /*!< 16+10 EFM32 TIMER1 Interrupt */
|
||||
TIMER2_IRQn = 11, /*!< 16+11 EFM32 TIMER2 Interrupt */
|
||||
USART1_RX_IRQn = 12, /*!< 16+12 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 13, /*!< 16+13 EFM32 USART1_TX Interrupt */
|
||||
USART2_RX_IRQn = 14, /*!< 16+14 EFM32 USART2_RX Interrupt */
|
||||
USART2_TX_IRQn = 15, /*!< 16+15 EFM32 USART2_TX Interrupt */
|
||||
UART0_RX_IRQn = 16, /*!< 16+16 EFM32 UART0_RX Interrupt */
|
||||
UART0_TX_IRQn = 17, /*!< 16+17 EFM32 UART0_TX Interrupt */
|
||||
LEUART0_IRQn = 18, /*!< 16+18 EFM32 LEUART0 Interrupt */
|
||||
LEUART1_IRQn = 19, /*!< 16+19 EFM32 LEUART1 Interrupt */
|
||||
LETIMER0_IRQn = 20, /*!< 16+20 EFM32 LETIMER0 Interrupt */
|
||||
PCNT0_IRQn = 21, /*!< 16+21 EFM32 PCNT0 Interrupt */
|
||||
PCNT1_IRQn = 22, /*!< 16+22 EFM32 PCNT1 Interrupt */
|
||||
PCNT2_IRQn = 23, /*!< 16+23 EFM32 PCNT2 Interrupt */
|
||||
RTC_IRQn = 24, /*!< 16+24 EFM32 RTC Interrupt */
|
||||
CMU_IRQn = 25, /*!< 16+25 EFM32 CMU Interrupt */
|
||||
VCMP_IRQn = 26, /*!< 16+26 EFM32 VCMP Interrupt */
|
||||
LCD_IRQn = 27, /*!< 16+27 EFM32 LCD Interrupt */
|
||||
MSC_IRQn = 28, /*!< 16+28 EFM32 MSC Interrupt */
|
||||
AES_IRQn = 29, /*!< 16+29 EFM32 AES Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_Core EFM32G890F32 Core
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
|
||||
|
||||
/** @} End of group EFM32G890F32_Core */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_Part EFM32G890F32 Part
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/** Part family */
|
||||
#define _EFM32_GECKO_FAMILY 1 /**< Gecko EFM32G MCU Family */
|
||||
#define _EFM_DEVICE /**< Energy Micro EFM-type microcontroller */
|
||||
|
||||
/* If part number is not defined as compiler option, define it */
|
||||
#if !defined(EFM32G890F32)
|
||||
#define EFM32G890F32 1 /**< Gecko Part */
|
||||
#endif
|
||||
|
||||
/** Configure part number */
|
||||
#define PART_NUMBER "EFM32G890F32" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G890F32 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
#define FLASH_SIZE (0x00008000UL) /**< Available Flash Memory */
|
||||
#define FLASH_PAGE_SIZE 512 /**< Flash Memory page size */
|
||||
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
|
||||
#define SRAM_SIZE (0x00002000UL) /**< Available SRAM Memory */
|
||||
#define __CM3_REV 0x200 /**< Cortex-M3 Core revision r2p0 */
|
||||
#define PRS_CHAN_COUNT 8 /**< Number of PRS channels */
|
||||
#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
|
||||
|
||||
/** AF channels connect the different on-chip peripherals with the af-mux */
|
||||
#define AFCHAN_MAX 79
|
||||
#define AFCHANLOC_MAX 4
|
||||
/** Analog AF channels */
|
||||
#define AFACHAN_MAX 37
|
||||
|
||||
/* Part number capabilities */
|
||||
|
||||
#define TIMER_PRESENT /**< TIMER is available in this part */
|
||||
#define TIMER_COUNT 3 /**< 3 TIMERs available */
|
||||
#define USART_PRESENT /**< USART is available in this part */
|
||||
#define USART_COUNT 3 /**< 3 USARTs available */
|
||||
#define UART_PRESENT /**< UART is available in this part */
|
||||
#define UART_COUNT 1 /**< 1 UARTs available */
|
||||
#define LEUART_PRESENT /**< LEUART is available in this part */
|
||||
#define LEUART_COUNT 2 /**< 2 LEUARTs available */
|
||||
#define LETIMER_PRESENT /**< LETIMER is available in this part */
|
||||
#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
|
||||
#define PCNT_PRESENT /**< PCNT is available in this part */
|
||||
#define PCNT_COUNT 3 /**< 3 PCNTs available */
|
||||
#define I2C_PRESENT /**< I2C is available in this part */
|
||||
#define I2C_COUNT 1 /**< 1 I2Cs available */
|
||||
#define ADC_PRESENT /**< ADC is available in this part */
|
||||
#define ADC_COUNT 1 /**< 1 ADCs available */
|
||||
#define DAC_PRESENT /**< DAC is available in this part */
|
||||
#define DAC_COUNT 1 /**< 1 DACs available */
|
||||
#define ACMP_PRESENT /**< ACMP is available in this part */
|
||||
#define ACMP_COUNT 2 /**< 2 ACMPs available */
|
||||
#define LE_PRESENT
|
||||
#define LE_COUNT 1
|
||||
#define MSC_PRESENT
|
||||
#define MSC_COUNT 1
|
||||
#define EMU_PRESENT
|
||||
#define EMU_COUNT 1
|
||||
#define RMU_PRESENT
|
||||
#define RMU_COUNT 1
|
||||
#define CMU_PRESENT
|
||||
#define CMU_COUNT 1
|
||||
#define AES_PRESENT
|
||||
#define AES_COUNT 1
|
||||
#define EBI_PRESENT
|
||||
#define EBI_COUNT 1
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
#define PRS_PRESENT
|
||||
#define PRS_COUNT 1
|
||||
#define DMA_PRESENT
|
||||
#define DMA_COUNT 1
|
||||
#define VCMP_PRESENT
|
||||
#define VCMP_COUNT 1
|
||||
#define LCD_PRESENT
|
||||
#define LCD_COUNT 1
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 1
|
||||
#define HFXTAL_PRESENT
|
||||
#define HFXTAL_COUNT 1
|
||||
#define LFXTAL_PRESENT
|
||||
#define LFXTAL_COUNT 1
|
||||
#define WDOG_PRESENT
|
||||
#define WDOG_COUNT 1
|
||||
#define DBG_PRESENT
|
||||
#define DBG_COUNT 1
|
||||
|
||||
#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
|
||||
#include "system_efm32g.h" /* System Header */
|
||||
|
||||
/** @} End of group EFM32G890F32_Part */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_Peripheral_TypeDefs EFM32G890F32 Peripheral TypeDefs
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32g_msc.h"
|
||||
#include "efm32g_emu.h"
|
||||
#include "efm32g_rmu.h"
|
||||
#include "efm32g_cmu.h"
|
||||
#include "efm32g_aes.h"
|
||||
#include "efm32g_ebi.h"
|
||||
#include "efm32g_gpio_p.h"
|
||||
#include "efm32g_gpio.h"
|
||||
#include "efm32g_prs_ch.h"
|
||||
#include "efm32g_prs.h"
|
||||
#include "efm32g_dma_ch.h"
|
||||
#include "efm32g_dma.h"
|
||||
#include "efm32g_timer_cc.h"
|
||||
#include "efm32g_timer.h"
|
||||
#include "efm32g_usart.h"
|
||||
#include "efm32g_leuart.h"
|
||||
#include "efm32g_letimer.h"
|
||||
#include "efm32g_pcnt.h"
|
||||
#include "efm32g_i2c.h"
|
||||
#include "efm32g_adc.h"
|
||||
#include "efm32g_dac.h"
|
||||
#include "efm32g_acmp.h"
|
||||
#include "efm32g_vcmp.h"
|
||||
#include "efm32g_lcd.h"
|
||||
#include "efm32g_rtc.h"
|
||||
#include "efm32g_wdog.h"
|
||||
#include "efm32g_dma_descriptor.h"
|
||||
#include "efm32g_devinfo.h"
|
||||
#include "efm32g_romtable.h"
|
||||
#include "efm32g_calibrate.h"
|
||||
|
||||
/** @} End of group EFM32G890F32_Peripheral_TypeDefs */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_Peripheral_Base EFM32G890F32 Peripheral Memory Map
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC_BASE (0x400C0000UL) /**< MSC base address */
|
||||
#define EMU_BASE (0x400C6000UL) /**< EMU base address */
|
||||
#define RMU_BASE (0x400CA000UL) /**< RMU base address */
|
||||
#define CMU_BASE (0x400C8000UL) /**< CMU base address */
|
||||
#define AES_BASE (0x400E0000UL) /**< AES base address */
|
||||
#define EBI_BASE (0x40008000UL) /**< EBI base address */
|
||||
#define GPIO_BASE (0x40006000UL) /**< GPIO base address */
|
||||
#define PRS_BASE (0x400CC000UL) /**< PRS base address */
|
||||
#define DMA_BASE (0x400C2000UL) /**< DMA base address */
|
||||
#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
|
||||
#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
|
||||
#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
|
||||
#define USART0_BASE (0x4000C000UL) /**< USART0 base address */
|
||||
#define USART1_BASE (0x4000C400UL) /**< USART1 base address */
|
||||
#define USART2_BASE (0x4000C800UL) /**< USART2 base address */
|
||||
#define UART0_BASE (0x4000E000UL) /**< UART0 base address */
|
||||
#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
|
||||
#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
|
||||
#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
|
||||
#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
|
||||
#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
|
||||
#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
|
||||
#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
|
||||
#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
|
||||
#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
|
||||
#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
|
||||
#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
|
||||
#define VCMP_BASE (0x40000000UL) /**< VCMP base address */
|
||||
#define LCD_BASE (0x4008A000UL) /**< LCD base address */
|
||||
#define RTC_BASE (0x40080000UL) /**< RTC base address */
|
||||
#define WDOG_BASE (0x40088000UL) /**< WDOG base address */
|
||||
#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
|
||||
#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
|
||||
#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
|
||||
|
||||
/** @} End of group EFM32G890F32_Peripheral_Base */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_Peripheral_Declaration EFM32G890F32 Peripheral Declarations
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G890F32_Peripheral_Declaration */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_BitFields EFM32G890F32 Bit Fields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32g_prs_signals.h"
|
||||
#include "efm32g_dmareq.h"
|
||||
#include "efm32g_dmactrl.h"
|
||||
#include "efm32g_uart.h"
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_UNLOCK EFM32G890F32 Unlock Codes
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
||||
/** @} End of group EFM32G890F32_UNLOCK */
|
||||
|
||||
/** @} End of group EFM32G890F32_BitFields */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F32_Alternate_Function EFM32G890F32 Alternate Function
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32g_af_ports.h"
|
||||
#include "efm32g_af_pins.h"
|
||||
|
||||
/** @} End of group EFM32G890F32_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @brief Set the value of a bit field within a register.
|
||||
*
|
||||
* @param REG
|
||||
* The register to update
|
||||
* @param MASK
|
||||
* The mask for the bit field to update
|
||||
* @param VALUE
|
||||
* The value to write to the bit field
|
||||
* @param OFFSET
|
||||
* The number of bits that the field is offset within the register.
|
||||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G890F32 */
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __EFM32G890F32_H */
|
||||
|
|
@ -0,0 +1,416 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File
|
||||
* for EFM EFM32G890F64
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __EFM32G890F64_H
|
||||
#define __EFM32G890F64_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64 EFM32G890F64
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/** Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers *******************************************/
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
|
||||
|
||||
/****** EFM32G Peripheral Interrupt Numbers **********************************************/
|
||||
DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */
|
||||
GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */
|
||||
TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */
|
||||
USART0_RX_IRQn = 3, /*!< 16+3 EFM32 USART0_RX Interrupt */
|
||||
USART0_TX_IRQn = 4, /*!< 16+4 EFM32 USART0_TX Interrupt */
|
||||
ACMP0_IRQn = 5, /*!< 16+5 EFM32 ACMP0 Interrupt */
|
||||
ADC0_IRQn = 6, /*!< 16+6 EFM32 ADC0 Interrupt */
|
||||
DAC0_IRQn = 7, /*!< 16+7 EFM32 DAC0 Interrupt */
|
||||
I2C0_IRQn = 8, /*!< 16+8 EFM32 I2C0 Interrupt */
|
||||
GPIO_ODD_IRQn = 9, /*!< 16+9 EFM32 GPIO_ODD Interrupt */
|
||||
TIMER1_IRQn = 10, /*!< 16+10 EFM32 TIMER1 Interrupt */
|
||||
TIMER2_IRQn = 11, /*!< 16+11 EFM32 TIMER2 Interrupt */
|
||||
USART1_RX_IRQn = 12, /*!< 16+12 EFM32 USART1_RX Interrupt */
|
||||
USART1_TX_IRQn = 13, /*!< 16+13 EFM32 USART1_TX Interrupt */
|
||||
USART2_RX_IRQn = 14, /*!< 16+14 EFM32 USART2_RX Interrupt */
|
||||
USART2_TX_IRQn = 15, /*!< 16+15 EFM32 USART2_TX Interrupt */
|
||||
UART0_RX_IRQn = 16, /*!< 16+16 EFM32 UART0_RX Interrupt */
|
||||
UART0_TX_IRQn = 17, /*!< 16+17 EFM32 UART0_TX Interrupt */
|
||||
LEUART0_IRQn = 18, /*!< 16+18 EFM32 LEUART0 Interrupt */
|
||||
LEUART1_IRQn = 19, /*!< 16+19 EFM32 LEUART1 Interrupt */
|
||||
LETIMER0_IRQn = 20, /*!< 16+20 EFM32 LETIMER0 Interrupt */
|
||||
PCNT0_IRQn = 21, /*!< 16+21 EFM32 PCNT0 Interrupt */
|
||||
PCNT1_IRQn = 22, /*!< 16+22 EFM32 PCNT1 Interrupt */
|
||||
PCNT2_IRQn = 23, /*!< 16+23 EFM32 PCNT2 Interrupt */
|
||||
RTC_IRQn = 24, /*!< 16+24 EFM32 RTC Interrupt */
|
||||
CMU_IRQn = 25, /*!< 16+25 EFM32 CMU Interrupt */
|
||||
VCMP_IRQn = 26, /*!< 16+26 EFM32 VCMP Interrupt */
|
||||
LCD_IRQn = 27, /*!< 16+27 EFM32 LCD Interrupt */
|
||||
MSC_IRQn = 28, /*!< 16+28 EFM32 MSC Interrupt */
|
||||
AES_IRQn = 29, /*!< 16+29 EFM32 AES Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_Core EFM32G890F64 Core
|
||||
* @{
|
||||
* @brief Processor and Core Peripheral Section
|
||||
*****************************************************************************/
|
||||
#define __MPU_PRESENT 1 /**< Presence of MPU */
|
||||
#define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
|
||||
#define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
|
||||
|
||||
/** @} End of group EFM32G890F64_Core */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_Part EFM32G890F64 Part
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/** Part family */
|
||||
#define _EFM32_GECKO_FAMILY 1 /**< Gecko EFM32G MCU Family */
|
||||
#define _EFM_DEVICE /**< Energy Micro EFM-type microcontroller */
|
||||
|
||||
/* If part number is not defined as compiler option, define it */
|
||||
#if !defined(EFM32G890F64)
|
||||
#define EFM32G890F64 1 /**< Gecko Part */
|
||||
#endif
|
||||
|
||||
/** Configure part number */
|
||||
#define PART_NUMBER "EFM32G890F64" /**< Part Number */
|
||||
|
||||
/** Memory Base addresses and limits */
|
||||
#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
|
||||
#define EBI_MEM_SIZE ((uint32_t) 0x10000000UL) /**< EBI available address space */
|
||||
#define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) /**< EBI end address */
|
||||
#define EBI_MEM_BITS ((uint32_t) 0x28UL) /**< EBI used bits */
|
||||
#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
|
||||
#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
|
||||
#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
|
||||
#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
|
||||
#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
|
||||
#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
|
||||
#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
|
||||
#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
|
||||
#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
|
||||
#define RAM_MEM_SIZE ((uint32_t) 0x8000UL) /**< RAM available address space */
|
||||
#define RAM_MEM_END ((uint32_t) 0x20007FFFUL) /**< RAM end address */
|
||||
#define RAM_MEM_BITS ((uint32_t) 0x15UL) /**< RAM used bits */
|
||||
#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
|
||||
#define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) /**< RAM_CODE available address space */
|
||||
#define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) /**< RAM_CODE end address */
|
||||
#define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) /**< RAM_CODE used bits */
|
||||
#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
|
||||
#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
|
||||
#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
|
||||
#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
|
||||
|
||||
/** Bit banding area */
|
||||
#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
|
||||
#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
|
||||
|
||||
/** Flash and SRAM limits for EFM32G890F64 */
|
||||
#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
|
||||
#define FLASH_SIZE (0x00010000UL) /**< Available Flash Memory */
|
||||
#define FLASH_PAGE_SIZE 512 /**< Flash Memory page size */
|
||||
#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
|
||||
#define SRAM_SIZE (0x00004000UL) /**< Available SRAM Memory */
|
||||
#define __CM3_REV 0x200 /**< Cortex-M3 Core revision r2p0 */
|
||||
#define PRS_CHAN_COUNT 8 /**< Number of PRS channels */
|
||||
#define DMA_CHAN_COUNT 8 /**< Number of DMA channels */
|
||||
|
||||
/** AF channels connect the different on-chip peripherals with the af-mux */
|
||||
#define AFCHAN_MAX 79
|
||||
#define AFCHANLOC_MAX 4
|
||||
/** Analog AF channels */
|
||||
#define AFACHAN_MAX 37
|
||||
|
||||
/* Part number capabilities */
|
||||
|
||||
#define TIMER_PRESENT /**< TIMER is available in this part */
|
||||
#define TIMER_COUNT 3 /**< 3 TIMERs available */
|
||||
#define USART_PRESENT /**< USART is available in this part */
|
||||
#define USART_COUNT 3 /**< 3 USARTs available */
|
||||
#define UART_PRESENT /**< UART is available in this part */
|
||||
#define UART_COUNT 1 /**< 1 UARTs available */
|
||||
#define LEUART_PRESENT /**< LEUART is available in this part */
|
||||
#define LEUART_COUNT 2 /**< 2 LEUARTs available */
|
||||
#define LETIMER_PRESENT /**< LETIMER is available in this part */
|
||||
#define LETIMER_COUNT 1 /**< 1 LETIMERs available */
|
||||
#define PCNT_PRESENT /**< PCNT is available in this part */
|
||||
#define PCNT_COUNT 3 /**< 3 PCNTs available */
|
||||
#define I2C_PRESENT /**< I2C is available in this part */
|
||||
#define I2C_COUNT 1 /**< 1 I2Cs available */
|
||||
#define ADC_PRESENT /**< ADC is available in this part */
|
||||
#define ADC_COUNT 1 /**< 1 ADCs available */
|
||||
#define DAC_PRESENT /**< DAC is available in this part */
|
||||
#define DAC_COUNT 1 /**< 1 DACs available */
|
||||
#define ACMP_PRESENT /**< ACMP is available in this part */
|
||||
#define ACMP_COUNT 2 /**< 2 ACMPs available */
|
||||
#define LE_PRESENT
|
||||
#define LE_COUNT 1
|
||||
#define MSC_PRESENT
|
||||
#define MSC_COUNT 1
|
||||
#define EMU_PRESENT
|
||||
#define EMU_COUNT 1
|
||||
#define RMU_PRESENT
|
||||
#define RMU_COUNT 1
|
||||
#define CMU_PRESENT
|
||||
#define CMU_COUNT 1
|
||||
#define AES_PRESENT
|
||||
#define AES_COUNT 1
|
||||
#define EBI_PRESENT
|
||||
#define EBI_COUNT 1
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
#define PRS_PRESENT
|
||||
#define PRS_COUNT 1
|
||||
#define DMA_PRESENT
|
||||
#define DMA_COUNT 1
|
||||
#define VCMP_PRESENT
|
||||
#define VCMP_COUNT 1
|
||||
#define LCD_PRESENT
|
||||
#define LCD_COUNT 1
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 1
|
||||
#define HFXTAL_PRESENT
|
||||
#define HFXTAL_COUNT 1
|
||||
#define LFXTAL_PRESENT
|
||||
#define LFXTAL_COUNT 1
|
||||
#define WDOG_PRESENT
|
||||
#define WDOG_COUNT 1
|
||||
#define DBG_PRESENT
|
||||
#define DBG_COUNT 1
|
||||
|
||||
#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
|
||||
#include "system_efm32g.h" /* System Header */
|
||||
|
||||
/** @} End of group EFM32G890F64_Part */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_Peripheral_TypeDefs EFM32G890F64 Peripheral TypeDefs
|
||||
* @{
|
||||
* @brief Device Specific Peripheral Register Structures
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32g_msc.h"
|
||||
#include "efm32g_emu.h"
|
||||
#include "efm32g_rmu.h"
|
||||
#include "efm32g_cmu.h"
|
||||
#include "efm32g_aes.h"
|
||||
#include "efm32g_ebi.h"
|
||||
#include "efm32g_gpio_p.h"
|
||||
#include "efm32g_gpio.h"
|
||||
#include "efm32g_prs_ch.h"
|
||||
#include "efm32g_prs.h"
|
||||
#include "efm32g_dma_ch.h"
|
||||
#include "efm32g_dma.h"
|
||||
#include "efm32g_timer_cc.h"
|
||||
#include "efm32g_timer.h"
|
||||
#include "efm32g_usart.h"
|
||||
#include "efm32g_leuart.h"
|
||||
#include "efm32g_letimer.h"
|
||||
#include "efm32g_pcnt.h"
|
||||
#include "efm32g_i2c.h"
|
||||
#include "efm32g_adc.h"
|
||||
#include "efm32g_dac.h"
|
||||
#include "efm32g_acmp.h"
|
||||
#include "efm32g_vcmp.h"
|
||||
#include "efm32g_lcd.h"
|
||||
#include "efm32g_rtc.h"
|
||||
#include "efm32g_wdog.h"
|
||||
#include "efm32g_dma_descriptor.h"
|
||||
#include "efm32g_devinfo.h"
|
||||
#include "efm32g_romtable.h"
|
||||
#include "efm32g_calibrate.h"
|
||||
|
||||
/** @} End of group EFM32G890F64_Peripheral_TypeDefs */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_Peripheral_Base EFM32G890F64 Peripheral Memory Map
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC_BASE (0x400C0000UL) /**< MSC base address */
|
||||
#define EMU_BASE (0x400C6000UL) /**< EMU base address */
|
||||
#define RMU_BASE (0x400CA000UL) /**< RMU base address */
|
||||
#define CMU_BASE (0x400C8000UL) /**< CMU base address */
|
||||
#define AES_BASE (0x400E0000UL) /**< AES base address */
|
||||
#define EBI_BASE (0x40008000UL) /**< EBI base address */
|
||||
#define GPIO_BASE (0x40006000UL) /**< GPIO base address */
|
||||
#define PRS_BASE (0x400CC000UL) /**< PRS base address */
|
||||
#define DMA_BASE (0x400C2000UL) /**< DMA base address */
|
||||
#define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
|
||||
#define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
|
||||
#define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
|
||||
#define USART0_BASE (0x4000C000UL) /**< USART0 base address */
|
||||
#define USART1_BASE (0x4000C400UL) /**< USART1 base address */
|
||||
#define USART2_BASE (0x4000C800UL) /**< USART2 base address */
|
||||
#define UART0_BASE (0x4000E000UL) /**< UART0 base address */
|
||||
#define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
|
||||
#define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
|
||||
#define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
|
||||
#define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
|
||||
#define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
|
||||
#define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
|
||||
#define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
|
||||
#define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
|
||||
#define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
|
||||
#define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
|
||||
#define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
|
||||
#define VCMP_BASE (0x40000000UL) /**< VCMP base address */
|
||||
#define LCD_BASE (0x4008A000UL) /**< LCD base address */
|
||||
#define RTC_BASE (0x40080000UL) /**< RTC base address */
|
||||
#define WDOG_BASE (0x40088000UL) /**< WDOG base address */
|
||||
#define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
|
||||
#define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
|
||||
#define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
|
||||
|
||||
/** @} End of group EFM32G890F64_Peripheral_Base */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_Peripheral_Declaration EFM32G890F64 Peripheral Declarations
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
|
||||
#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
|
||||
#define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
|
||||
#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
|
||||
#define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
|
||||
#define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
|
||||
#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
|
||||
#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
|
||||
#define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
|
||||
#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
|
||||
#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
|
||||
#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
|
||||
#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
|
||||
#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
|
||||
#define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
|
||||
#define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
|
||||
#define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
|
||||
#define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
|
||||
#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
|
||||
#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
|
||||
#define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
|
||||
#define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
|
||||
#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
|
||||
#define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
|
||||
#define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
|
||||
#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
|
||||
#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
|
||||
#define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
|
||||
#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
|
||||
#define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
|
||||
#define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
|
||||
#define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
|
||||
#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
|
||||
#define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
|
||||
|
||||
/** @} End of group EFM32G890F64_Peripheral_Declaration */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_BitFields EFM32G890F64 Bit Fields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32g_prs_signals.h"
|
||||
#include "efm32g_dmareq.h"
|
||||
#include "efm32g_dmactrl.h"
|
||||
#include "efm32g_uart.h"
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_UNLOCK EFM32G890F64 Unlock Codes
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
|
||||
#define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
|
||||
#define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
|
||||
#define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
|
||||
#define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
|
||||
|
||||
/** @} End of group EFM32G890F64_UNLOCK */
|
||||
|
||||
/** @} End of group EFM32G890F64_BitFields */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G890F64_Alternate_Function EFM32G890F64 Alternate Function
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
#include "efm32g_af_ports.h"
|
||||
#include "efm32g_af_pins.h"
|
||||
|
||||
/** @} End of group EFM32G890F64_Alternate_Function */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @brief Set the value of a bit field within a register.
|
||||
*
|
||||
* @param REG
|
||||
* The register to update
|
||||
* @param MASK
|
||||
* The mask for the bit field to update
|
||||
* @param VALUE
|
||||
* The value to write to the bit field
|
||||
* @param OFFSET
|
||||
* The number of bits that the field is offset within the register.
|
||||
* 0 (zero) means LSB.
|
||||
*****************************************************************************/
|
||||
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
|
||||
REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
|
||||
|
||||
/** @} End of group EFM32G890F64 */
|
||||
|
||||
/** @} End of group Parts */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __EFM32G890F64_H */
|
||||
|
|
@ -0,0 +1,330 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief efm32g_acmp Register and Bit Field definitions
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_ACMP
|
||||
* @{
|
||||
* @brief EFM32G_ACMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__IO uint32_t INPUTSEL; /**< Input Selection Register */
|
||||
__I uint32_t STATUS; /**< Status Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IO uint32_t ROUTE; /**< I/O Routing Register */
|
||||
} ACMP_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_ACMP_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/* Bit fields for ACMP CTRL */
|
||||
#define _ACMP_CTRL_RESETVALUE 0x47000000UL /**< Default value for ACMP_CTRL */
|
||||
#define _ACMP_CTRL_MASK 0xCF03077FUL /**< Mask for ACMP_CTRL */
|
||||
#define ACMP_CTRL_EN (0x1UL << 0) /**< Analog Comparator Enable */
|
||||
#define _ACMP_CTRL_EN_SHIFT 0 /**< Shift value for ACMP_EN */
|
||||
#define _ACMP_CTRL_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */
|
||||
#define _ACMP_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
|
||||
#define ACMP_CTRL_EN_DEFAULT (_ACMP_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CTRL */
|
||||
#define ACMP_CTRL_MUXEN (0x1UL << 1) /**< Input Mux Enable */
|
||||
#define _ACMP_CTRL_MUXEN_SHIFT 1 /**< Shift value for ACMP_MUXEN */
|
||||
#define _ACMP_CTRL_MUXEN_MASK 0x2UL /**< Bit mask for ACMP_MUXEN */
|
||||
#define _ACMP_CTRL_MUXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
|
||||
#define ACMP_CTRL_MUXEN_DEFAULT (_ACMP_CTRL_MUXEN_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_CTRL */
|
||||
#define ACMP_CTRL_INACTVAL (0x1UL << 2) /**< Inactive Value */
|
||||
#define _ACMP_CTRL_INACTVAL_SHIFT 2 /**< Shift value for ACMP_INACTVAL */
|
||||
#define _ACMP_CTRL_INACTVAL_MASK 0x4UL /**< Bit mask for ACMP_INACTVAL */
|
||||
#define _ACMP_CTRL_INACTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
|
||||
#define _ACMP_CTRL_INACTVAL_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */
|
||||
#define _ACMP_CTRL_INACTVAL_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */
|
||||
#define ACMP_CTRL_INACTVAL_DEFAULT (_ACMP_CTRL_INACTVAL_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_CTRL */
|
||||
#define ACMP_CTRL_INACTVAL_LOW (_ACMP_CTRL_INACTVAL_LOW << 2) /**< Shifted mode LOW for ACMP_CTRL */
|
||||
#define ACMP_CTRL_INACTVAL_HIGH (_ACMP_CTRL_INACTVAL_HIGH << 2) /**< Shifted mode HIGH for ACMP_CTRL */
|
||||
#define ACMP_CTRL_GPIOINV (0x1UL << 3) /**< Comparator GPIO Output Invert */
|
||||
#define _ACMP_CTRL_GPIOINV_SHIFT 3 /**< Shift value for ACMP_GPIOINV */
|
||||
#define _ACMP_CTRL_GPIOINV_MASK 0x8UL /**< Bit mask for ACMP_GPIOINV */
|
||||
#define _ACMP_CTRL_GPIOINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
|
||||
#define _ACMP_CTRL_GPIOINV_NOTINV 0x00000000UL /**< Mode NOTINV for ACMP_CTRL */
|
||||
#define _ACMP_CTRL_GPIOINV_INV 0x00000001UL /**< Mode INV for ACMP_CTRL */
|
||||
#define ACMP_CTRL_GPIOINV_DEFAULT (_ACMP_CTRL_GPIOINV_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_CTRL */
|
||||
#define ACMP_CTRL_GPIOINV_NOTINV (_ACMP_CTRL_GPIOINV_NOTINV << 3) /**< Shifted mode NOTINV for ACMP_CTRL */
|
||||
#define ACMP_CTRL_GPIOINV_INV (_ACMP_CTRL_GPIOINV_INV << 3) /**< Shifted mode INV for ACMP_CTRL */
|
||||
#define _ACMP_CTRL_HYSTSEL_SHIFT 4 /**< Shift value for ACMP_HYSTSEL */
|
||||
#define _ACMP_CTRL_HYSTSEL_MASK 0x70UL /**< Bit mask for ACMP_HYSTSEL */
|
||||
#define _ACMP_CTRL_HYSTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
|
||||
#define _ACMP_CTRL_HYSTSEL_HYST0 0x00000000UL /**< Mode HYST0 for ACMP_CTRL */
|
||||
#define _ACMP_CTRL_HYSTSEL_HYST1 0x00000001UL /**< Mode HYST1 for ACMP_CTRL */
|
||||
#define _ACMP_CTRL_HYSTSEL_HYST2 0x00000002UL /**< Mode HYST2 for ACMP_CTRL */
|
||||
#define _ACMP_CTRL_HYSTSEL_HYST3 0x00000003UL /**< Mode HYST3 for ACMP_CTRL */
|
||||
#define _ACMP_CTRL_HYSTSEL_HYST4 0x00000004UL /**< Mode HYST4 for ACMP_CTRL */
|
||||
#define _ACMP_CTRL_HYSTSEL_HYST5 0x00000005UL /**< Mode HYST5 for ACMP_CTRL */
|
||||
#define _ACMP_CTRL_HYSTSEL_HYST6 0x00000006UL /**< Mode HYST6 for ACMP_CTRL */
|
||||
#define _ACMP_CTRL_HYSTSEL_HYST7 0x00000007UL /**< Mode HYST7 for ACMP_CTRL */
|
||||
#define ACMP_CTRL_HYSTSEL_DEFAULT (_ACMP_CTRL_HYSTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_CTRL */
|
||||
#define ACMP_CTRL_HYSTSEL_HYST0 (_ACMP_CTRL_HYSTSEL_HYST0 << 4) /**< Shifted mode HYST0 for ACMP_CTRL */
|
||||
#define ACMP_CTRL_HYSTSEL_HYST1 (_ACMP_CTRL_HYSTSEL_HYST1 << 4) /**< Shifted mode HYST1 for ACMP_CTRL */
|
||||
#define ACMP_CTRL_HYSTSEL_HYST2 (_ACMP_CTRL_HYSTSEL_HYST2 << 4) /**< Shifted mode HYST2 for ACMP_CTRL */
|
||||
#define ACMP_CTRL_HYSTSEL_HYST3 (_ACMP_CTRL_HYSTSEL_HYST3 << 4) /**< Shifted mode HYST3 for ACMP_CTRL */
|
||||
#define ACMP_CTRL_HYSTSEL_HYST4 (_ACMP_CTRL_HYSTSEL_HYST4 << 4) /**< Shifted mode HYST4 for ACMP_CTRL */
|
||||
#define ACMP_CTRL_HYSTSEL_HYST5 (_ACMP_CTRL_HYSTSEL_HYST5 << 4) /**< Shifted mode HYST5 for ACMP_CTRL */
|
||||
#define ACMP_CTRL_HYSTSEL_HYST6 (_ACMP_CTRL_HYSTSEL_HYST6 << 4) /**< Shifted mode HYST6 for ACMP_CTRL */
|
||||
#define ACMP_CTRL_HYSTSEL_HYST7 (_ACMP_CTRL_HYSTSEL_HYST7 << 4) /**< Shifted mode HYST7 for ACMP_CTRL */
|
||||
#define _ACMP_CTRL_WARMTIME_SHIFT 8 /**< Shift value for ACMP_WARMTIME */
|
||||
#define _ACMP_CTRL_WARMTIME_MASK 0x700UL /**< Bit mask for ACMP_WARMTIME */
|
||||
#define _ACMP_CTRL_WARMTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
|
||||
#define _ACMP_CTRL_WARMTIME_4CYCLES 0x00000000UL /**< Mode 4CYCLES for ACMP_CTRL */
|
||||
#define _ACMP_CTRL_WARMTIME_8CYCLES 0x00000001UL /**< Mode 8CYCLES for ACMP_CTRL */
|
||||
#define _ACMP_CTRL_WARMTIME_16CYCLES 0x00000002UL /**< Mode 16CYCLES for ACMP_CTRL */
|
||||
#define _ACMP_CTRL_WARMTIME_32CYCLES 0x00000003UL /**< Mode 32CYCLES for ACMP_CTRL */
|
||||
#define _ACMP_CTRL_WARMTIME_64CYCLES 0x00000004UL /**< Mode 64CYCLES for ACMP_CTRL */
|
||||
#define _ACMP_CTRL_WARMTIME_128CYCLES 0x00000005UL /**< Mode 128CYCLES for ACMP_CTRL */
|
||||
#define _ACMP_CTRL_WARMTIME_256CYCLES 0x00000006UL /**< Mode 256CYCLES for ACMP_CTRL */
|
||||
#define _ACMP_CTRL_WARMTIME_512CYCLES 0x00000007UL /**< Mode 512CYCLES for ACMP_CTRL */
|
||||
#define ACMP_CTRL_WARMTIME_DEFAULT (_ACMP_CTRL_WARMTIME_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_CTRL */
|
||||
#define ACMP_CTRL_WARMTIME_4CYCLES (_ACMP_CTRL_WARMTIME_4CYCLES << 8) /**< Shifted mode 4CYCLES for ACMP_CTRL */
|
||||
#define ACMP_CTRL_WARMTIME_8CYCLES (_ACMP_CTRL_WARMTIME_8CYCLES << 8) /**< Shifted mode 8CYCLES for ACMP_CTRL */
|
||||
#define ACMP_CTRL_WARMTIME_16CYCLES (_ACMP_CTRL_WARMTIME_16CYCLES << 8) /**< Shifted mode 16CYCLES for ACMP_CTRL */
|
||||
#define ACMP_CTRL_WARMTIME_32CYCLES (_ACMP_CTRL_WARMTIME_32CYCLES << 8) /**< Shifted mode 32CYCLES for ACMP_CTRL */
|
||||
#define ACMP_CTRL_WARMTIME_64CYCLES (_ACMP_CTRL_WARMTIME_64CYCLES << 8) /**< Shifted mode 64CYCLES for ACMP_CTRL */
|
||||
#define ACMP_CTRL_WARMTIME_128CYCLES (_ACMP_CTRL_WARMTIME_128CYCLES << 8) /**< Shifted mode 128CYCLES for ACMP_CTRL */
|
||||
#define ACMP_CTRL_WARMTIME_256CYCLES (_ACMP_CTRL_WARMTIME_256CYCLES << 8) /**< Shifted mode 256CYCLES for ACMP_CTRL */
|
||||
#define ACMP_CTRL_WARMTIME_512CYCLES (_ACMP_CTRL_WARMTIME_512CYCLES << 8) /**< Shifted mode 512CYCLES for ACMP_CTRL */
|
||||
#define ACMP_CTRL_IRISE (0x1UL << 16) /**< Rising Edge Interrupt Sense */
|
||||
#define _ACMP_CTRL_IRISE_SHIFT 16 /**< Shift value for ACMP_IRISE */
|
||||
#define _ACMP_CTRL_IRISE_MASK 0x10000UL /**< Bit mask for ACMP_IRISE */
|
||||
#define _ACMP_CTRL_IRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
|
||||
#define _ACMP_CTRL_IRISE_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CTRL */
|
||||
#define _ACMP_CTRL_IRISE_ENABLED 0x00000001UL /**< Mode ENABLED for ACMP_CTRL */
|
||||
#define ACMP_CTRL_IRISE_DEFAULT (_ACMP_CTRL_IRISE_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_CTRL */
|
||||
#define ACMP_CTRL_IRISE_DISABLED (_ACMP_CTRL_IRISE_DISABLED << 16) /**< Shifted mode DISABLED for ACMP_CTRL */
|
||||
#define ACMP_CTRL_IRISE_ENABLED (_ACMP_CTRL_IRISE_ENABLED << 16) /**< Shifted mode ENABLED for ACMP_CTRL */
|
||||
#define ACMP_CTRL_IFALL (0x1UL << 17) /**< Falling Edge Interrupt Sense */
|
||||
#define _ACMP_CTRL_IFALL_SHIFT 17 /**< Shift value for ACMP_IFALL */
|
||||
#define _ACMP_CTRL_IFALL_MASK 0x20000UL /**< Bit mask for ACMP_IFALL */
|
||||
#define _ACMP_CTRL_IFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
|
||||
#define _ACMP_CTRL_IFALL_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CTRL */
|
||||
#define _ACMP_CTRL_IFALL_ENABLED 0x00000001UL /**< Mode ENABLED for ACMP_CTRL */
|
||||
#define ACMP_CTRL_IFALL_DEFAULT (_ACMP_CTRL_IFALL_DEFAULT << 17) /**< Shifted mode DEFAULT for ACMP_CTRL */
|
||||
#define ACMP_CTRL_IFALL_DISABLED (_ACMP_CTRL_IFALL_DISABLED << 17) /**< Shifted mode DISABLED for ACMP_CTRL */
|
||||
#define ACMP_CTRL_IFALL_ENABLED (_ACMP_CTRL_IFALL_ENABLED << 17) /**< Shifted mode ENABLED for ACMP_CTRL */
|
||||
#define _ACMP_CTRL_BIASPROG_SHIFT 24 /**< Shift value for ACMP_BIASPROG */
|
||||
#define _ACMP_CTRL_BIASPROG_MASK 0xF000000UL /**< Bit mask for ACMP_BIASPROG */
|
||||
#define _ACMP_CTRL_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for ACMP_CTRL */
|
||||
#define ACMP_CTRL_BIASPROG_DEFAULT (_ACMP_CTRL_BIASPROG_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_CTRL */
|
||||
#define ACMP_CTRL_HALFBIAS (0x1UL << 30) /**< Half Bias Current */
|
||||
#define _ACMP_CTRL_HALFBIAS_SHIFT 30 /**< Shift value for ACMP_HALFBIAS */
|
||||
#define _ACMP_CTRL_HALFBIAS_MASK 0x40000000UL /**< Bit mask for ACMP_HALFBIAS */
|
||||
#define _ACMP_CTRL_HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ACMP_CTRL */
|
||||
#define ACMP_CTRL_HALFBIAS_DEFAULT (_ACMP_CTRL_HALFBIAS_DEFAULT << 30) /**< Shifted mode DEFAULT for ACMP_CTRL */
|
||||
#define ACMP_CTRL_FULLBIAS (0x1UL << 31) /**< Full Bias Current */
|
||||
#define _ACMP_CTRL_FULLBIAS_SHIFT 31 /**< Shift value for ACMP_FULLBIAS */
|
||||
#define _ACMP_CTRL_FULLBIAS_MASK 0x80000000UL /**< Bit mask for ACMP_FULLBIAS */
|
||||
#define _ACMP_CTRL_FULLBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */
|
||||
#define ACMP_CTRL_FULLBIAS_DEFAULT (_ACMP_CTRL_FULLBIAS_DEFAULT << 31) /**< Shifted mode DEFAULT for ACMP_CTRL */
|
||||
|
||||
/* Bit fields for ACMP INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_RESETVALUE 0x00010080UL /**< Default value for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_MASK 0x31013FF7UL /**< Mask for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_POSSEL_SHIFT 0 /**< Shift value for ACMP_POSSEL */
|
||||
#define _ACMP_INPUTSEL_POSSEL_MASK 0x7UL /**< Bit mask for ACMP_POSSEL */
|
||||
#define _ACMP_INPUTSEL_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_POSSEL_CH0 0x00000000UL /**< Mode CH0 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_POSSEL_CH1 0x00000001UL /**< Mode CH1 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_POSSEL_CH2 0x00000002UL /**< Mode CH2 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_POSSEL_CH3 0x00000003UL /**< Mode CH3 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_POSSEL_CH4 0x00000004UL /**< Mode CH4 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_POSSEL_CH5 0x00000005UL /**< Mode CH5 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_POSSEL_CH6 0x00000006UL /**< Mode CH6 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_POSSEL_CH7 0x00000007UL /**< Mode CH7 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_POSSEL_DEFAULT (_ACMP_INPUTSEL_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_POSSEL_CH0 (_ACMP_INPUTSEL_POSSEL_CH0 << 0) /**< Shifted mode CH0 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_POSSEL_CH1 (_ACMP_INPUTSEL_POSSEL_CH1 << 0) /**< Shifted mode CH1 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_POSSEL_CH2 (_ACMP_INPUTSEL_POSSEL_CH2 << 0) /**< Shifted mode CH2 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_POSSEL_CH3 (_ACMP_INPUTSEL_POSSEL_CH3 << 0) /**< Shifted mode CH3 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_POSSEL_CH4 (_ACMP_INPUTSEL_POSSEL_CH4 << 0) /**< Shifted mode CH4 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_POSSEL_CH5 (_ACMP_INPUTSEL_POSSEL_CH5 << 0) /**< Shifted mode CH5 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_POSSEL_CH6 (_ACMP_INPUTSEL_POSSEL_CH6 << 0) /**< Shifted mode CH6 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_POSSEL_CH7 (_ACMP_INPUTSEL_POSSEL_CH7 << 0) /**< Shifted mode CH7 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_NEGSEL_SHIFT 4 /**< Shift value for ACMP_NEGSEL */
|
||||
#define _ACMP_INPUTSEL_NEGSEL_MASK 0xF0UL /**< Bit mask for ACMP_NEGSEL */
|
||||
#define _ACMP_INPUTSEL_NEGSEL_CH0 0x00000000UL /**< Mode CH0 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_NEGSEL_CH1 0x00000001UL /**< Mode CH1 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_NEGSEL_CH2 0x00000002UL /**< Mode CH2 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_NEGSEL_CH3 0x00000003UL /**< Mode CH3 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_NEGSEL_CH4 0x00000004UL /**< Mode CH4 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_NEGSEL_CH5 0x00000005UL /**< Mode CH5 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_NEGSEL_CH6 0x00000006UL /**< Mode CH6 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_NEGSEL_CH7 0x00000007UL /**< Mode CH7 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_NEGSEL_DEFAULT 0x00000008UL /**< Mode DEFAULT for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_NEGSEL_1V25 0x00000008UL /**< Mode 1V25 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_NEGSEL_2V5 0x00000009UL /**< Mode 2V5 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_NEGSEL_VDD 0x0000000AUL /**< Mode VDD for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_NEGSEL_CAPSENSE 0x0000000BUL /**< Mode CAPSENSE for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_NEGSEL_CH0 (_ACMP_INPUTSEL_NEGSEL_CH0 << 4) /**< Shifted mode CH0 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_NEGSEL_CH1 (_ACMP_INPUTSEL_NEGSEL_CH1 << 4) /**< Shifted mode CH1 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_NEGSEL_CH2 (_ACMP_INPUTSEL_NEGSEL_CH2 << 4) /**< Shifted mode CH2 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_NEGSEL_CH3 (_ACMP_INPUTSEL_NEGSEL_CH3 << 4) /**< Shifted mode CH3 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_NEGSEL_CH4 (_ACMP_INPUTSEL_NEGSEL_CH4 << 4) /**< Shifted mode CH4 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_NEGSEL_CH5 (_ACMP_INPUTSEL_NEGSEL_CH5 << 4) /**< Shifted mode CH5 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_NEGSEL_CH6 (_ACMP_INPUTSEL_NEGSEL_CH6 << 4) /**< Shifted mode CH6 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_NEGSEL_CH7 (_ACMP_INPUTSEL_NEGSEL_CH7 << 4) /**< Shifted mode CH7 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_NEGSEL_DEFAULT (_ACMP_INPUTSEL_NEGSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_NEGSEL_1V25 (_ACMP_INPUTSEL_NEGSEL_1V25 << 4) /**< Shifted mode 1V25 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_NEGSEL_2V5 (_ACMP_INPUTSEL_NEGSEL_2V5 << 4) /**< Shifted mode 2V5 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_NEGSEL_VDD (_ACMP_INPUTSEL_NEGSEL_VDD << 4) /**< Shifted mode VDD for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_NEGSEL_CAPSENSE (_ACMP_INPUTSEL_NEGSEL_CAPSENSE << 4) /**< Shifted mode CAPSENSE for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_VDDLEVEL_SHIFT 8 /**< Shift value for ACMP_VDDLEVEL */
|
||||
#define _ACMP_INPUTSEL_VDDLEVEL_MASK 0x3F00UL /**< Bit mask for ACMP_VDDLEVEL */
|
||||
#define _ACMP_INPUTSEL_VDDLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_VDDLEVEL_DEFAULT (_ACMP_INPUTSEL_VDDLEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_LPREF (0x1UL << 16) /**< Low Power Reference Mode */
|
||||
#define _ACMP_INPUTSEL_LPREF_SHIFT 16 /**< Shift value for ACMP_LPREF */
|
||||
#define _ACMP_INPUTSEL_LPREF_MASK 0x10000UL /**< Bit mask for ACMP_LPREF */
|
||||
#define _ACMP_INPUTSEL_LPREF_DEFAULT 0x00000001UL /**< Mode DEFAULT for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_LPREF_DEFAULT (_ACMP_INPUTSEL_LPREF_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_CSRESEN (0x1UL << 24) /**< Capacitive Sense Mode Internal Resistor Enable */
|
||||
#define _ACMP_INPUTSEL_CSRESEN_SHIFT 24 /**< Shift value for ACMP_CSRESEN */
|
||||
#define _ACMP_INPUTSEL_CSRESEN_MASK 0x1000000UL /**< Bit mask for ACMP_CSRESEN */
|
||||
#define _ACMP_INPUTSEL_CSRESEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_CSRESEN_DEFAULT (_ACMP_INPUTSEL_CSRESEN_DEFAULT << 24) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_CSRESSEL_SHIFT 28 /**< Shift value for ACMP_CSRESSEL */
|
||||
#define _ACMP_INPUTSEL_CSRESSEL_MASK 0x30000000UL /**< Bit mask for ACMP_CSRESSEL */
|
||||
#define _ACMP_INPUTSEL_CSRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_CSRESSEL_RES0 0x00000000UL /**< Mode RES0 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_CSRESSEL_RES1 0x00000001UL /**< Mode RES1 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_CSRESSEL_RES2 0x00000002UL /**< Mode RES2 for ACMP_INPUTSEL */
|
||||
#define _ACMP_INPUTSEL_CSRESSEL_RES3 0x00000003UL /**< Mode RES3 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_CSRESSEL_DEFAULT (_ACMP_INPUTSEL_CSRESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_CSRESSEL_RES0 (_ACMP_INPUTSEL_CSRESSEL_RES0 << 28) /**< Shifted mode RES0 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_CSRESSEL_RES1 (_ACMP_INPUTSEL_CSRESSEL_RES1 << 28) /**< Shifted mode RES1 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_CSRESSEL_RES2 (_ACMP_INPUTSEL_CSRESSEL_RES2 << 28) /**< Shifted mode RES2 for ACMP_INPUTSEL */
|
||||
#define ACMP_INPUTSEL_CSRESSEL_RES3 (_ACMP_INPUTSEL_CSRESSEL_RES3 << 28) /**< Shifted mode RES3 for ACMP_INPUTSEL */
|
||||
|
||||
/* Bit fields for ACMP STATUS */
|
||||
#define _ACMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for ACMP_STATUS */
|
||||
#define _ACMP_STATUS_MASK 0x00000003UL /**< Mask for ACMP_STATUS */
|
||||
#define ACMP_STATUS_ACMPACT (0x1UL << 0) /**< Analog Comparator Active */
|
||||
#define _ACMP_STATUS_ACMPACT_SHIFT 0 /**< Shift value for ACMP_ACMPACT */
|
||||
#define _ACMP_STATUS_ACMPACT_MASK 0x1UL /**< Bit mask for ACMP_ACMPACT */
|
||||
#define _ACMP_STATUS_ACMPACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */
|
||||
#define ACMP_STATUS_ACMPACT_DEFAULT (_ACMP_STATUS_ACMPACT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_STATUS */
|
||||
#define ACMP_STATUS_ACMPOUT (0x1UL << 1) /**< Analog Comparator Output */
|
||||
#define _ACMP_STATUS_ACMPOUT_SHIFT 1 /**< Shift value for ACMP_ACMPOUT */
|
||||
#define _ACMP_STATUS_ACMPOUT_MASK 0x2UL /**< Bit mask for ACMP_ACMPOUT */
|
||||
#define _ACMP_STATUS_ACMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */
|
||||
#define ACMP_STATUS_ACMPOUT_DEFAULT (_ACMP_STATUS_ACMPOUT_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_STATUS */
|
||||
|
||||
/* Bit fields for ACMP IEN */
|
||||
#define _ACMP_IEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_IEN */
|
||||
#define _ACMP_IEN_MASK 0x00000003UL /**< Mask for ACMP_IEN */
|
||||
#define ACMP_IEN_EDGE (0x1UL << 0) /**< Edge Trigger Interrupt Enable */
|
||||
#define _ACMP_IEN_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */
|
||||
#define _ACMP_IEN_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */
|
||||
#define _ACMP_IEN_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */
|
||||
#define ACMP_IEN_EDGE_DEFAULT (_ACMP_IEN_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IEN */
|
||||
#define ACMP_IEN_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Enable */
|
||||
#define _ACMP_IEN_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */
|
||||
#define _ACMP_IEN_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */
|
||||
#define _ACMP_IEN_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */
|
||||
#define ACMP_IEN_WARMUP_DEFAULT (_ACMP_IEN_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IEN */
|
||||
|
||||
/* Bit fields for ACMP IF */
|
||||
#define _ACMP_IF_RESETVALUE 0x00000000UL /**< Default value for ACMP_IF */
|
||||
#define _ACMP_IF_MASK 0x00000003UL /**< Mask for ACMP_IF */
|
||||
#define ACMP_IF_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag */
|
||||
#define _ACMP_IF_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */
|
||||
#define _ACMP_IF_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */
|
||||
#define _ACMP_IF_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */
|
||||
#define ACMP_IF_EDGE_DEFAULT (_ACMP_IF_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IF */
|
||||
#define ACMP_IF_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag */
|
||||
#define _ACMP_IF_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */
|
||||
#define _ACMP_IF_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */
|
||||
#define _ACMP_IF_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */
|
||||
#define ACMP_IF_WARMUP_DEFAULT (_ACMP_IF_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IF */
|
||||
|
||||
/* Bit fields for ACMP IFS */
|
||||
#define _ACMP_IFS_RESETVALUE 0x00000000UL /**< Default value for ACMP_IFS */
|
||||
#define _ACMP_IFS_MASK 0x00000003UL /**< Mask for ACMP_IFS */
|
||||
#define ACMP_IFS_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag Set */
|
||||
#define _ACMP_IFS_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */
|
||||
#define _ACMP_IFS_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */
|
||||
#define _ACMP_IFS_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */
|
||||
#define ACMP_IFS_EDGE_DEFAULT (_ACMP_IFS_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IFS */
|
||||
#define ACMP_IFS_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag Set */
|
||||
#define _ACMP_IFS_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */
|
||||
#define _ACMP_IFS_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */
|
||||
#define _ACMP_IFS_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFS */
|
||||
#define ACMP_IFS_WARMUP_DEFAULT (_ACMP_IFS_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IFS */
|
||||
|
||||
/* Bit fields for ACMP IFC */
|
||||
#define _ACMP_IFC_RESETVALUE 0x00000000UL /**< Default value for ACMP_IFC */
|
||||
#define _ACMP_IFC_MASK 0x00000003UL /**< Mask for ACMP_IFC */
|
||||
#define ACMP_IFC_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag Clear */
|
||||
#define _ACMP_IFC_EDGE_SHIFT 0 /**< Shift value for ACMP_EDGE */
|
||||
#define _ACMP_IFC_EDGE_MASK 0x1UL /**< Bit mask for ACMP_EDGE */
|
||||
#define _ACMP_IFC_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */
|
||||
#define ACMP_IFC_EDGE_DEFAULT (_ACMP_IFC_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IFC */
|
||||
#define ACMP_IFC_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag Clear */
|
||||
#define _ACMP_IFC_WARMUP_SHIFT 1 /**< Shift value for ACMP_WARMUP */
|
||||
#define _ACMP_IFC_WARMUP_MASK 0x2UL /**< Bit mask for ACMP_WARMUP */
|
||||
#define _ACMP_IFC_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IFC */
|
||||
#define ACMP_IFC_WARMUP_DEFAULT (_ACMP_IFC_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IFC */
|
||||
|
||||
/* Bit fields for ACMP ROUTE */
|
||||
#define _ACMP_ROUTE_RESETVALUE 0x00000000UL /**< Default value for ACMP_ROUTE */
|
||||
#define _ACMP_ROUTE_MASK 0x00000301UL /**< Mask for ACMP_ROUTE */
|
||||
#define ACMP_ROUTE_ACMPPEN (0x1UL << 0) /**< ACMP Output Pin Enable */
|
||||
#define _ACMP_ROUTE_ACMPPEN_SHIFT 0 /**< Shift value for ACMP_ACMPPEN */
|
||||
#define _ACMP_ROUTE_ACMPPEN_MASK 0x1UL /**< Bit mask for ACMP_ACMPPEN */
|
||||
#define _ACMP_ROUTE_ACMPPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_ROUTE */
|
||||
#define ACMP_ROUTE_ACMPPEN_DEFAULT (_ACMP_ROUTE_ACMPPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_ROUTE */
|
||||
#define _ACMP_ROUTE_LOCATION_SHIFT 8 /**< Shift value for ACMP_LOCATION */
|
||||
#define _ACMP_ROUTE_LOCATION_MASK 0x300UL /**< Bit mask for ACMP_LOCATION */
|
||||
#define _ACMP_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_ROUTE */
|
||||
#define _ACMP_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for ACMP_ROUTE */
|
||||
#define _ACMP_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for ACMP_ROUTE */
|
||||
#define _ACMP_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for ACMP_ROUTE */
|
||||
#define _ACMP_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for ACMP_ROUTE */
|
||||
#define ACMP_ROUTE_LOCATION_DEFAULT (_ACMP_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_ROUTE */
|
||||
#define ACMP_ROUTE_LOCATION_LOC0 (_ACMP_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for ACMP_ROUTE */
|
||||
#define ACMP_ROUTE_LOCATION_LOC1 (_ACMP_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for ACMP_ROUTE */
|
||||
#define ACMP_ROUTE_LOCATION_LOC2 (_ACMP_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for ACMP_ROUTE */
|
||||
#define ACMP_ROUTE_LOCATION_LOC3 (_ACMP_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for ACMP_ROUTE */
|
||||
|
||||
/** @} End of group EFM32G_ACMP */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,655 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief efm32g_adc Register and Bit Field definitions
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_ADC
|
||||
* @{
|
||||
* @brief EFM32G_ADC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__IO uint32_t CMD; /**< Command Register */
|
||||
__I uint32_t STATUS; /**< Status Register */
|
||||
__IO uint32_t SINGLECTRL; /**< Single Sample Control Register */
|
||||
__IO uint32_t SCANCTRL; /**< Scan Control Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__I uint32_t SINGLEDATA; /**< Single Conversion Result Data */
|
||||
__I uint32_t SCANDATA; /**< Scan Conversion Result Data */
|
||||
__I uint32_t SINGLEDATAP; /**< Single Conversion Result Data Peek Register */
|
||||
__I uint32_t SCANDATAP; /**< Scan Sequence Result Data Peek Register */
|
||||
__IO uint32_t CAL; /**< Calibration Register */
|
||||
|
||||
uint32_t RESERVED0[1]; /**< Reserved for future use **/
|
||||
__IO uint32_t BIASPROG; /**< Bias Programming Register */
|
||||
} ADC_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_ADC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/* Bit fields for ADC CTRL */
|
||||
#define _ADC_CTRL_RESETVALUE 0x001F0000UL /**< Default value for ADC_CTRL */
|
||||
#define _ADC_CTRL_MASK 0x0F1F7F3BUL /**< Mask for ADC_CTRL */
|
||||
#define _ADC_CTRL_WARMUPMODE_SHIFT 0 /**< Shift value for ADC_WARMUPMODE */
|
||||
#define _ADC_CTRL_WARMUPMODE_MASK 0x3UL /**< Bit mask for ADC_WARMUPMODE */
|
||||
#define _ADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
|
||||
#define _ADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for ADC_CTRL */
|
||||
#define _ADC_CTRL_WARMUPMODE_FASTBG 0x00000001UL /**< Mode FASTBG for ADC_CTRL */
|
||||
#define _ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM 0x00000002UL /**< Mode KEEPSCANREFWARM for ADC_CTRL */
|
||||
#define _ADC_CTRL_WARMUPMODE_KEEPADCWARM 0x00000003UL /**< Mode KEEPADCWARM for ADC_CTRL */
|
||||
#define ADC_CTRL_WARMUPMODE_DEFAULT (_ADC_CTRL_WARMUPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CTRL */
|
||||
#define ADC_CTRL_WARMUPMODE_NORMAL (_ADC_CTRL_WARMUPMODE_NORMAL << 0) /**< Shifted mode NORMAL for ADC_CTRL */
|
||||
#define ADC_CTRL_WARMUPMODE_FASTBG (_ADC_CTRL_WARMUPMODE_FASTBG << 0) /**< Shifted mode FASTBG for ADC_CTRL */
|
||||
#define ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM (_ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM << 0) /**< Shifted mode KEEPSCANREFWARM for ADC_CTRL */
|
||||
#define ADC_CTRL_WARMUPMODE_KEEPADCWARM (_ADC_CTRL_WARMUPMODE_KEEPADCWARM << 0) /**< Shifted mode KEEPADCWARM for ADC_CTRL */
|
||||
#define ADC_CTRL_TAILGATE (0x1UL << 3) /**< Conversion Tailgating */
|
||||
#define _ADC_CTRL_TAILGATE_SHIFT 3 /**< Shift value for ADC_TAILGATE */
|
||||
#define _ADC_CTRL_TAILGATE_MASK 0x8UL /**< Bit mask for ADC_TAILGATE */
|
||||
#define _ADC_CTRL_TAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
|
||||
#define ADC_CTRL_TAILGATE_DEFAULT (_ADC_CTRL_TAILGATE_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CTRL */
|
||||
#define _ADC_CTRL_LPFMODE_SHIFT 4 /**< Shift value for ADC_LPFMODE */
|
||||
#define _ADC_CTRL_LPFMODE_MASK 0x30UL /**< Bit mask for ADC_LPFMODE */
|
||||
#define _ADC_CTRL_LPFMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
|
||||
#define _ADC_CTRL_LPFMODE_BYPASS 0x00000000UL /**< Mode BYPASS for ADC_CTRL */
|
||||
#define _ADC_CTRL_LPFMODE_DECAP 0x00000001UL /**< Mode DECAP for ADC_CTRL */
|
||||
#define _ADC_CTRL_LPFMODE_RCFILT 0x00000002UL /**< Mode RCFILT for ADC_CTRL */
|
||||
#define ADC_CTRL_LPFMODE_DEFAULT (_ADC_CTRL_LPFMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_CTRL */
|
||||
#define ADC_CTRL_LPFMODE_BYPASS (_ADC_CTRL_LPFMODE_BYPASS << 4) /**< Shifted mode BYPASS for ADC_CTRL */
|
||||
#define ADC_CTRL_LPFMODE_DECAP (_ADC_CTRL_LPFMODE_DECAP << 4) /**< Shifted mode DECAP for ADC_CTRL */
|
||||
#define ADC_CTRL_LPFMODE_RCFILT (_ADC_CTRL_LPFMODE_RCFILT << 4) /**< Shifted mode RCFILT for ADC_CTRL */
|
||||
#define _ADC_CTRL_PRESC_SHIFT 8 /**< Shift value for ADC_PRESC */
|
||||
#define _ADC_CTRL_PRESC_MASK 0x7F00UL /**< Bit mask for ADC_PRESC */
|
||||
#define _ADC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
|
||||
#define _ADC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for ADC_CTRL */
|
||||
#define ADC_CTRL_PRESC_DEFAULT (_ADC_CTRL_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CTRL */
|
||||
#define ADC_CTRL_PRESC_NODIVISION (_ADC_CTRL_PRESC_NODIVISION << 8) /**< Shifted mode NODIVISION for ADC_CTRL */
|
||||
#define _ADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for ADC_TIMEBASE */
|
||||
#define _ADC_CTRL_TIMEBASE_MASK 0x1F0000UL /**< Bit mask for ADC_TIMEBASE */
|
||||
#define _ADC_CTRL_TIMEBASE_DEFAULT 0x0000001FUL /**< Mode DEFAULT for ADC_CTRL */
|
||||
#define ADC_CTRL_TIMEBASE_DEFAULT (_ADC_CTRL_TIMEBASE_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CTRL */
|
||||
#define _ADC_CTRL_OVSRSEL_SHIFT 24 /**< Shift value for ADC_OVSRSEL */
|
||||
#define _ADC_CTRL_OVSRSEL_MASK 0xF000000UL /**< Bit mask for ADC_OVSRSEL */
|
||||
#define _ADC_CTRL_OVSRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CTRL */
|
||||
#define _ADC_CTRL_OVSRSEL_X2 0x00000000UL /**< Mode X2 for ADC_CTRL */
|
||||
#define _ADC_CTRL_OVSRSEL_X4 0x00000001UL /**< Mode X4 for ADC_CTRL */
|
||||
#define _ADC_CTRL_OVSRSEL_X8 0x00000002UL /**< Mode X8 for ADC_CTRL */
|
||||
#define _ADC_CTRL_OVSRSEL_X16 0x00000003UL /**< Mode X16 for ADC_CTRL */
|
||||
#define _ADC_CTRL_OVSRSEL_X32 0x00000004UL /**< Mode X32 for ADC_CTRL */
|
||||
#define _ADC_CTRL_OVSRSEL_X64 0x00000005UL /**< Mode X64 for ADC_CTRL */
|
||||
#define _ADC_CTRL_OVSRSEL_X128 0x00000006UL /**< Mode X128 for ADC_CTRL */
|
||||
#define _ADC_CTRL_OVSRSEL_X256 0x00000007UL /**< Mode X256 for ADC_CTRL */
|
||||
#define _ADC_CTRL_OVSRSEL_X512 0x00000008UL /**< Mode X512 for ADC_CTRL */
|
||||
#define _ADC_CTRL_OVSRSEL_X1024 0x00000009UL /**< Mode X1024 for ADC_CTRL */
|
||||
#define _ADC_CTRL_OVSRSEL_X2048 0x0000000AUL /**< Mode X2048 for ADC_CTRL */
|
||||
#define _ADC_CTRL_OVSRSEL_X4096 0x0000000BUL /**< Mode X4096 for ADC_CTRL */
|
||||
#define ADC_CTRL_OVSRSEL_DEFAULT (_ADC_CTRL_OVSRSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CTRL */
|
||||
#define ADC_CTRL_OVSRSEL_X2 (_ADC_CTRL_OVSRSEL_X2 << 24) /**< Shifted mode X2 for ADC_CTRL */
|
||||
#define ADC_CTRL_OVSRSEL_X4 (_ADC_CTRL_OVSRSEL_X4 << 24) /**< Shifted mode X4 for ADC_CTRL */
|
||||
#define ADC_CTRL_OVSRSEL_X8 (_ADC_CTRL_OVSRSEL_X8 << 24) /**< Shifted mode X8 for ADC_CTRL */
|
||||
#define ADC_CTRL_OVSRSEL_X16 (_ADC_CTRL_OVSRSEL_X16 << 24) /**< Shifted mode X16 for ADC_CTRL */
|
||||
#define ADC_CTRL_OVSRSEL_X32 (_ADC_CTRL_OVSRSEL_X32 << 24) /**< Shifted mode X32 for ADC_CTRL */
|
||||
#define ADC_CTRL_OVSRSEL_X64 (_ADC_CTRL_OVSRSEL_X64 << 24) /**< Shifted mode X64 for ADC_CTRL */
|
||||
#define ADC_CTRL_OVSRSEL_X128 (_ADC_CTRL_OVSRSEL_X128 << 24) /**< Shifted mode X128 for ADC_CTRL */
|
||||
#define ADC_CTRL_OVSRSEL_X256 (_ADC_CTRL_OVSRSEL_X256 << 24) /**< Shifted mode X256 for ADC_CTRL */
|
||||
#define ADC_CTRL_OVSRSEL_X512 (_ADC_CTRL_OVSRSEL_X512 << 24) /**< Shifted mode X512 for ADC_CTRL */
|
||||
#define ADC_CTRL_OVSRSEL_X1024 (_ADC_CTRL_OVSRSEL_X1024 << 24) /**< Shifted mode X1024 for ADC_CTRL */
|
||||
#define ADC_CTRL_OVSRSEL_X2048 (_ADC_CTRL_OVSRSEL_X2048 << 24) /**< Shifted mode X2048 for ADC_CTRL */
|
||||
#define ADC_CTRL_OVSRSEL_X4096 (_ADC_CTRL_OVSRSEL_X4096 << 24) /**< Shifted mode X4096 for ADC_CTRL */
|
||||
|
||||
/* Bit fields for ADC CMD */
|
||||
#define _ADC_CMD_RESETVALUE 0x00000000UL /**< Default value for ADC_CMD */
|
||||
#define _ADC_CMD_MASK 0x0000000FUL /**< Mask for ADC_CMD */
|
||||
#define ADC_CMD_SINGLESTART (0x1UL << 0) /**< Single Conversion Start */
|
||||
#define _ADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for ADC_SINGLESTART */
|
||||
#define _ADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for ADC_SINGLESTART */
|
||||
#define _ADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */
|
||||
#define ADC_CMD_SINGLESTART_DEFAULT (_ADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CMD */
|
||||
#define ADC_CMD_SINGLESTOP (0x1UL << 1) /**< Single Conversion Stop */
|
||||
#define _ADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for ADC_SINGLESTOP */
|
||||
#define _ADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for ADC_SINGLESTOP */
|
||||
#define _ADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */
|
||||
#define ADC_CMD_SINGLESTOP_DEFAULT (_ADC_CMD_SINGLESTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_CMD */
|
||||
#define ADC_CMD_SCANSTART (0x1UL << 2) /**< Scan Sequence Start */
|
||||
#define _ADC_CMD_SCANSTART_SHIFT 2 /**< Shift value for ADC_SCANSTART */
|
||||
#define _ADC_CMD_SCANSTART_MASK 0x4UL /**< Bit mask for ADC_SCANSTART */
|
||||
#define _ADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */
|
||||
#define ADC_CMD_SCANSTART_DEFAULT (_ADC_CMD_SCANSTART_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_CMD */
|
||||
#define ADC_CMD_SCANSTOP (0x1UL << 3) /**< Scan Sequence Stop */
|
||||
#define _ADC_CMD_SCANSTOP_SHIFT 3 /**< Shift value for ADC_SCANSTOP */
|
||||
#define _ADC_CMD_SCANSTOP_MASK 0x8UL /**< Bit mask for ADC_SCANSTOP */
|
||||
#define _ADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CMD */
|
||||
#define ADC_CMD_SCANSTOP_DEFAULT (_ADC_CMD_SCANSTOP_DEFAULT << 3) /**< Shifted mode DEFAULT for ADC_CMD */
|
||||
|
||||
/* Bit fields for ADC STATUS */
|
||||
#define _ADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for ADC_STATUS */
|
||||
#define _ADC_STATUS_MASK 0x07031303UL /**< Mask for ADC_STATUS */
|
||||
#define ADC_STATUS_SINGLEACT (0x1UL << 0) /**< Single Conversion Active */
|
||||
#define _ADC_STATUS_SINGLEACT_SHIFT 0 /**< Shift value for ADC_SINGLEACT */
|
||||
#define _ADC_STATUS_SINGLEACT_MASK 0x1UL /**< Bit mask for ADC_SINGLEACT */
|
||||
#define _ADC_STATUS_SINGLEACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
|
||||
#define ADC_STATUS_SINGLEACT_DEFAULT (_ADC_STATUS_SINGLEACT_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_STATUS */
|
||||
#define ADC_STATUS_SCANACT (0x1UL << 1) /**< Scan Conversion Active */
|
||||
#define _ADC_STATUS_SCANACT_SHIFT 1 /**< Shift value for ADC_SCANACT */
|
||||
#define _ADC_STATUS_SCANACT_MASK 0x2UL /**< Bit mask for ADC_SCANACT */
|
||||
#define _ADC_STATUS_SCANACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
|
||||
#define ADC_STATUS_SCANACT_DEFAULT (_ADC_STATUS_SCANACT_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_STATUS */
|
||||
#define ADC_STATUS_SINGLEREFWARM (0x1UL << 8) /**< Single Reference Warmed Up */
|
||||
#define _ADC_STATUS_SINGLEREFWARM_SHIFT 8 /**< Shift value for ADC_SINGLEREFWARM */
|
||||
#define _ADC_STATUS_SINGLEREFWARM_MASK 0x100UL /**< Bit mask for ADC_SINGLEREFWARM */
|
||||
#define _ADC_STATUS_SINGLEREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
|
||||
#define ADC_STATUS_SINGLEREFWARM_DEFAULT (_ADC_STATUS_SINGLEREFWARM_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_STATUS */
|
||||
#define ADC_STATUS_SCANREFWARM (0x1UL << 9) /**< Scan Reference Warmed Up */
|
||||
#define _ADC_STATUS_SCANREFWARM_SHIFT 9 /**< Shift value for ADC_SCANREFWARM */
|
||||
#define _ADC_STATUS_SCANREFWARM_MASK 0x200UL /**< Bit mask for ADC_SCANREFWARM */
|
||||
#define _ADC_STATUS_SCANREFWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
|
||||
#define ADC_STATUS_SCANREFWARM_DEFAULT (_ADC_STATUS_SCANREFWARM_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_STATUS */
|
||||
#define ADC_STATUS_WARM (0x1UL << 12) /**< ADC Warmed Up */
|
||||
#define _ADC_STATUS_WARM_SHIFT 12 /**< Shift value for ADC_WARM */
|
||||
#define _ADC_STATUS_WARM_MASK 0x1000UL /**< Bit mask for ADC_WARM */
|
||||
#define _ADC_STATUS_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
|
||||
#define ADC_STATUS_WARM_DEFAULT (_ADC_STATUS_WARM_DEFAULT << 12) /**< Shifted mode DEFAULT for ADC_STATUS */
|
||||
#define ADC_STATUS_SINGLEDV (0x1UL << 16) /**< Single Sample Data Valid */
|
||||
#define _ADC_STATUS_SINGLEDV_SHIFT 16 /**< Shift value for ADC_SINGLEDV */
|
||||
#define _ADC_STATUS_SINGLEDV_MASK 0x10000UL /**< Bit mask for ADC_SINGLEDV */
|
||||
#define _ADC_STATUS_SINGLEDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
|
||||
#define ADC_STATUS_SINGLEDV_DEFAULT (_ADC_STATUS_SINGLEDV_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_STATUS */
|
||||
#define ADC_STATUS_SCANDV (0x1UL << 17) /**< Scan Data Valid */
|
||||
#define _ADC_STATUS_SCANDV_SHIFT 17 /**< Shift value for ADC_SCANDV */
|
||||
#define _ADC_STATUS_SCANDV_MASK 0x20000UL /**< Bit mask for ADC_SCANDV */
|
||||
#define _ADC_STATUS_SCANDV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
|
||||
#define ADC_STATUS_SCANDV_DEFAULT (_ADC_STATUS_SCANDV_DEFAULT << 17) /**< Shifted mode DEFAULT for ADC_STATUS */
|
||||
#define _ADC_STATUS_SCANDATASRC_SHIFT 24 /**< Shift value for ADC_SCANDATASRC */
|
||||
#define _ADC_STATUS_SCANDATASRC_MASK 0x7000000UL /**< Bit mask for ADC_SCANDATASRC */
|
||||
#define _ADC_STATUS_SCANDATASRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_STATUS */
|
||||
#define _ADC_STATUS_SCANDATASRC_CH0 0x00000000UL /**< Mode CH0 for ADC_STATUS */
|
||||
#define _ADC_STATUS_SCANDATASRC_CH1 0x00000001UL /**< Mode CH1 for ADC_STATUS */
|
||||
#define _ADC_STATUS_SCANDATASRC_CH2 0x00000002UL /**< Mode CH2 for ADC_STATUS */
|
||||
#define _ADC_STATUS_SCANDATASRC_CH3 0x00000003UL /**< Mode CH3 for ADC_STATUS */
|
||||
#define _ADC_STATUS_SCANDATASRC_CH4 0x00000004UL /**< Mode CH4 for ADC_STATUS */
|
||||
#define _ADC_STATUS_SCANDATASRC_CH5 0x00000005UL /**< Mode CH5 for ADC_STATUS */
|
||||
#define _ADC_STATUS_SCANDATASRC_CH6 0x00000006UL /**< Mode CH6 for ADC_STATUS */
|
||||
#define _ADC_STATUS_SCANDATASRC_CH7 0x00000007UL /**< Mode CH7 for ADC_STATUS */
|
||||
#define ADC_STATUS_SCANDATASRC_DEFAULT (_ADC_STATUS_SCANDATASRC_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_STATUS */
|
||||
#define ADC_STATUS_SCANDATASRC_CH0 (_ADC_STATUS_SCANDATASRC_CH0 << 24) /**< Shifted mode CH0 for ADC_STATUS */
|
||||
#define ADC_STATUS_SCANDATASRC_CH1 (_ADC_STATUS_SCANDATASRC_CH1 << 24) /**< Shifted mode CH1 for ADC_STATUS */
|
||||
#define ADC_STATUS_SCANDATASRC_CH2 (_ADC_STATUS_SCANDATASRC_CH2 << 24) /**< Shifted mode CH2 for ADC_STATUS */
|
||||
#define ADC_STATUS_SCANDATASRC_CH3 (_ADC_STATUS_SCANDATASRC_CH3 << 24) /**< Shifted mode CH3 for ADC_STATUS */
|
||||
#define ADC_STATUS_SCANDATASRC_CH4 (_ADC_STATUS_SCANDATASRC_CH4 << 24) /**< Shifted mode CH4 for ADC_STATUS */
|
||||
#define ADC_STATUS_SCANDATASRC_CH5 (_ADC_STATUS_SCANDATASRC_CH5 << 24) /**< Shifted mode CH5 for ADC_STATUS */
|
||||
#define ADC_STATUS_SCANDATASRC_CH6 (_ADC_STATUS_SCANDATASRC_CH6 << 24) /**< Shifted mode CH6 for ADC_STATUS */
|
||||
#define ADC_STATUS_SCANDATASRC_CH7 (_ADC_STATUS_SCANDATASRC_CH7 << 24) /**< Shifted mode CH7 for ADC_STATUS */
|
||||
|
||||
/* Bit fields for ADC SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_MASK 0x71F70F37UL /**< Mask for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_REP (0x1UL << 0) /**< Single Sample Repetitive Mode */
|
||||
#define _ADC_SINGLECTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */
|
||||
#define _ADC_SINGLECTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */
|
||||
#define _ADC_SINGLECTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_REP_DEFAULT (_ADC_SINGLECTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_DIFF (0x1UL << 1) /**< Single Sample Differential Mode */
|
||||
#define _ADC_SINGLECTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */
|
||||
#define _ADC_SINGLECTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */
|
||||
#define _ADC_SINGLECTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_DIFF_DEFAULT (_ADC_SINGLECTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_ADJ (0x1UL << 2) /**< Single Sample Result Adjustment */
|
||||
#define _ADC_SINGLECTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */
|
||||
#define _ADC_SINGLECTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */
|
||||
#define _ADC_SINGLECTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_ADJ_DEFAULT (_ADC_SINGLECTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_ADJ_RIGHT (_ADC_SINGLECTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_ADJ_LEFT (_ADC_SINGLECTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_RES_SHIFT 4 /**< Shift value for ADC_RES */
|
||||
#define _ADC_SINGLECTRL_RES_MASK 0x30UL /**< Bit mask for ADC_RES */
|
||||
#define _ADC_SINGLECTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_RES_DEFAULT (_ADC_SINGLECTRL_RES_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_RES_12BIT (_ADC_SINGLECTRL_RES_12BIT << 4) /**< Shifted mode 12BIT for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_RES_8BIT (_ADC_SINGLECTRL_RES_8BIT << 4) /**< Shifted mode 8BIT for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_RES_6BIT (_ADC_SINGLECTRL_RES_6BIT << 4) /**< Shifted mode 6BIT for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_RES_OVS (_ADC_SINGLECTRL_RES_OVS << 4) /**< Shifted mode OVS for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_INPUTSEL_SHIFT 8 /**< Shift value for ADC_INPUTSEL */
|
||||
#define _ADC_SINGLECTRL_INPUTSEL_MASK 0xF00UL /**< Bit mask for ADC_INPUTSEL */
|
||||
#define _ADC_SINGLECTRL_INPUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_INPUTSEL_CH0 0x00000000UL /**< Mode CH0 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_INPUTSEL_CH0CH1 0x00000000UL /**< Mode CH0CH1 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_INPUTSEL_CH1 0x00000001UL /**< Mode CH1 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_INPUTSEL_CH2CH3 0x00000001UL /**< Mode CH2CH3 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_INPUTSEL_CH2 0x00000002UL /**< Mode CH2 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_INPUTSEL_CH4CH5 0x00000002UL /**< Mode CH4CH5 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_INPUTSEL_CH6CH7 0x00000003UL /**< Mode CH6CH7 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_INPUTSEL_CH3 0x00000003UL /**< Mode CH3 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_INPUTSEL_CH4 0x00000004UL /**< Mode CH4 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_INPUTSEL_DIFF0 0x00000004UL /**< Mode DIFF0 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_INPUTSEL_CH5 0x00000005UL /**< Mode CH5 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_INPUTSEL_CH6 0x00000006UL /**< Mode CH6 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_INPUTSEL_CH7 0x00000007UL /**< Mode CH7 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_INPUTSEL_TEMP 0x00000008UL /**< Mode TEMP for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_INPUTSEL_VDDDIV3 0x00000009UL /**< Mode VDDDIV3 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_INPUTSEL_VDD 0x0000000AUL /**< Mode VDD for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_INPUTSEL_VSS 0x0000000BUL /**< Mode VSS for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_INPUTSEL_VREFDIV2 0x0000000CUL /**< Mode VREFDIV2 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 0x0000000DUL /**< Mode DAC0OUT0 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 0x0000000EUL /**< Mode DAC0OUT1 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_INPUTSEL_DEFAULT (_ADC_SINGLECTRL_INPUTSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_INPUTSEL_CH0 (_ADC_SINGLECTRL_INPUTSEL_CH0 << 8) /**< Shifted mode CH0 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_INPUTSEL_CH0CH1 (_ADC_SINGLECTRL_INPUTSEL_CH0CH1 << 8) /**< Shifted mode CH0CH1 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_INPUTSEL_CH1 (_ADC_SINGLECTRL_INPUTSEL_CH1 << 8) /**< Shifted mode CH1 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_INPUTSEL_CH2CH3 (_ADC_SINGLECTRL_INPUTSEL_CH2CH3 << 8) /**< Shifted mode CH2CH3 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_INPUTSEL_CH2 (_ADC_SINGLECTRL_INPUTSEL_CH2 << 8) /**< Shifted mode CH2 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_INPUTSEL_CH4CH5 (_ADC_SINGLECTRL_INPUTSEL_CH4CH5 << 8) /**< Shifted mode CH4CH5 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_INPUTSEL_CH6CH7 (_ADC_SINGLECTRL_INPUTSEL_CH6CH7 << 8) /**< Shifted mode CH6CH7 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_INPUTSEL_CH3 (_ADC_SINGLECTRL_INPUTSEL_CH3 << 8) /**< Shifted mode CH3 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_INPUTSEL_CH4 (_ADC_SINGLECTRL_INPUTSEL_CH4 << 8) /**< Shifted mode CH4 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_INPUTSEL_DIFF0 (_ADC_SINGLECTRL_INPUTSEL_DIFF0 << 8) /**< Shifted mode DIFF0 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_INPUTSEL_CH5 (_ADC_SINGLECTRL_INPUTSEL_CH5 << 8) /**< Shifted mode CH5 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_INPUTSEL_CH6 (_ADC_SINGLECTRL_INPUTSEL_CH6 << 8) /**< Shifted mode CH6 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_INPUTSEL_CH7 (_ADC_SINGLECTRL_INPUTSEL_CH7 << 8) /**< Shifted mode CH7 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_INPUTSEL_TEMP (_ADC_SINGLECTRL_INPUTSEL_TEMP << 8) /**< Shifted mode TEMP for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_INPUTSEL_VDDDIV3 (_ADC_SINGLECTRL_INPUTSEL_VDDDIV3 << 8) /**< Shifted mode VDDDIV3 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_INPUTSEL_VDD (_ADC_SINGLECTRL_INPUTSEL_VDD << 8) /**< Shifted mode VDD for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_INPUTSEL_VSS (_ADC_SINGLECTRL_INPUTSEL_VSS << 8) /**< Shifted mode VSS for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_INPUTSEL_VREFDIV2 (_ADC_SINGLECTRL_INPUTSEL_VREFDIV2 << 8) /**< Shifted mode VREFDIV2 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 (_ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 << 8) /**< Shifted mode DAC0OUT0 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 (_ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 << 8) /**< Shifted mode DAC0OUT1 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_REF_SHIFT 16 /**< Shift value for ADC_REF */
|
||||
#define _ADC_SINGLECTRL_REF_MASK 0x70000UL /**< Bit mask for ADC_REF */
|
||||
#define _ADC_SINGLECTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_REF_5VDIFF 0x00000003UL /**< Mode 5VDIFF for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_REF_DEFAULT (_ADC_SINGLECTRL_REF_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_REF_1V25 (_ADC_SINGLECTRL_REF_1V25 << 16) /**< Shifted mode 1V25 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_REF_2V5 (_ADC_SINGLECTRL_REF_2V5 << 16) /**< Shifted mode 2V5 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_REF_VDD (_ADC_SINGLECTRL_REF_VDD << 16) /**< Shifted mode VDD for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_REF_5VDIFF (_ADC_SINGLECTRL_REF_5VDIFF << 16) /**< Shifted mode 5VDIFF for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_REF_EXTSINGLE (_ADC_SINGLECTRL_REF_EXTSINGLE << 16) /**< Shifted mode EXTSINGLE for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_REF_2XEXTDIFF (_ADC_SINGLECTRL_REF_2XEXTDIFF << 16) /**< Shifted mode 2XEXTDIFF for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_REF_2XVDD (_ADC_SINGLECTRL_REF_2XVDD << 16) /**< Shifted mode 2XVDD for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_AT_SHIFT 20 /**< Shift value for ADC_AT */
|
||||
#define _ADC_SINGLECTRL_AT_MASK 0xF00000UL /**< Bit mask for ADC_AT */
|
||||
#define _ADC_SINGLECTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_AT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_AT_8CYCLES 0x00000003UL /**< Mode 8CYCLES for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_AT_16CYCLES 0x00000004UL /**< Mode 16CYCLES for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_AT_32CYCLES 0x00000005UL /**< Mode 32CYCLES for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_AT_64CYCLES 0x00000006UL /**< Mode 64CYCLES for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_AT_128CYCLES 0x00000007UL /**< Mode 128CYCLES for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_AT_256CYCLES 0x00000008UL /**< Mode 256CYCLES for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_AT_DEFAULT (_ADC_SINGLECTRL_AT_DEFAULT << 20) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_AT_1CYCLE (_ADC_SINGLECTRL_AT_1CYCLE << 20) /**< Shifted mode 1CYCLE for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_AT_2CYCLES (_ADC_SINGLECTRL_AT_2CYCLES << 20) /**< Shifted mode 2CYCLES for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_AT_4CYCLES (_ADC_SINGLECTRL_AT_4CYCLES << 20) /**< Shifted mode 4CYCLES for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_AT_8CYCLES (_ADC_SINGLECTRL_AT_8CYCLES << 20) /**< Shifted mode 8CYCLES for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_AT_16CYCLES (_ADC_SINGLECTRL_AT_16CYCLES << 20) /**< Shifted mode 16CYCLES for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_AT_32CYCLES (_ADC_SINGLECTRL_AT_32CYCLES << 20) /**< Shifted mode 32CYCLES for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_AT_64CYCLES (_ADC_SINGLECTRL_AT_64CYCLES << 20) /**< Shifted mode 64CYCLES for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_AT_128CYCLES (_ADC_SINGLECTRL_AT_128CYCLES << 20) /**< Shifted mode 128CYCLES for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_AT_256CYCLES (_ADC_SINGLECTRL_AT_256CYCLES << 20) /**< Shifted mode 256CYCLES for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_PRSEN (0x1UL << 24) /**< Single Sample PRS Trigger Enable */
|
||||
#define _ADC_SINGLECTRL_PRSEN_SHIFT 24 /**< Shift value for ADC_PRSEN */
|
||||
#define _ADC_SINGLECTRL_PRSEN_MASK 0x1000000UL /**< Bit mask for ADC_PRSEN */
|
||||
#define _ADC_SINGLECTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_PRSEN_DEFAULT (_ADC_SINGLECTRL_PRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_PRSSEL_SHIFT 28 /**< Shift value for ADC_PRSSEL */
|
||||
#define _ADC_SINGLECTRL_PRSSEL_MASK 0x70000000UL /**< Bit mask for ADC_PRSSEL */
|
||||
#define _ADC_SINGLECTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SINGLECTRL */
|
||||
#define _ADC_SINGLECTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_PRSSEL_DEFAULT (_ADC_SINGLECTRL_PRSSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_PRSSEL_PRSCH0 (_ADC_SINGLECTRL_PRSSEL_PRSCH0 << 28) /**< Shifted mode PRSCH0 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_PRSSEL_PRSCH1 (_ADC_SINGLECTRL_PRSSEL_PRSCH1 << 28) /**< Shifted mode PRSCH1 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_PRSSEL_PRSCH2 (_ADC_SINGLECTRL_PRSSEL_PRSCH2 << 28) /**< Shifted mode PRSCH2 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_PRSSEL_PRSCH3 (_ADC_SINGLECTRL_PRSSEL_PRSCH3 << 28) /**< Shifted mode PRSCH3 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_PRSSEL_PRSCH4 (_ADC_SINGLECTRL_PRSSEL_PRSCH4 << 28) /**< Shifted mode PRSCH4 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_PRSSEL_PRSCH5 (_ADC_SINGLECTRL_PRSSEL_PRSCH5 << 28) /**< Shifted mode PRSCH5 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_PRSSEL_PRSCH6 (_ADC_SINGLECTRL_PRSSEL_PRSCH6 << 28) /**< Shifted mode PRSCH6 for ADC_SINGLECTRL */
|
||||
#define ADC_SINGLECTRL_PRSSEL_PRSCH7 (_ADC_SINGLECTRL_PRSSEL_PRSCH7 << 28) /**< Shifted mode PRSCH7 for ADC_SINGLECTRL */
|
||||
|
||||
/* Bit fields for ADC SCANCTRL */
|
||||
#define _ADC_SCANCTRL_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_MASK 0x71F7FF37UL /**< Mask for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_REP (0x1UL << 0) /**< Scan Sequence Repetitive Mode */
|
||||
#define _ADC_SCANCTRL_REP_SHIFT 0 /**< Shift value for ADC_REP */
|
||||
#define _ADC_SCANCTRL_REP_MASK 0x1UL /**< Bit mask for ADC_REP */
|
||||
#define _ADC_SCANCTRL_REP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_REP_DEFAULT (_ADC_SCANCTRL_REP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_DIFF (0x1UL << 1) /**< Scan Sequence Differential Mode */
|
||||
#define _ADC_SCANCTRL_DIFF_SHIFT 1 /**< Shift value for ADC_DIFF */
|
||||
#define _ADC_SCANCTRL_DIFF_MASK 0x2UL /**< Bit mask for ADC_DIFF */
|
||||
#define _ADC_SCANCTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_DIFF_DEFAULT (_ADC_SCANCTRL_DIFF_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_ADJ (0x1UL << 2) /**< Scan Sequence Result Adjustment */
|
||||
#define _ADC_SCANCTRL_ADJ_SHIFT 2 /**< Shift value for ADC_ADJ */
|
||||
#define _ADC_SCANCTRL_ADJ_MASK 0x4UL /**< Bit mask for ADC_ADJ */
|
||||
#define _ADC_SCANCTRL_ADJ_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_ADJ_RIGHT 0x00000000UL /**< Mode RIGHT for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_ADJ_LEFT 0x00000001UL /**< Mode LEFT for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_ADJ_DEFAULT (_ADC_SCANCTRL_ADJ_DEFAULT << 2) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_ADJ_RIGHT (_ADC_SCANCTRL_ADJ_RIGHT << 2) /**< Shifted mode RIGHT for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_ADJ_LEFT (_ADC_SCANCTRL_ADJ_LEFT << 2) /**< Shifted mode LEFT for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_RES_SHIFT 4 /**< Shift value for ADC_RES */
|
||||
#define _ADC_SCANCTRL_RES_MASK 0x30UL /**< Bit mask for ADC_RES */
|
||||
#define _ADC_SCANCTRL_RES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_RES_12BIT 0x00000000UL /**< Mode 12BIT for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_RES_8BIT 0x00000001UL /**< Mode 8BIT for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_RES_6BIT 0x00000002UL /**< Mode 6BIT for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_RES_OVS 0x00000003UL /**< Mode OVS for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_RES_DEFAULT (_ADC_SCANCTRL_RES_DEFAULT << 4) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_RES_12BIT (_ADC_SCANCTRL_RES_12BIT << 4) /**< Shifted mode 12BIT for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_RES_8BIT (_ADC_SCANCTRL_RES_8BIT << 4) /**< Shifted mode 8BIT for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_RES_6BIT (_ADC_SCANCTRL_RES_6BIT << 4) /**< Shifted mode 6BIT for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_RES_OVS (_ADC_SCANCTRL_RES_OVS << 4) /**< Shifted mode OVS for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_INPUTMASK_SHIFT 8 /**< Shift value for ADC_INPUTMASK */
|
||||
#define _ADC_SCANCTRL_INPUTMASK_MASK 0xFF00UL /**< Bit mask for ADC_INPUTMASK */
|
||||
#define _ADC_SCANCTRL_INPUTMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_INPUTMASK_CH0 0x00000001UL /**< Mode CH0 for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_INPUTMASK_CH0CH1 0x00000001UL /**< Mode CH0CH1 for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_INPUTMASK_CH1 0x00000002UL /**< Mode CH1 for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_INPUTMASK_CH2CH3 0x00000002UL /**< Mode CH2CH3 for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_INPUTMASK_CH2 0x00000004UL /**< Mode CH2 for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_INPUTMASK_CH4CH5 0x00000004UL /**< Mode CH4CH5 for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_INPUTMASK_CH6CH7 0x00000008UL /**< Mode CH6CH7 for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_INPUTMASK_CH3 0x00000008UL /**< Mode CH3 for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_INPUTMASK_CH4 0x00000010UL /**< Mode CH4 for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_INPUTMASK_CH5 0x00000020UL /**< Mode CH5 for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_INPUTMASK_CH6 0x00000040UL /**< Mode CH6 for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_INPUTMASK_CH7 0x00000080UL /**< Mode CH7 for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_INPUTMASK_DEFAULT (_ADC_SCANCTRL_INPUTMASK_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_INPUTMASK_CH0 (_ADC_SCANCTRL_INPUTMASK_CH0 << 8) /**< Shifted mode CH0 for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_INPUTMASK_CH0CH1 (_ADC_SCANCTRL_INPUTMASK_CH0CH1 << 8) /**< Shifted mode CH0CH1 for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_INPUTMASK_CH1 (_ADC_SCANCTRL_INPUTMASK_CH1 << 8) /**< Shifted mode CH1 for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_INPUTMASK_CH2CH3 (_ADC_SCANCTRL_INPUTMASK_CH2CH3 << 8) /**< Shifted mode CH2CH3 for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_INPUTMASK_CH2 (_ADC_SCANCTRL_INPUTMASK_CH2 << 8) /**< Shifted mode CH2 for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_INPUTMASK_CH4CH5 (_ADC_SCANCTRL_INPUTMASK_CH4CH5 << 8) /**< Shifted mode CH4CH5 for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_INPUTMASK_CH6CH7 (_ADC_SCANCTRL_INPUTMASK_CH6CH7 << 8) /**< Shifted mode CH6CH7 for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_INPUTMASK_CH3 (_ADC_SCANCTRL_INPUTMASK_CH3 << 8) /**< Shifted mode CH3 for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_INPUTMASK_CH4 (_ADC_SCANCTRL_INPUTMASK_CH4 << 8) /**< Shifted mode CH4 for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_INPUTMASK_CH5 (_ADC_SCANCTRL_INPUTMASK_CH5 << 8) /**< Shifted mode CH5 for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_INPUTMASK_CH6 (_ADC_SCANCTRL_INPUTMASK_CH6 << 8) /**< Shifted mode CH6 for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_INPUTMASK_CH7 (_ADC_SCANCTRL_INPUTMASK_CH7 << 8) /**< Shifted mode CH7 for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_REF_SHIFT 16 /**< Shift value for ADC_REF */
|
||||
#define _ADC_SCANCTRL_REF_MASK 0x70000UL /**< Bit mask for ADC_REF */
|
||||
#define _ADC_SCANCTRL_REF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_REF_1V25 0x00000000UL /**< Mode 1V25 for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_REF_2V5 0x00000001UL /**< Mode 2V5 for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_REF_VDD 0x00000002UL /**< Mode VDD for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_REF_5VDIFF 0x00000003UL /**< Mode 5VDIFF for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_REF_EXTSINGLE 0x00000004UL /**< Mode EXTSINGLE for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_REF_2XEXTDIFF 0x00000005UL /**< Mode 2XEXTDIFF for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_REF_2XVDD 0x00000006UL /**< Mode 2XVDD for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_REF_DEFAULT (_ADC_SCANCTRL_REF_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_REF_1V25 (_ADC_SCANCTRL_REF_1V25 << 16) /**< Shifted mode 1V25 for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_REF_2V5 (_ADC_SCANCTRL_REF_2V5 << 16) /**< Shifted mode 2V5 for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_REF_VDD (_ADC_SCANCTRL_REF_VDD << 16) /**< Shifted mode VDD for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_REF_5VDIFF (_ADC_SCANCTRL_REF_5VDIFF << 16) /**< Shifted mode 5VDIFF for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_REF_EXTSINGLE (_ADC_SCANCTRL_REF_EXTSINGLE << 16) /**< Shifted mode EXTSINGLE for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_REF_2XEXTDIFF (_ADC_SCANCTRL_REF_2XEXTDIFF << 16) /**< Shifted mode 2XEXTDIFF for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_REF_2XVDD (_ADC_SCANCTRL_REF_2XVDD << 16) /**< Shifted mode 2XVDD for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_AT_SHIFT 20 /**< Shift value for ADC_AT */
|
||||
#define _ADC_SCANCTRL_AT_MASK 0xF00000UL /**< Bit mask for ADC_AT */
|
||||
#define _ADC_SCANCTRL_AT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_AT_1CYCLE 0x00000000UL /**< Mode 1CYCLE for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_AT_2CYCLES 0x00000001UL /**< Mode 2CYCLES for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_AT_4CYCLES 0x00000002UL /**< Mode 4CYCLES for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_AT_8CYCLES 0x00000003UL /**< Mode 8CYCLES for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_AT_16CYCLES 0x00000004UL /**< Mode 16CYCLES for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_AT_32CYCLES 0x00000005UL /**< Mode 32CYCLES for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_AT_64CYCLES 0x00000006UL /**< Mode 64CYCLES for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_AT_128CYCLES 0x00000007UL /**< Mode 128CYCLES for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_AT_256CYCLES 0x00000008UL /**< Mode 256CYCLES for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_AT_DEFAULT (_ADC_SCANCTRL_AT_DEFAULT << 20) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_AT_1CYCLE (_ADC_SCANCTRL_AT_1CYCLE << 20) /**< Shifted mode 1CYCLE for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_AT_2CYCLES (_ADC_SCANCTRL_AT_2CYCLES << 20) /**< Shifted mode 2CYCLES for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_AT_4CYCLES (_ADC_SCANCTRL_AT_4CYCLES << 20) /**< Shifted mode 4CYCLES for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_AT_8CYCLES (_ADC_SCANCTRL_AT_8CYCLES << 20) /**< Shifted mode 8CYCLES for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_AT_16CYCLES (_ADC_SCANCTRL_AT_16CYCLES << 20) /**< Shifted mode 16CYCLES for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_AT_32CYCLES (_ADC_SCANCTRL_AT_32CYCLES << 20) /**< Shifted mode 32CYCLES for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_AT_64CYCLES (_ADC_SCANCTRL_AT_64CYCLES << 20) /**< Shifted mode 64CYCLES for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_AT_128CYCLES (_ADC_SCANCTRL_AT_128CYCLES << 20) /**< Shifted mode 128CYCLES for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_AT_256CYCLES (_ADC_SCANCTRL_AT_256CYCLES << 20) /**< Shifted mode 256CYCLES for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_PRSEN (0x1UL << 24) /**< Scan Sequence PRS Trigger Enable */
|
||||
#define _ADC_SCANCTRL_PRSEN_SHIFT 24 /**< Shift value for ADC_PRSEN */
|
||||
#define _ADC_SCANCTRL_PRSEN_MASK 0x1000000UL /**< Bit mask for ADC_PRSEN */
|
||||
#define _ADC_SCANCTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_PRSEN_DEFAULT (_ADC_SCANCTRL_PRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_PRSSEL_SHIFT 28 /**< Shift value for ADC_PRSSEL */
|
||||
#define _ADC_SCANCTRL_PRSSEL_MASK 0x70000000UL /**< Bit mask for ADC_PRSSEL */
|
||||
#define _ADC_SCANCTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for ADC_SCANCTRL */
|
||||
#define _ADC_SCANCTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_PRSSEL_DEFAULT (_ADC_SCANCTRL_PRSSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_PRSSEL_PRSCH0 (_ADC_SCANCTRL_PRSSEL_PRSCH0 << 28) /**< Shifted mode PRSCH0 for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_PRSSEL_PRSCH1 (_ADC_SCANCTRL_PRSSEL_PRSCH1 << 28) /**< Shifted mode PRSCH1 for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_PRSSEL_PRSCH2 (_ADC_SCANCTRL_PRSSEL_PRSCH2 << 28) /**< Shifted mode PRSCH2 for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_PRSSEL_PRSCH3 (_ADC_SCANCTRL_PRSSEL_PRSCH3 << 28) /**< Shifted mode PRSCH3 for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_PRSSEL_PRSCH4 (_ADC_SCANCTRL_PRSSEL_PRSCH4 << 28) /**< Shifted mode PRSCH4 for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_PRSSEL_PRSCH5 (_ADC_SCANCTRL_PRSSEL_PRSCH5 << 28) /**< Shifted mode PRSCH5 for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_PRSSEL_PRSCH6 (_ADC_SCANCTRL_PRSSEL_PRSCH6 << 28) /**< Shifted mode PRSCH6 for ADC_SCANCTRL */
|
||||
#define ADC_SCANCTRL_PRSSEL_PRSCH7 (_ADC_SCANCTRL_PRSSEL_PRSCH7 << 28) /**< Shifted mode PRSCH7 for ADC_SCANCTRL */
|
||||
|
||||
/* Bit fields for ADC IEN */
|
||||
#define _ADC_IEN_RESETVALUE 0x00000000UL /**< Default value for ADC_IEN */
|
||||
#define _ADC_IEN_MASK 0x00000303UL /**< Mask for ADC_IEN */
|
||||
#define ADC_IEN_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Enable */
|
||||
#define _ADC_IEN_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */
|
||||
#define _ADC_IEN_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */
|
||||
#define _ADC_IEN_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
|
||||
#define ADC_IEN_SINGLE_DEFAULT (_ADC_IEN_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IEN */
|
||||
#define ADC_IEN_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Enable */
|
||||
#define _ADC_IEN_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */
|
||||
#define _ADC_IEN_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */
|
||||
#define _ADC_IEN_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
|
||||
#define ADC_IEN_SCAN_DEFAULT (_ADC_IEN_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IEN */
|
||||
#define ADC_IEN_SINGLEOF (0x1UL << 8) /**< Single Result Overflow Interrupt Enable */
|
||||
#define _ADC_IEN_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */
|
||||
#define _ADC_IEN_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */
|
||||
#define _ADC_IEN_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
|
||||
#define ADC_IEN_SINGLEOF_DEFAULT (_ADC_IEN_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IEN */
|
||||
#define ADC_IEN_SCANOF (0x1UL << 9) /**< Scan Result Overflow Interrupt Enable */
|
||||
#define _ADC_IEN_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */
|
||||
#define _ADC_IEN_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */
|
||||
#define _ADC_IEN_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IEN */
|
||||
#define ADC_IEN_SCANOF_DEFAULT (_ADC_IEN_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IEN */
|
||||
|
||||
/* Bit fields for ADC IF */
|
||||
#define _ADC_IF_RESETVALUE 0x00000000UL /**< Default value for ADC_IF */
|
||||
#define _ADC_IF_MASK 0x00000303UL /**< Mask for ADC_IF */
|
||||
#define ADC_IF_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Flag */
|
||||
#define _ADC_IF_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */
|
||||
#define _ADC_IF_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */
|
||||
#define _ADC_IF_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
|
||||
#define ADC_IF_SINGLE_DEFAULT (_ADC_IF_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IF */
|
||||
#define ADC_IF_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Flag */
|
||||
#define _ADC_IF_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */
|
||||
#define _ADC_IF_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */
|
||||
#define _ADC_IF_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
|
||||
#define ADC_IF_SCAN_DEFAULT (_ADC_IF_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IF */
|
||||
#define ADC_IF_SINGLEOF (0x1UL << 8) /**< Single Result Overflow Interrupt Flag */
|
||||
#define _ADC_IF_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */
|
||||
#define _ADC_IF_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */
|
||||
#define _ADC_IF_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
|
||||
#define ADC_IF_SINGLEOF_DEFAULT (_ADC_IF_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IF */
|
||||
#define ADC_IF_SCANOF (0x1UL << 9) /**< Scan Result Overflow Interrupt Flag */
|
||||
#define _ADC_IF_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */
|
||||
#define _ADC_IF_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */
|
||||
#define _ADC_IF_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IF */
|
||||
#define ADC_IF_SCANOF_DEFAULT (_ADC_IF_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IF */
|
||||
|
||||
/* Bit fields for ADC IFS */
|
||||
#define _ADC_IFS_RESETVALUE 0x00000000UL /**< Default value for ADC_IFS */
|
||||
#define _ADC_IFS_MASK 0x00000303UL /**< Mask for ADC_IFS */
|
||||
#define ADC_IFS_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Flag Set */
|
||||
#define _ADC_IFS_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */
|
||||
#define _ADC_IFS_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */
|
||||
#define _ADC_IFS_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
|
||||
#define ADC_IFS_SINGLE_DEFAULT (_ADC_IFS_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IFS */
|
||||
#define ADC_IFS_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Flag Set */
|
||||
#define _ADC_IFS_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */
|
||||
#define _ADC_IFS_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */
|
||||
#define _ADC_IFS_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
|
||||
#define ADC_IFS_SCAN_DEFAULT (_ADC_IFS_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IFS */
|
||||
#define ADC_IFS_SINGLEOF (0x1UL << 8) /**< Single Result Overflow Interrupt Flag Set */
|
||||
#define _ADC_IFS_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */
|
||||
#define _ADC_IFS_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */
|
||||
#define _ADC_IFS_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
|
||||
#define ADC_IFS_SINGLEOF_DEFAULT (_ADC_IFS_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFS */
|
||||
#define ADC_IFS_SCANOF (0x1UL << 9) /**< Scan Result Overflow Interrupt Flag Set */
|
||||
#define _ADC_IFS_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */
|
||||
#define _ADC_IFS_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */
|
||||
#define _ADC_IFS_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFS */
|
||||
#define ADC_IFS_SCANOF_DEFAULT (_ADC_IFS_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFS */
|
||||
|
||||
/* Bit fields for ADC IFC */
|
||||
#define _ADC_IFC_RESETVALUE 0x00000000UL /**< Default value for ADC_IFC */
|
||||
#define _ADC_IFC_MASK 0x00000303UL /**< Mask for ADC_IFC */
|
||||
#define ADC_IFC_SINGLE (0x1UL << 0) /**< Single Conversion Complete Interrupt Flag Clear */
|
||||
#define _ADC_IFC_SINGLE_SHIFT 0 /**< Shift value for ADC_SINGLE */
|
||||
#define _ADC_IFC_SINGLE_MASK 0x1UL /**< Bit mask for ADC_SINGLE */
|
||||
#define _ADC_IFC_SINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
|
||||
#define ADC_IFC_SINGLE_DEFAULT (_ADC_IFC_SINGLE_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_IFC */
|
||||
#define ADC_IFC_SCAN (0x1UL << 1) /**< Scan Conversion Complete Interrupt Flag Clear */
|
||||
#define _ADC_IFC_SCAN_SHIFT 1 /**< Shift value for ADC_SCAN */
|
||||
#define _ADC_IFC_SCAN_MASK 0x2UL /**< Bit mask for ADC_SCAN */
|
||||
#define _ADC_IFC_SCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
|
||||
#define ADC_IFC_SCAN_DEFAULT (_ADC_IFC_SCAN_DEFAULT << 1) /**< Shifted mode DEFAULT for ADC_IFC */
|
||||
#define ADC_IFC_SINGLEOF (0x1UL << 8) /**< Single Result Overflow Interrupt Flag Clear */
|
||||
#define _ADC_IFC_SINGLEOF_SHIFT 8 /**< Shift value for ADC_SINGLEOF */
|
||||
#define _ADC_IFC_SINGLEOF_MASK 0x100UL /**< Bit mask for ADC_SINGLEOF */
|
||||
#define _ADC_IFC_SINGLEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
|
||||
#define ADC_IFC_SINGLEOF_DEFAULT (_ADC_IFC_SINGLEOF_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_IFC */
|
||||
#define ADC_IFC_SCANOF (0x1UL << 9) /**< Scan Result Overflow Interrupt Flag Clear */
|
||||
#define _ADC_IFC_SCANOF_SHIFT 9 /**< Shift value for ADC_SCANOF */
|
||||
#define _ADC_IFC_SCANOF_MASK 0x200UL /**< Bit mask for ADC_SCANOF */
|
||||
#define _ADC_IFC_SCANOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_IFC */
|
||||
#define ADC_IFC_SCANOF_DEFAULT (_ADC_IFC_SCANOF_DEFAULT << 9) /**< Shifted mode DEFAULT for ADC_IFC */
|
||||
|
||||
/* Bit fields for ADC SINGLEDATA */
|
||||
#define _ADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATA */
|
||||
#define _ADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATA */
|
||||
#define _ADC_SINGLEDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */
|
||||
#define _ADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */
|
||||
#define _ADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATA */
|
||||
#define ADC_SINGLEDATA_DATA_DEFAULT (_ADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATA */
|
||||
|
||||
/* Bit fields for ADC SCANDATA */
|
||||
#define _ADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATA */
|
||||
#define _ADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATA */
|
||||
#define _ADC_SCANDATA_DATA_SHIFT 0 /**< Shift value for ADC_DATA */
|
||||
#define _ADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATA */
|
||||
#define _ADC_SCANDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATA */
|
||||
#define ADC_SCANDATA_DATA_DEFAULT (_ADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATA */
|
||||
|
||||
/* Bit fields for ADC SINGLEDATAP */
|
||||
#define _ADC_SINGLEDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SINGLEDATAP */
|
||||
#define _ADC_SINGLEDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SINGLEDATAP */
|
||||
#define _ADC_SINGLEDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */
|
||||
#define _ADC_SINGLEDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */
|
||||
#define _ADC_SINGLEDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SINGLEDATAP */
|
||||
#define ADC_SINGLEDATAP_DATAP_DEFAULT (_ADC_SINGLEDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SINGLEDATAP */
|
||||
|
||||
/* Bit fields for ADC SCANDATAP */
|
||||
#define _ADC_SCANDATAP_RESETVALUE 0x00000000UL /**< Default value for ADC_SCANDATAP */
|
||||
#define _ADC_SCANDATAP_MASK 0xFFFFFFFFUL /**< Mask for ADC_SCANDATAP */
|
||||
#define _ADC_SCANDATAP_DATAP_SHIFT 0 /**< Shift value for ADC_DATAP */
|
||||
#define _ADC_SCANDATAP_DATAP_MASK 0xFFFFFFFFUL /**< Bit mask for ADC_DATAP */
|
||||
#define _ADC_SCANDATAP_DATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_SCANDATAP */
|
||||
#define ADC_SCANDATAP_DATAP_DEFAULT (_ADC_SCANDATAP_DATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_SCANDATAP */
|
||||
|
||||
/* Bit fields for ADC CAL */
|
||||
#define _ADC_CAL_RESETVALUE 0x3F003F00UL /**< Default value for ADC_CAL */
|
||||
#define _ADC_CAL_MASK 0x7F7F7F7FUL /**< Mask for ADC_CAL */
|
||||
#define _ADC_CAL_SINGLEOFFSET_SHIFT 0 /**< Shift value for ADC_SINGLEOFFSET */
|
||||
#define _ADC_CAL_SINGLEOFFSET_MASK 0x7FUL /**< Bit mask for ADC_SINGLEOFFSET */
|
||||
#define _ADC_CAL_SINGLEOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */
|
||||
#define ADC_CAL_SINGLEOFFSET_DEFAULT (_ADC_CAL_SINGLEOFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_CAL */
|
||||
#define _ADC_CAL_SINGLEGAIN_SHIFT 8 /**< Shift value for ADC_SINGLEGAIN */
|
||||
#define _ADC_CAL_SINGLEGAIN_MASK 0x7F00UL /**< Bit mask for ADC_SINGLEGAIN */
|
||||
#define _ADC_CAL_SINGLEGAIN_DEFAULT 0x0000003FUL /**< Mode DEFAULT for ADC_CAL */
|
||||
#define ADC_CAL_SINGLEGAIN_DEFAULT (_ADC_CAL_SINGLEGAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_CAL */
|
||||
#define _ADC_CAL_SCANOFFSET_SHIFT 16 /**< Shift value for ADC_SCANOFFSET */
|
||||
#define _ADC_CAL_SCANOFFSET_MASK 0x7F0000UL /**< Bit mask for ADC_SCANOFFSET */
|
||||
#define _ADC_CAL_SCANOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for ADC_CAL */
|
||||
#define ADC_CAL_SCANOFFSET_DEFAULT (_ADC_CAL_SCANOFFSET_DEFAULT << 16) /**< Shifted mode DEFAULT for ADC_CAL */
|
||||
#define _ADC_CAL_SCANGAIN_SHIFT 24 /**< Shift value for ADC_SCANGAIN */
|
||||
#define _ADC_CAL_SCANGAIN_MASK 0x7F000000UL /**< Bit mask for ADC_SCANGAIN */
|
||||
#define _ADC_CAL_SCANGAIN_DEFAULT 0x0000003FUL /**< Mode DEFAULT for ADC_CAL */
|
||||
#define ADC_CAL_SCANGAIN_DEFAULT (_ADC_CAL_SCANGAIN_DEFAULT << 24) /**< Shifted mode DEFAULT for ADC_CAL */
|
||||
|
||||
/* Bit fields for ADC BIASPROG */
|
||||
#define _ADC_BIASPROG_RESETVALUE 0x00000747UL /**< Default value for ADC_BIASPROG */
|
||||
#define _ADC_BIASPROG_MASK 0x00000F4FUL /**< Mask for ADC_BIASPROG */
|
||||
#define _ADC_BIASPROG_BIASPROG_SHIFT 0 /**< Shift value for ADC_BIASPROG */
|
||||
#define _ADC_BIASPROG_BIASPROG_MASK 0xFUL /**< Bit mask for ADC_BIASPROG */
|
||||
#define _ADC_BIASPROG_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_BIASPROG */
|
||||
#define ADC_BIASPROG_BIASPROG_DEFAULT (_ADC_BIASPROG_BIASPROG_DEFAULT << 0) /**< Shifted mode DEFAULT for ADC_BIASPROG */
|
||||
#define ADC_BIASPROG_HALFBIAS (0x1UL << 6) /**< Half Bias Current */
|
||||
#define _ADC_BIASPROG_HALFBIAS_SHIFT 6 /**< Shift value for ADC_HALFBIAS */
|
||||
#define _ADC_BIASPROG_HALFBIAS_MASK 0x40UL /**< Bit mask for ADC_HALFBIAS */
|
||||
#define _ADC_BIASPROG_HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ADC_BIASPROG */
|
||||
#define ADC_BIASPROG_HALFBIAS_DEFAULT (_ADC_BIASPROG_HALFBIAS_DEFAULT << 6) /**< Shifted mode DEFAULT for ADC_BIASPROG */
|
||||
#define _ADC_BIASPROG_COMPBIAS_SHIFT 8 /**< Shift value for ADC_COMPBIAS */
|
||||
#define _ADC_BIASPROG_COMPBIAS_MASK 0xF00UL /**< Bit mask for ADC_COMPBIAS */
|
||||
#define _ADC_BIASPROG_COMPBIAS_DEFAULT 0x00000007UL /**< Mode DEFAULT for ADC_BIASPROG */
|
||||
#define ADC_BIASPROG_COMPBIAS_DEFAULT (_ADC_BIASPROG_COMPBIAS_DEFAULT << 8) /**< Shifted mode DEFAULT for ADC_BIASPROG */
|
||||
|
||||
/** @} End of group EFM32G_ADC */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,235 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief efm32g_aes Register and Bit Field definitions
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_AES
|
||||
* @{
|
||||
* @brief EFM32G_AES Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__IO uint32_t CMD; /**< Command Register */
|
||||
__I uint32_t STATUS; /**< Status Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IO uint32_t DATA; /**< DATA Register */
|
||||
__IO uint32_t XORDATA; /**< XORDATA Register */
|
||||
uint32_t RESERVED0[3]; /**< Reserved for future use **/
|
||||
__IO uint32_t KEYLA; /**< KEY Low Register */
|
||||
__IO uint32_t KEYLB; /**< KEY Low Register */
|
||||
__IO uint32_t KEYLC; /**< KEY Low Register */
|
||||
__IO uint32_t KEYLD; /**< KEY Low Register */
|
||||
__IO uint32_t KEYHA; /**< KEY High Register */
|
||||
__IO uint32_t KEYHB; /**< KEY High Register */
|
||||
__IO uint32_t KEYHC; /**< KEY High Register */
|
||||
__IO uint32_t KEYHD; /**< KEY High Register */
|
||||
} AES_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_AES_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/* Bit fields for AES CTRL */
|
||||
#define _AES_CTRL_RESETVALUE 0x00000000UL /**< Default value for AES_CTRL */
|
||||
#define _AES_CTRL_MASK 0x00000037UL /**< Mask for AES_CTRL */
|
||||
#define AES_CTRL_DECRYPT (0x1UL << 0) /**< Decryption/Encryption Mode */
|
||||
#define _AES_CTRL_DECRYPT_SHIFT 0 /**< Shift value for AES_DECRYPT */
|
||||
#define _AES_CTRL_DECRYPT_MASK 0x1UL /**< Bit mask for AES_DECRYPT */
|
||||
#define _AES_CTRL_DECRYPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
|
||||
#define AES_CTRL_DECRYPT_DEFAULT (_AES_CTRL_DECRYPT_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CTRL */
|
||||
#define AES_CTRL_AES256 (0x1UL << 1) /**< AES-256 Mode */
|
||||
#define _AES_CTRL_AES256_SHIFT 1 /**< Shift value for AES_AES256 */
|
||||
#define _AES_CTRL_AES256_MASK 0x2UL /**< Bit mask for AES_AES256 */
|
||||
#define _AES_CTRL_AES256_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
|
||||
#define AES_CTRL_AES256_DEFAULT (_AES_CTRL_AES256_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CTRL */
|
||||
#define AES_CTRL_KEYBUFEN (0x1UL << 2) /**< Key Buffer Enable */
|
||||
#define _AES_CTRL_KEYBUFEN_SHIFT 2 /**< Shift value for AES_KEYBUFEN */
|
||||
#define _AES_CTRL_KEYBUFEN_MASK 0x4UL /**< Bit mask for AES_KEYBUFEN */
|
||||
#define _AES_CTRL_KEYBUFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
|
||||
#define AES_CTRL_KEYBUFEN_DEFAULT (_AES_CTRL_KEYBUFEN_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_CTRL */
|
||||
#define AES_CTRL_DATASTART (0x1UL << 4) /**< AES_DATA Write Start */
|
||||
#define _AES_CTRL_DATASTART_SHIFT 4 /**< Shift value for AES_DATASTART */
|
||||
#define _AES_CTRL_DATASTART_MASK 0x10UL /**< Bit mask for AES_DATASTART */
|
||||
#define _AES_CTRL_DATASTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
|
||||
#define AES_CTRL_DATASTART_DEFAULT (_AES_CTRL_DATASTART_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_CTRL */
|
||||
#define AES_CTRL_XORSTART (0x1UL << 5) /**< AES_XORDATA Write Start */
|
||||
#define _AES_CTRL_XORSTART_SHIFT 5 /**< Shift value for AES_XORSTART */
|
||||
#define _AES_CTRL_XORSTART_MASK 0x20UL /**< Bit mask for AES_XORSTART */
|
||||
#define _AES_CTRL_XORSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */
|
||||
#define AES_CTRL_XORSTART_DEFAULT (_AES_CTRL_XORSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_CTRL */
|
||||
|
||||
/* Bit fields for AES CMD */
|
||||
#define _AES_CMD_RESETVALUE 0x00000000UL /**< Default value for AES_CMD */
|
||||
#define _AES_CMD_MASK 0x00000003UL /**< Mask for AES_CMD */
|
||||
#define AES_CMD_START (0x1UL << 0) /**< Encryption/Decryption Start */
|
||||
#define _AES_CMD_START_SHIFT 0 /**< Shift value for AES_START */
|
||||
#define _AES_CMD_START_MASK 0x1UL /**< Bit mask for AES_START */
|
||||
#define _AES_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */
|
||||
#define AES_CMD_START_DEFAULT (_AES_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CMD */
|
||||
#define AES_CMD_STOP (0x1UL << 1) /**< Encryption/Decryption Stop */
|
||||
#define _AES_CMD_STOP_SHIFT 1 /**< Shift value for AES_STOP */
|
||||
#define _AES_CMD_STOP_MASK 0x2UL /**< Bit mask for AES_STOP */
|
||||
#define _AES_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */
|
||||
#define AES_CMD_STOP_DEFAULT (_AES_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CMD */
|
||||
|
||||
/* Bit fields for AES STATUS */
|
||||
#define _AES_STATUS_RESETVALUE 0x00000000UL /**< Default value for AES_STATUS */
|
||||
#define _AES_STATUS_MASK 0x00000001UL /**< Mask for AES_STATUS */
|
||||
#define AES_STATUS_RUNNING (0x1UL << 0) /**< AES Running */
|
||||
#define _AES_STATUS_RUNNING_SHIFT 0 /**< Shift value for AES_RUNNING */
|
||||
#define _AES_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for AES_RUNNING */
|
||||
#define _AES_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */
|
||||
#define AES_STATUS_RUNNING_DEFAULT (_AES_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_STATUS */
|
||||
|
||||
/* Bit fields for AES IEN */
|
||||
#define _AES_IEN_RESETVALUE 0x00000000UL /**< Default value for AES_IEN */
|
||||
#define _AES_IEN_MASK 0x00000001UL /**< Mask for AES_IEN */
|
||||
#define AES_IEN_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Enable */
|
||||
#define _AES_IEN_DONE_SHIFT 0 /**< Shift value for AES_DONE */
|
||||
#define _AES_IEN_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */
|
||||
#define _AES_IEN_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */
|
||||
#define AES_IEN_DONE_DEFAULT (_AES_IEN_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IEN */
|
||||
|
||||
/* Bit fields for AES IF */
|
||||
#define _AES_IF_RESETVALUE 0x00000000UL /**< Default value for AES_IF */
|
||||
#define _AES_IF_MASK 0x00000001UL /**< Mask for AES_IF */
|
||||
#define AES_IF_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Flag */
|
||||
#define _AES_IF_DONE_SHIFT 0 /**< Shift value for AES_DONE */
|
||||
#define _AES_IF_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */
|
||||
#define _AES_IF_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */
|
||||
#define AES_IF_DONE_DEFAULT (_AES_IF_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF */
|
||||
|
||||
/* Bit fields for AES IFS */
|
||||
#define _AES_IFS_RESETVALUE 0x00000000UL /**< Default value for AES_IFS */
|
||||
#define _AES_IFS_MASK 0x00000001UL /**< Mask for AES_IFS */
|
||||
#define AES_IFS_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Flag Set */
|
||||
#define _AES_IFS_DONE_SHIFT 0 /**< Shift value for AES_DONE */
|
||||
#define _AES_IFS_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */
|
||||
#define _AES_IFS_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IFS */
|
||||
#define AES_IFS_DONE_DEFAULT (_AES_IFS_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IFS */
|
||||
|
||||
/* Bit fields for AES IFC */
|
||||
#define _AES_IFC_RESETVALUE 0x00000000UL /**< Default value for AES_IFC */
|
||||
#define _AES_IFC_MASK 0x00000001UL /**< Mask for AES_IFC */
|
||||
#define AES_IFC_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Flag Clear */
|
||||
#define _AES_IFC_DONE_SHIFT 0 /**< Shift value for AES_DONE */
|
||||
#define _AES_IFC_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */
|
||||
#define _AES_IFC_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IFC */
|
||||
#define AES_IFC_DONE_DEFAULT (_AES_IFC_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IFC */
|
||||
|
||||
/* Bit fields for AES DATA */
|
||||
#define _AES_DATA_RESETVALUE 0x00000000UL /**< Default value for AES_DATA */
|
||||
#define _AES_DATA_MASK 0xFFFFFFFFUL /**< Mask for AES_DATA */
|
||||
#define _AES_DATA_DATA_SHIFT 0 /**< Shift value for AES_DATA */
|
||||
#define _AES_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_DATA */
|
||||
#define _AES_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_DATA */
|
||||
#define AES_DATA_DATA_DEFAULT (_AES_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_DATA */
|
||||
|
||||
/* Bit fields for AES XORDATA */
|
||||
#define _AES_XORDATA_RESETVALUE 0x00000000UL /**< Default value for AES_XORDATA */
|
||||
#define _AES_XORDATA_MASK 0xFFFFFFFFUL /**< Mask for AES_XORDATA */
|
||||
#define _AES_XORDATA_XORDATA_SHIFT 0 /**< Shift value for AES_XORDATA */
|
||||
#define _AES_XORDATA_XORDATA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_XORDATA */
|
||||
#define _AES_XORDATA_XORDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_XORDATA */
|
||||
#define AES_XORDATA_XORDATA_DEFAULT (_AES_XORDATA_XORDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_XORDATA */
|
||||
|
||||
/* Bit fields for AES KEYLA */
|
||||
#define _AES_KEYLA_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLA */
|
||||
#define _AES_KEYLA_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLA */
|
||||
#define _AES_KEYLA_KEYLA_SHIFT 0 /**< Shift value for AES_KEYLA */
|
||||
#define _AES_KEYLA_KEYLA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLA */
|
||||
#define _AES_KEYLA_KEYLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLA */
|
||||
#define AES_KEYLA_KEYLA_DEFAULT (_AES_KEYLA_KEYLA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLA */
|
||||
|
||||
/* Bit fields for AES KEYLB */
|
||||
#define _AES_KEYLB_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLB */
|
||||
#define _AES_KEYLB_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLB */
|
||||
#define _AES_KEYLB_KEYLB_SHIFT 0 /**< Shift value for AES_KEYLB */
|
||||
#define _AES_KEYLB_KEYLB_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLB */
|
||||
#define _AES_KEYLB_KEYLB_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLB */
|
||||
#define AES_KEYLB_KEYLB_DEFAULT (_AES_KEYLB_KEYLB_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLB */
|
||||
|
||||
/* Bit fields for AES KEYLC */
|
||||
#define _AES_KEYLC_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLC */
|
||||
#define _AES_KEYLC_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLC */
|
||||
#define _AES_KEYLC_KEYLC_SHIFT 0 /**< Shift value for AES_KEYLC */
|
||||
#define _AES_KEYLC_KEYLC_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLC */
|
||||
#define _AES_KEYLC_KEYLC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLC */
|
||||
#define AES_KEYLC_KEYLC_DEFAULT (_AES_KEYLC_KEYLC_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLC */
|
||||
|
||||
/* Bit fields for AES KEYLD */
|
||||
#define _AES_KEYLD_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLD */
|
||||
#define _AES_KEYLD_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLD */
|
||||
#define _AES_KEYLD_KEYLD_SHIFT 0 /**< Shift value for AES_KEYLD */
|
||||
#define _AES_KEYLD_KEYLD_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLD */
|
||||
#define _AES_KEYLD_KEYLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLD */
|
||||
#define AES_KEYLD_KEYLD_DEFAULT (_AES_KEYLD_KEYLD_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLD */
|
||||
|
||||
/* Bit fields for AES KEYHA */
|
||||
#define _AES_KEYHA_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHA */
|
||||
#define _AES_KEYHA_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHA */
|
||||
#define _AES_KEYHA_KEYHA_SHIFT 0 /**< Shift value for AES_KEYHA */
|
||||
#define _AES_KEYHA_KEYHA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHA */
|
||||
#define _AES_KEYHA_KEYHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHA */
|
||||
#define AES_KEYHA_KEYHA_DEFAULT (_AES_KEYHA_KEYHA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHA */
|
||||
|
||||
/* Bit fields for AES KEYHB */
|
||||
#define _AES_KEYHB_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHB */
|
||||
#define _AES_KEYHB_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHB */
|
||||
#define _AES_KEYHB_KEYHB_SHIFT 0 /**< Shift value for AES_KEYHB */
|
||||
#define _AES_KEYHB_KEYHB_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHB */
|
||||
#define _AES_KEYHB_KEYHB_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHB */
|
||||
#define AES_KEYHB_KEYHB_DEFAULT (_AES_KEYHB_KEYHB_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHB */
|
||||
|
||||
/* Bit fields for AES KEYHC */
|
||||
#define _AES_KEYHC_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHC */
|
||||
#define _AES_KEYHC_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHC */
|
||||
#define _AES_KEYHC_KEYHC_SHIFT 0 /**< Shift value for AES_KEYHC */
|
||||
#define _AES_KEYHC_KEYHC_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHC */
|
||||
#define _AES_KEYHC_KEYHC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHC */
|
||||
#define AES_KEYHC_KEYHC_DEFAULT (_AES_KEYHC_KEYHC_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHC */
|
||||
|
||||
/* Bit fields for AES KEYHD */
|
||||
#define _AES_KEYHD_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHD */
|
||||
#define _AES_KEYHD_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHD */
|
||||
#define _AES_KEYHD_KEYHD_SHIFT 0 /**< Shift value for AES_KEYHD */
|
||||
#define _AES_KEYHD_KEYHD_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHD */
|
||||
#define _AES_KEYHD_KEYHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHD */
|
||||
#define AES_KEYHD_KEYHD_DEFAULT (_AES_KEYHD_KEYHD_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHD */
|
||||
|
||||
/** @} End of group EFM32G_AES */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,121 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief efm32g_af_pins Register and Bit Field definitions
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_AF_Pins
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/** AF pin number for location number i */
|
||||
#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : -1)
|
||||
#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : -1)
|
||||
#define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : -1)
|
||||
#define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : -1)
|
||||
#define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : -1)
|
||||
#define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : -1)
|
||||
#define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : -1)
|
||||
#define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : -1)
|
||||
#define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : -1)
|
||||
#define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : -1)
|
||||
#define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : -1)
|
||||
#define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : -1)
|
||||
#define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : -1)
|
||||
#define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : -1)
|
||||
#define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : -1)
|
||||
#define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : -1)
|
||||
#define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : -1)
|
||||
#define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : -1)
|
||||
#define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : -1)
|
||||
#define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : -1)
|
||||
#define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : -1)
|
||||
#define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : -1)
|
||||
#define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : -1)
|
||||
#define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : -1)
|
||||
#define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : -1)
|
||||
#define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : -1)
|
||||
#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 1 : -1)
|
||||
#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1)
|
||||
#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1)
|
||||
#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 13 : -1)
|
||||
#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 14 : -1)
|
||||
#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 15 : -1)
|
||||
#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : -1)
|
||||
#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : -1)
|
||||
#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1)
|
||||
#define AF_TIMER1_CDTI0_PIN(i) (-1)
|
||||
#define AF_TIMER1_CDTI1_PIN(i) (-1)
|
||||
#define AF_TIMER1_CDTI2_PIN(i) (-1)
|
||||
#define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : -1)
|
||||
#define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : -1)
|
||||
#define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : -1)
|
||||
#define AF_TIMER2_CDTI0_PIN(i) (-1)
|
||||
#define AF_TIMER2_CDTI1_PIN(i) (-1)
|
||||
#define AF_TIMER2_CDTI2_PIN(i) (-1)
|
||||
#define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : -1)
|
||||
#define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : -1)
|
||||
#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : -1)
|
||||
#define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : -1)
|
||||
#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : -1)
|
||||
#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : -1)
|
||||
#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : -1)
|
||||
#define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : -1)
|
||||
#define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : -1)
|
||||
#define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : -1)
|
||||
#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : -1)
|
||||
#define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : -1)
|
||||
#define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : -1)
|
||||
#define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : -1)
|
||||
#define AF_UART0_CLK_PIN(i) (-1)
|
||||
#define AF_UART0_CS_PIN(i) (-1)
|
||||
#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : -1)
|
||||
#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : -1)
|
||||
#define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : -1)
|
||||
#define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : -1)
|
||||
#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : -1)
|
||||
#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : -1)
|
||||
#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1)
|
||||
#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1)
|
||||
#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : -1)
|
||||
#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : -1)
|
||||
#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : -1)
|
||||
#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : -1)
|
||||
#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : -1)
|
||||
#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : -1)
|
||||
#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : -1)
|
||||
#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : -1)
|
||||
#define AF_DBG_SWO_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : -1)
|
||||
#define AF_DBG_SWDIO_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : -1)
|
||||
#define AF_DBG_SWCLK_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : -1)
|
||||
|
||||
/** @} End of group EFM32G_AF_Pins */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,121 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief efm32g_af_ports Register and Bit Field definitions
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_AF_Ports
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/** AF port number for location number i */
|
||||
#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : -1)
|
||||
#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : -1)
|
||||
#define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : -1)
|
||||
#define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : -1)
|
||||
#define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : -1)
|
||||
#define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : -1)
|
||||
#define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : -1)
|
||||
#define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : -1)
|
||||
#define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : -1)
|
||||
#define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : -1)
|
||||
#define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : -1)
|
||||
#define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : -1)
|
||||
#define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : -1)
|
||||
#define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : -1)
|
||||
#define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : -1)
|
||||
#define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : -1)
|
||||
#define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : -1)
|
||||
#define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : -1)
|
||||
#define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : -1)
|
||||
#define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : -1)
|
||||
#define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : -1)
|
||||
#define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : -1)
|
||||
#define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : -1)
|
||||
#define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : -1)
|
||||
#define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : -1)
|
||||
#define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : -1)
|
||||
#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 3 : -1)
|
||||
#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 3 : -1)
|
||||
#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 3 : -1)
|
||||
#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : -1)
|
||||
#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : -1)
|
||||
#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : -1)
|
||||
#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : -1)
|
||||
#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : -1)
|
||||
#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : -1)
|
||||
#define AF_TIMER1_CDTI0_PORT(i) (-1)
|
||||
#define AF_TIMER1_CDTI1_PORT(i) (-1)
|
||||
#define AF_TIMER1_CDTI2_PORT(i) (-1)
|
||||
#define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : -1)
|
||||
#define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : -1)
|
||||
#define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : -1)
|
||||
#define AF_TIMER2_CDTI0_PORT(i) (-1)
|
||||
#define AF_TIMER2_CDTI1_PORT(i) (-1)
|
||||
#define AF_TIMER2_CDTI2_PORT(i) (-1)
|
||||
#define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : -1)
|
||||
#define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : -1)
|
||||
#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : -1)
|
||||
#define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : -1)
|
||||
#define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : -1)
|
||||
#define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : -1)
|
||||
#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : -1)
|
||||
#define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : -1)
|
||||
#define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : -1)
|
||||
#define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : -1)
|
||||
#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : -1)
|
||||
#define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : -1)
|
||||
#define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : -1)
|
||||
#define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : -1)
|
||||
#define AF_UART0_CLK_PORT(i) (-1)
|
||||
#define AF_UART0_CS_PORT(i) (-1)
|
||||
#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1)
|
||||
#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1)
|
||||
#define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : -1)
|
||||
#define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : -1)
|
||||
#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : -1)
|
||||
#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : -1)
|
||||
#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : -1)
|
||||
#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : -1)
|
||||
#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : -1)
|
||||
#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : -1)
|
||||
#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : -1)
|
||||
#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : -1)
|
||||
#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1)
|
||||
#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1)
|
||||
#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : -1)
|
||||
#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : -1)
|
||||
#define AF_DBG_SWO_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : -1)
|
||||
#define AF_DBG_SWDIO_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : -1)
|
||||
#define AF_DBG_SWCLK_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : -1)
|
||||
|
||||
/** @} End of group EFM32G_AF_Ports */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief efm32g_calibrate Register and Bit Field definitions
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_CALIBRATE
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define CALIBRATE_MAX_REGISTERS 50 /**< Max number of address/value pairs for calibration */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__I uint32_t ADDRESS; /**< Address of calibration register */
|
||||
__I uint32_t VALUE; /**< Default value for calibration register */
|
||||
} CALIBRATE_TypeDef; /** @} */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,381 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief efm32g_dac Register and Bit Field definitions
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_DAC
|
||||
* @{
|
||||
* @brief EFM32G_DAC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__I uint32_t STATUS; /**< Status Register */
|
||||
__IO uint32_t CH0CTRL; /**< Channel 0 Control Register */
|
||||
__IO uint32_t CH1CTRL; /**< Channel 1 Control Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IO uint32_t CH0DATA; /**< Channel 0 Data Register */
|
||||
__IO uint32_t CH1DATA; /**< Channel 1 Data Register */
|
||||
__IO uint32_t COMBDATA; /**< Combined Data Register */
|
||||
__IO uint32_t CAL; /**< Calibration Register */
|
||||
__IO uint32_t BIASPROG; /**< Bias Programming Register */
|
||||
} DAC_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_DAC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/* Bit fields for DAC CTRL */
|
||||
#define _DAC_CTRL_RESETVALUE 0x00000010UL /**< Default value for DAC_CTRL */
|
||||
#define _DAC_CTRL_MASK 0x003703FFUL /**< Mask for DAC_CTRL */
|
||||
#define DAC_CTRL_DIFF (0x1UL << 0) /**< Differential Mode */
|
||||
#define _DAC_CTRL_DIFF_SHIFT 0 /**< Shift value for DAC_DIFF */
|
||||
#define _DAC_CTRL_DIFF_MASK 0x1UL /**< Bit mask for DAC_DIFF */
|
||||
#define _DAC_CTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
|
||||
#define DAC_CTRL_DIFF_DEFAULT (_DAC_CTRL_DIFF_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_CTRL */
|
||||
#define DAC_CTRL_SINEMODE (0x1UL << 1) /**< Sine Mode */
|
||||
#define _DAC_CTRL_SINEMODE_SHIFT 1 /**< Shift value for DAC_SINEMODE */
|
||||
#define _DAC_CTRL_SINEMODE_MASK 0x2UL /**< Bit mask for DAC_SINEMODE */
|
||||
#define _DAC_CTRL_SINEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
|
||||
#define DAC_CTRL_SINEMODE_DEFAULT (_DAC_CTRL_SINEMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_CTRL */
|
||||
#define _DAC_CTRL_CONVMODE_SHIFT 2 /**< Shift value for DAC_CONVMODE */
|
||||
#define _DAC_CTRL_CONVMODE_MASK 0xCUL /**< Bit mask for DAC_CONVMODE */
|
||||
#define _DAC_CTRL_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
|
||||
#define _DAC_CTRL_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for DAC_CTRL */
|
||||
#define _DAC_CTRL_CONVMODE_SAMPLEHOLD 0x00000001UL /**< Mode SAMPLEHOLD for DAC_CTRL */
|
||||
#define _DAC_CTRL_CONVMODE_SAMPLEOFF 0x00000002UL /**< Mode SAMPLEOFF for DAC_CTRL */
|
||||
#define DAC_CTRL_CONVMODE_DEFAULT (_DAC_CTRL_CONVMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for DAC_CTRL */
|
||||
#define DAC_CTRL_CONVMODE_CONTINUOUS (_DAC_CTRL_CONVMODE_CONTINUOUS << 2) /**< Shifted mode CONTINUOUS for DAC_CTRL */
|
||||
#define DAC_CTRL_CONVMODE_SAMPLEHOLD (_DAC_CTRL_CONVMODE_SAMPLEHOLD << 2) /**< Shifted mode SAMPLEHOLD for DAC_CTRL */
|
||||
#define DAC_CTRL_CONVMODE_SAMPLEOFF (_DAC_CTRL_CONVMODE_SAMPLEOFF << 2) /**< Shifted mode SAMPLEOFF for DAC_CTRL */
|
||||
#define _DAC_CTRL_OUTMODE_SHIFT 4 /**< Shift value for DAC_OUTMODE */
|
||||
#define _DAC_CTRL_OUTMODE_MASK 0x30UL /**< Bit mask for DAC_OUTMODE */
|
||||
#define _DAC_CTRL_OUTMODE_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_CTRL */
|
||||
#define _DAC_CTRL_OUTMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for DAC_CTRL */
|
||||
#define _DAC_CTRL_OUTMODE_PIN 0x00000001UL /**< Mode PIN for DAC_CTRL */
|
||||
#define _DAC_CTRL_OUTMODE_ADC 0x00000002UL /**< Mode ADC for DAC_CTRL */
|
||||
#define _DAC_CTRL_OUTMODE_PINADC 0x00000003UL /**< Mode PINADC for DAC_CTRL */
|
||||
#define DAC_CTRL_OUTMODE_DISABLE (_DAC_CTRL_OUTMODE_DISABLE << 4) /**< Shifted mode DISABLE for DAC_CTRL */
|
||||
#define DAC_CTRL_OUTMODE_DEFAULT (_DAC_CTRL_OUTMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_CTRL */
|
||||
#define DAC_CTRL_OUTMODE_PIN (_DAC_CTRL_OUTMODE_PIN << 4) /**< Shifted mode PIN for DAC_CTRL */
|
||||
#define DAC_CTRL_OUTMODE_ADC (_DAC_CTRL_OUTMODE_ADC << 4) /**< Shifted mode ADC for DAC_CTRL */
|
||||
#define DAC_CTRL_OUTMODE_PINADC (_DAC_CTRL_OUTMODE_PINADC << 4) /**< Shifted mode PINADC for DAC_CTRL */
|
||||
#define DAC_CTRL_OUTENPRS (0x1UL << 6) /**< PRS Controlled Output Enable */
|
||||
#define _DAC_CTRL_OUTENPRS_SHIFT 6 /**< Shift value for DAC_OUTENPRS */
|
||||
#define _DAC_CTRL_OUTENPRS_MASK 0x40UL /**< Bit mask for DAC_OUTENPRS */
|
||||
#define _DAC_CTRL_OUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
|
||||
#define DAC_CTRL_OUTENPRS_DEFAULT (_DAC_CTRL_OUTENPRS_DEFAULT << 6) /**< Shifted mode DEFAULT for DAC_CTRL */
|
||||
#define DAC_CTRL_CH0PRESCRST (0x1UL << 7) /**< Channel 0 Start Reset Prescaler */
|
||||
#define _DAC_CTRL_CH0PRESCRST_SHIFT 7 /**< Shift value for DAC_CH0PRESCRST */
|
||||
#define _DAC_CTRL_CH0PRESCRST_MASK 0x80UL /**< Bit mask for DAC_CH0PRESCRST */
|
||||
#define _DAC_CTRL_CH0PRESCRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
|
||||
#define DAC_CTRL_CH0PRESCRST_DEFAULT (_DAC_CTRL_CH0PRESCRST_DEFAULT << 7) /**< Shifted mode DEFAULT for DAC_CTRL */
|
||||
#define _DAC_CTRL_REFSEL_SHIFT 8 /**< Shift value for DAC_REFSEL */
|
||||
#define _DAC_CTRL_REFSEL_MASK 0x300UL /**< Bit mask for DAC_REFSEL */
|
||||
#define _DAC_CTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
|
||||
#define _DAC_CTRL_REFSEL_1V25 0x00000000UL /**< Mode 1V25 for DAC_CTRL */
|
||||
#define _DAC_CTRL_REFSEL_2V5 0x00000001UL /**< Mode 2V5 for DAC_CTRL */
|
||||
#define _DAC_CTRL_REFSEL_VDD 0x00000002UL /**< Mode VDD for DAC_CTRL */
|
||||
#define DAC_CTRL_REFSEL_DEFAULT (_DAC_CTRL_REFSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_CTRL */
|
||||
#define DAC_CTRL_REFSEL_1V25 (_DAC_CTRL_REFSEL_1V25 << 8) /**< Shifted mode 1V25 for DAC_CTRL */
|
||||
#define DAC_CTRL_REFSEL_2V5 (_DAC_CTRL_REFSEL_2V5 << 8) /**< Shifted mode 2V5 for DAC_CTRL */
|
||||
#define DAC_CTRL_REFSEL_VDD (_DAC_CTRL_REFSEL_VDD << 8) /**< Shifted mode VDD for DAC_CTRL */
|
||||
#define _DAC_CTRL_PRESC_SHIFT 16 /**< Shift value for DAC_PRESC */
|
||||
#define _DAC_CTRL_PRESC_MASK 0x70000UL /**< Bit mask for DAC_PRESC */
|
||||
#define _DAC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
|
||||
#define _DAC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for DAC_CTRL */
|
||||
#define DAC_CTRL_PRESC_DEFAULT (_DAC_CTRL_PRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for DAC_CTRL */
|
||||
#define DAC_CTRL_PRESC_NODIVISION (_DAC_CTRL_PRESC_NODIVISION << 16) /**< Shifted mode NODIVISION for DAC_CTRL */
|
||||
#define _DAC_CTRL_REFRSEL_SHIFT 20 /**< Shift value for DAC_REFRSEL */
|
||||
#define _DAC_CTRL_REFRSEL_MASK 0x300000UL /**< Bit mask for DAC_REFRSEL */
|
||||
#define _DAC_CTRL_REFRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
|
||||
#define _DAC_CTRL_REFRSEL_8CYCLES 0x00000000UL /**< Mode 8CYCLES for DAC_CTRL */
|
||||
#define _DAC_CTRL_REFRSEL_16CYCLES 0x00000001UL /**< Mode 16CYCLES for DAC_CTRL */
|
||||
#define _DAC_CTRL_REFRSEL_32CYCLES 0x00000002UL /**< Mode 32CYCLES for DAC_CTRL */
|
||||
#define _DAC_CTRL_REFRSEL_64CYCLES 0x00000003UL /**< Mode 64CYCLES for DAC_CTRL */
|
||||
#define DAC_CTRL_REFRSEL_DEFAULT (_DAC_CTRL_REFRSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for DAC_CTRL */
|
||||
#define DAC_CTRL_REFRSEL_8CYCLES (_DAC_CTRL_REFRSEL_8CYCLES << 20) /**< Shifted mode 8CYCLES for DAC_CTRL */
|
||||
#define DAC_CTRL_REFRSEL_16CYCLES (_DAC_CTRL_REFRSEL_16CYCLES << 20) /**< Shifted mode 16CYCLES for DAC_CTRL */
|
||||
#define DAC_CTRL_REFRSEL_32CYCLES (_DAC_CTRL_REFRSEL_32CYCLES << 20) /**< Shifted mode 32CYCLES for DAC_CTRL */
|
||||
#define DAC_CTRL_REFRSEL_64CYCLES (_DAC_CTRL_REFRSEL_64CYCLES << 20) /**< Shifted mode 64CYCLES for DAC_CTRL */
|
||||
|
||||
/* Bit fields for DAC STATUS */
|
||||
#define _DAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for DAC_STATUS */
|
||||
#define _DAC_STATUS_MASK 0x00000003UL /**< Mask for DAC_STATUS */
|
||||
#define DAC_STATUS_CH0DV (0x1UL << 0) /**< Channel 0 Data Valid */
|
||||
#define _DAC_STATUS_CH0DV_SHIFT 0 /**< Shift value for DAC_CH0DV */
|
||||
#define _DAC_STATUS_CH0DV_MASK 0x1UL /**< Bit mask for DAC_CH0DV */
|
||||
#define _DAC_STATUS_CH0DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_STATUS */
|
||||
#define DAC_STATUS_CH0DV_DEFAULT (_DAC_STATUS_CH0DV_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_STATUS */
|
||||
#define DAC_STATUS_CH1DV (0x1UL << 1) /**< Channel 1 Data Valid */
|
||||
#define _DAC_STATUS_CH1DV_SHIFT 1 /**< Shift value for DAC_CH1DV */
|
||||
#define _DAC_STATUS_CH1DV_MASK 0x2UL /**< Bit mask for DAC_CH1DV */
|
||||
#define _DAC_STATUS_CH1DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_STATUS */
|
||||
#define DAC_STATUS_CH1DV_DEFAULT (_DAC_STATUS_CH1DV_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_STATUS */
|
||||
|
||||
/* Bit fields for DAC CH0CTRL */
|
||||
#define _DAC_CH0CTRL_RESETVALUE 0x00000000UL /**< Default value for DAC_CH0CTRL */
|
||||
#define _DAC_CH0CTRL_MASK 0x00000077UL /**< Mask for DAC_CH0CTRL */
|
||||
#define DAC_CH0CTRL_EN (0x1UL << 0) /**< Channel 0 Enable */
|
||||
#define _DAC_CH0CTRL_EN_SHIFT 0 /**< Shift value for DAC_EN */
|
||||
#define _DAC_CH0CTRL_EN_MASK 0x1UL /**< Bit mask for DAC_EN */
|
||||
#define _DAC_CH0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0CTRL */
|
||||
#define DAC_CH0CTRL_EN_DEFAULT (_DAC_CH0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_CH0CTRL */
|
||||
#define DAC_CH0CTRL_REFREN (0x1UL << 1) /**< Channel 0 Automatic Refresh Enable */
|
||||
#define _DAC_CH0CTRL_REFREN_SHIFT 1 /**< Shift value for DAC_REFREN */
|
||||
#define _DAC_CH0CTRL_REFREN_MASK 0x2UL /**< Bit mask for DAC_REFREN */
|
||||
#define _DAC_CH0CTRL_REFREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0CTRL */
|
||||
#define DAC_CH0CTRL_REFREN_DEFAULT (_DAC_CH0CTRL_REFREN_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_CH0CTRL */
|
||||
#define DAC_CH0CTRL_PRSEN (0x1UL << 2) /**< Channel 0 PRS Trigger Enable */
|
||||
#define _DAC_CH0CTRL_PRSEN_SHIFT 2 /**< Shift value for DAC_PRSEN */
|
||||
#define _DAC_CH0CTRL_PRSEN_MASK 0x4UL /**< Bit mask for DAC_PRSEN */
|
||||
#define _DAC_CH0CTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0CTRL */
|
||||
#define DAC_CH0CTRL_PRSEN_DEFAULT (_DAC_CH0CTRL_PRSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for DAC_CH0CTRL */
|
||||
#define _DAC_CH0CTRL_PRSSEL_SHIFT 4 /**< Shift value for DAC_PRSSEL */
|
||||
#define _DAC_CH0CTRL_PRSSEL_MASK 0x70UL /**< Bit mask for DAC_PRSSEL */
|
||||
#define _DAC_CH0CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0CTRL */
|
||||
#define _DAC_CH0CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for DAC_CH0CTRL */
|
||||
#define _DAC_CH0CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for DAC_CH0CTRL */
|
||||
#define _DAC_CH0CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for DAC_CH0CTRL */
|
||||
#define _DAC_CH0CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for DAC_CH0CTRL */
|
||||
#define _DAC_CH0CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for DAC_CH0CTRL */
|
||||
#define _DAC_CH0CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for DAC_CH0CTRL */
|
||||
#define _DAC_CH0CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for DAC_CH0CTRL */
|
||||
#define _DAC_CH0CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for DAC_CH0CTRL */
|
||||
#define DAC_CH0CTRL_PRSSEL_DEFAULT (_DAC_CH0CTRL_PRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_CH0CTRL */
|
||||
#define DAC_CH0CTRL_PRSSEL_PRSCH0 (_DAC_CH0CTRL_PRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for DAC_CH0CTRL */
|
||||
#define DAC_CH0CTRL_PRSSEL_PRSCH1 (_DAC_CH0CTRL_PRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for DAC_CH0CTRL */
|
||||
#define DAC_CH0CTRL_PRSSEL_PRSCH2 (_DAC_CH0CTRL_PRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for DAC_CH0CTRL */
|
||||
#define DAC_CH0CTRL_PRSSEL_PRSCH3 (_DAC_CH0CTRL_PRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for DAC_CH0CTRL */
|
||||
#define DAC_CH0CTRL_PRSSEL_PRSCH4 (_DAC_CH0CTRL_PRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for DAC_CH0CTRL */
|
||||
#define DAC_CH0CTRL_PRSSEL_PRSCH5 (_DAC_CH0CTRL_PRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for DAC_CH0CTRL */
|
||||
#define DAC_CH0CTRL_PRSSEL_PRSCH6 (_DAC_CH0CTRL_PRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for DAC_CH0CTRL */
|
||||
#define DAC_CH0CTRL_PRSSEL_PRSCH7 (_DAC_CH0CTRL_PRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for DAC_CH0CTRL */
|
||||
|
||||
/* Bit fields for DAC CH1CTRL */
|
||||
#define _DAC_CH1CTRL_RESETVALUE 0x00000000UL /**< Default value for DAC_CH1CTRL */
|
||||
#define _DAC_CH1CTRL_MASK 0x00000077UL /**< Mask for DAC_CH1CTRL */
|
||||
#define DAC_CH1CTRL_EN (0x1UL << 0) /**< Channel 1 Enable */
|
||||
#define _DAC_CH1CTRL_EN_SHIFT 0 /**< Shift value for DAC_EN */
|
||||
#define _DAC_CH1CTRL_EN_MASK 0x1UL /**< Bit mask for DAC_EN */
|
||||
#define _DAC_CH1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1CTRL */
|
||||
#define DAC_CH1CTRL_EN_DEFAULT (_DAC_CH1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_CH1CTRL */
|
||||
#define DAC_CH1CTRL_REFREN (0x1UL << 1) /**< Channel 1 Automatic Refresh Enable */
|
||||
#define _DAC_CH1CTRL_REFREN_SHIFT 1 /**< Shift value for DAC_REFREN */
|
||||
#define _DAC_CH1CTRL_REFREN_MASK 0x2UL /**< Bit mask for DAC_REFREN */
|
||||
#define _DAC_CH1CTRL_REFREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1CTRL */
|
||||
#define DAC_CH1CTRL_REFREN_DEFAULT (_DAC_CH1CTRL_REFREN_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_CH1CTRL */
|
||||
#define DAC_CH1CTRL_PRSEN (0x1UL << 2) /**< Channel 1 PRS Trigger Enable */
|
||||
#define _DAC_CH1CTRL_PRSEN_SHIFT 2 /**< Shift value for DAC_PRSEN */
|
||||
#define _DAC_CH1CTRL_PRSEN_MASK 0x4UL /**< Bit mask for DAC_PRSEN */
|
||||
#define _DAC_CH1CTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1CTRL */
|
||||
#define DAC_CH1CTRL_PRSEN_DEFAULT (_DAC_CH1CTRL_PRSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for DAC_CH1CTRL */
|
||||
#define _DAC_CH1CTRL_PRSSEL_SHIFT 4 /**< Shift value for DAC_PRSSEL */
|
||||
#define _DAC_CH1CTRL_PRSSEL_MASK 0x70UL /**< Bit mask for DAC_PRSSEL */
|
||||
#define _DAC_CH1CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1CTRL */
|
||||
#define _DAC_CH1CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for DAC_CH1CTRL */
|
||||
#define _DAC_CH1CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for DAC_CH1CTRL */
|
||||
#define _DAC_CH1CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for DAC_CH1CTRL */
|
||||
#define _DAC_CH1CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for DAC_CH1CTRL */
|
||||
#define _DAC_CH1CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for DAC_CH1CTRL */
|
||||
#define _DAC_CH1CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for DAC_CH1CTRL */
|
||||
#define _DAC_CH1CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for DAC_CH1CTRL */
|
||||
#define _DAC_CH1CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for DAC_CH1CTRL */
|
||||
#define DAC_CH1CTRL_PRSSEL_DEFAULT (_DAC_CH1CTRL_PRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_CH1CTRL */
|
||||
#define DAC_CH1CTRL_PRSSEL_PRSCH0 (_DAC_CH1CTRL_PRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for DAC_CH1CTRL */
|
||||
#define DAC_CH1CTRL_PRSSEL_PRSCH1 (_DAC_CH1CTRL_PRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for DAC_CH1CTRL */
|
||||
#define DAC_CH1CTRL_PRSSEL_PRSCH2 (_DAC_CH1CTRL_PRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for DAC_CH1CTRL */
|
||||
#define DAC_CH1CTRL_PRSSEL_PRSCH3 (_DAC_CH1CTRL_PRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for DAC_CH1CTRL */
|
||||
#define DAC_CH1CTRL_PRSSEL_PRSCH4 (_DAC_CH1CTRL_PRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for DAC_CH1CTRL */
|
||||
#define DAC_CH1CTRL_PRSSEL_PRSCH5 (_DAC_CH1CTRL_PRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for DAC_CH1CTRL */
|
||||
#define DAC_CH1CTRL_PRSSEL_PRSCH6 (_DAC_CH1CTRL_PRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for DAC_CH1CTRL */
|
||||
#define DAC_CH1CTRL_PRSSEL_PRSCH7 (_DAC_CH1CTRL_PRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for DAC_CH1CTRL */
|
||||
|
||||
/* Bit fields for DAC IEN */
|
||||
#define _DAC_IEN_RESETVALUE 0x00000000UL /**< Default value for DAC_IEN */
|
||||
#define _DAC_IEN_MASK 0x00000033UL /**< Mask for DAC_IEN */
|
||||
#define DAC_IEN_CH0 (0x1UL << 0) /**< Channel 0 Conversion Complete Interrupt Enable */
|
||||
#define _DAC_IEN_CH0_SHIFT 0 /**< Shift value for DAC_CH0 */
|
||||
#define _DAC_IEN_CH0_MASK 0x1UL /**< Bit mask for DAC_CH0 */
|
||||
#define _DAC_IEN_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IEN */
|
||||
#define DAC_IEN_CH0_DEFAULT (_DAC_IEN_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_IEN */
|
||||
#define DAC_IEN_CH1 (0x1UL << 1) /**< Channel 1 Conversion Complete Interrupt Enable */
|
||||
#define _DAC_IEN_CH1_SHIFT 1 /**< Shift value for DAC_CH1 */
|
||||
#define _DAC_IEN_CH1_MASK 0x2UL /**< Bit mask for DAC_CH1 */
|
||||
#define _DAC_IEN_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IEN */
|
||||
#define DAC_IEN_CH1_DEFAULT (_DAC_IEN_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_IEN */
|
||||
#define DAC_IEN_CH0UF (0x1UL << 4) /**< Channel 0 Conversion Data Underflow Interrupt Enable */
|
||||
#define _DAC_IEN_CH0UF_SHIFT 4 /**< Shift value for DAC_CH0UF */
|
||||
#define _DAC_IEN_CH0UF_MASK 0x10UL /**< Bit mask for DAC_CH0UF */
|
||||
#define _DAC_IEN_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IEN */
|
||||
#define DAC_IEN_CH0UF_DEFAULT (_DAC_IEN_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_IEN */
|
||||
#define DAC_IEN_CH1UF (0x1UL << 5) /**< Channel 1 Conversion Data Underflow Interrupt Enable */
|
||||
#define _DAC_IEN_CH1UF_SHIFT 5 /**< Shift value for DAC_CH1UF */
|
||||
#define _DAC_IEN_CH1UF_MASK 0x20UL /**< Bit mask for DAC_CH1UF */
|
||||
#define _DAC_IEN_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IEN */
|
||||
#define DAC_IEN_CH1UF_DEFAULT (_DAC_IEN_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for DAC_IEN */
|
||||
|
||||
/* Bit fields for DAC IF */
|
||||
#define _DAC_IF_RESETVALUE 0x00000000UL /**< Default value for DAC_IF */
|
||||
#define _DAC_IF_MASK 0x00000033UL /**< Mask for DAC_IF */
|
||||
#define DAC_IF_CH0 (0x1UL << 0) /**< Channel 0 Conversion Complete Interrupt Flag */
|
||||
#define _DAC_IF_CH0_SHIFT 0 /**< Shift value for DAC_CH0 */
|
||||
#define _DAC_IF_CH0_MASK 0x1UL /**< Bit mask for DAC_CH0 */
|
||||
#define _DAC_IF_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IF */
|
||||
#define DAC_IF_CH0_DEFAULT (_DAC_IF_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_IF */
|
||||
#define DAC_IF_CH1 (0x1UL << 1) /**< Channel 1 Conversion Complete Interrupt Flag */
|
||||
#define _DAC_IF_CH1_SHIFT 1 /**< Shift value for DAC_CH1 */
|
||||
#define _DAC_IF_CH1_MASK 0x2UL /**< Bit mask for DAC_CH1 */
|
||||
#define _DAC_IF_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IF */
|
||||
#define DAC_IF_CH1_DEFAULT (_DAC_IF_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_IF */
|
||||
#define DAC_IF_CH0UF (0x1UL << 4) /**< Channel 0 Data Underflow Interrupt Flag */
|
||||
#define _DAC_IF_CH0UF_SHIFT 4 /**< Shift value for DAC_CH0UF */
|
||||
#define _DAC_IF_CH0UF_MASK 0x10UL /**< Bit mask for DAC_CH0UF */
|
||||
#define _DAC_IF_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IF */
|
||||
#define DAC_IF_CH0UF_DEFAULT (_DAC_IF_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_IF */
|
||||
#define DAC_IF_CH1UF (0x1UL << 5) /**< Channel 1 Data Underflow Interrupt Flag */
|
||||
#define _DAC_IF_CH1UF_SHIFT 5 /**< Shift value for DAC_CH1UF */
|
||||
#define _DAC_IF_CH1UF_MASK 0x20UL /**< Bit mask for DAC_CH1UF */
|
||||
#define _DAC_IF_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IF */
|
||||
#define DAC_IF_CH1UF_DEFAULT (_DAC_IF_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for DAC_IF */
|
||||
|
||||
/* Bit fields for DAC IFS */
|
||||
#define _DAC_IFS_RESETVALUE 0x00000000UL /**< Default value for DAC_IFS */
|
||||
#define _DAC_IFS_MASK 0x00000033UL /**< Mask for DAC_IFS */
|
||||
#define DAC_IFS_CH0 (0x1UL << 0) /**< Channel 0 Conversion Complete Interrupt Flag Set */
|
||||
#define _DAC_IFS_CH0_SHIFT 0 /**< Shift value for DAC_CH0 */
|
||||
#define _DAC_IFS_CH0_MASK 0x1UL /**< Bit mask for DAC_CH0 */
|
||||
#define _DAC_IFS_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFS */
|
||||
#define DAC_IFS_CH0_DEFAULT (_DAC_IFS_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_IFS */
|
||||
#define DAC_IFS_CH1 (0x1UL << 1) /**< Channel 1 Conversion Complete Interrupt Flag Set */
|
||||
#define _DAC_IFS_CH1_SHIFT 1 /**< Shift value for DAC_CH1 */
|
||||
#define _DAC_IFS_CH1_MASK 0x2UL /**< Bit mask for DAC_CH1 */
|
||||
#define _DAC_IFS_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFS */
|
||||
#define DAC_IFS_CH1_DEFAULT (_DAC_IFS_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_IFS */
|
||||
#define DAC_IFS_CH0UF (0x1UL << 4) /**< Channel 0 Data Underflow Interrupt Flag Set */
|
||||
#define _DAC_IFS_CH0UF_SHIFT 4 /**< Shift value for DAC_CH0UF */
|
||||
#define _DAC_IFS_CH0UF_MASK 0x10UL /**< Bit mask for DAC_CH0UF */
|
||||
#define _DAC_IFS_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFS */
|
||||
#define DAC_IFS_CH0UF_DEFAULT (_DAC_IFS_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_IFS */
|
||||
#define DAC_IFS_CH1UF (0x1UL << 5) /**< Channel 1 Data Underflow Interrupt Flag Set */
|
||||
#define _DAC_IFS_CH1UF_SHIFT 5 /**< Shift value for DAC_CH1UF */
|
||||
#define _DAC_IFS_CH1UF_MASK 0x20UL /**< Bit mask for DAC_CH1UF */
|
||||
#define _DAC_IFS_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFS */
|
||||
#define DAC_IFS_CH1UF_DEFAULT (_DAC_IFS_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for DAC_IFS */
|
||||
|
||||
/* Bit fields for DAC IFC */
|
||||
#define _DAC_IFC_RESETVALUE 0x00000000UL /**< Default value for DAC_IFC */
|
||||
#define _DAC_IFC_MASK 0x00000033UL /**< Mask for DAC_IFC */
|
||||
#define DAC_IFC_CH0 (0x1UL << 0) /**< Channel 0 Conversion Complete Interrupt Flag Clear */
|
||||
#define _DAC_IFC_CH0_SHIFT 0 /**< Shift value for DAC_CH0 */
|
||||
#define _DAC_IFC_CH0_MASK 0x1UL /**< Bit mask for DAC_CH0 */
|
||||
#define _DAC_IFC_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFC */
|
||||
#define DAC_IFC_CH0_DEFAULT (_DAC_IFC_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_IFC */
|
||||
#define DAC_IFC_CH1 (0x1UL << 1) /**< Channel 1 Conversion Complete Interrupt Flag Clear */
|
||||
#define _DAC_IFC_CH1_SHIFT 1 /**< Shift value for DAC_CH1 */
|
||||
#define _DAC_IFC_CH1_MASK 0x2UL /**< Bit mask for DAC_CH1 */
|
||||
#define _DAC_IFC_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFC */
|
||||
#define DAC_IFC_CH1_DEFAULT (_DAC_IFC_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_IFC */
|
||||
#define DAC_IFC_CH0UF (0x1UL << 4) /**< Channel 0 Data Underflow Interrupt Flag Clear */
|
||||
#define _DAC_IFC_CH0UF_SHIFT 4 /**< Shift value for DAC_CH0UF */
|
||||
#define _DAC_IFC_CH0UF_MASK 0x10UL /**< Bit mask for DAC_CH0UF */
|
||||
#define _DAC_IFC_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFC */
|
||||
#define DAC_IFC_CH0UF_DEFAULT (_DAC_IFC_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_IFC */
|
||||
#define DAC_IFC_CH1UF (0x1UL << 5) /**< Channel 1 Data Underflow Interrupt Flag Clear */
|
||||
#define _DAC_IFC_CH1UF_SHIFT 5 /**< Shift value for DAC_CH1UF */
|
||||
#define _DAC_IFC_CH1UF_MASK 0x20UL /**< Bit mask for DAC_CH1UF */
|
||||
#define _DAC_IFC_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFC */
|
||||
#define DAC_IFC_CH1UF_DEFAULT (_DAC_IFC_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for DAC_IFC */
|
||||
|
||||
/* Bit fields for DAC CH0DATA */
|
||||
#define _DAC_CH0DATA_RESETVALUE 0x00000000UL /**< Default value for DAC_CH0DATA */
|
||||
#define _DAC_CH0DATA_MASK 0x00000FFFUL /**< Mask for DAC_CH0DATA */
|
||||
#define _DAC_CH0DATA_DATA_SHIFT 0 /**< Shift value for DAC_DATA */
|
||||
#define _DAC_CH0DATA_DATA_MASK 0xFFFUL /**< Bit mask for DAC_DATA */
|
||||
#define _DAC_CH0DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0DATA */
|
||||
#define DAC_CH0DATA_DATA_DEFAULT (_DAC_CH0DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_CH0DATA */
|
||||
|
||||
/* Bit fields for DAC CH1DATA */
|
||||
#define _DAC_CH1DATA_RESETVALUE 0x00000000UL /**< Default value for DAC_CH1DATA */
|
||||
#define _DAC_CH1DATA_MASK 0x00000FFFUL /**< Mask for DAC_CH1DATA */
|
||||
#define _DAC_CH1DATA_DATA_SHIFT 0 /**< Shift value for DAC_DATA */
|
||||
#define _DAC_CH1DATA_DATA_MASK 0xFFFUL /**< Bit mask for DAC_DATA */
|
||||
#define _DAC_CH1DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1DATA */
|
||||
#define DAC_CH1DATA_DATA_DEFAULT (_DAC_CH1DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_CH1DATA */
|
||||
|
||||
/* Bit fields for DAC COMBDATA */
|
||||
#define _DAC_COMBDATA_RESETVALUE 0x00000000UL /**< Default value for DAC_COMBDATA */
|
||||
#define _DAC_COMBDATA_MASK 0x0FFF0FFFUL /**< Mask for DAC_COMBDATA */
|
||||
#define _DAC_COMBDATA_CH0DATA_SHIFT 0 /**< Shift value for DAC_CH0DATA */
|
||||
#define _DAC_COMBDATA_CH0DATA_MASK 0xFFFUL /**< Bit mask for DAC_CH0DATA */
|
||||
#define _DAC_COMBDATA_CH0DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_COMBDATA */
|
||||
#define DAC_COMBDATA_CH0DATA_DEFAULT (_DAC_COMBDATA_CH0DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_COMBDATA */
|
||||
#define _DAC_COMBDATA_CH1DATA_SHIFT 16 /**< Shift value for DAC_CH1DATA */
|
||||
#define _DAC_COMBDATA_CH1DATA_MASK 0xFFF0000UL /**< Bit mask for DAC_CH1DATA */
|
||||
#define _DAC_COMBDATA_CH1DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_COMBDATA */
|
||||
#define DAC_COMBDATA_CH1DATA_DEFAULT (_DAC_COMBDATA_CH1DATA_DEFAULT << 16) /**< Shifted mode DEFAULT for DAC_COMBDATA */
|
||||
|
||||
/* Bit fields for DAC CAL */
|
||||
#define _DAC_CAL_RESETVALUE 0x00400000UL /**< Default value for DAC_CAL */
|
||||
#define _DAC_CAL_MASK 0x007F3F3FUL /**< Mask for DAC_CAL */
|
||||
#define _DAC_CAL_CH0OFFSET_SHIFT 0 /**< Shift value for DAC_CH0OFFSET */
|
||||
#define _DAC_CAL_CH0OFFSET_MASK 0x3FUL /**< Bit mask for DAC_CH0OFFSET */
|
||||
#define _DAC_CAL_CH0OFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CAL */
|
||||
#define DAC_CAL_CH0OFFSET_DEFAULT (_DAC_CAL_CH0OFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_CAL */
|
||||
#define _DAC_CAL_CH1OFFSET_SHIFT 8 /**< Shift value for DAC_CH1OFFSET */
|
||||
#define _DAC_CAL_CH1OFFSET_MASK 0x3F00UL /**< Bit mask for DAC_CH1OFFSET */
|
||||
#define _DAC_CAL_CH1OFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CAL */
|
||||
#define DAC_CAL_CH1OFFSET_DEFAULT (_DAC_CAL_CH1OFFSET_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_CAL */
|
||||
#define _DAC_CAL_GAIN_SHIFT 16 /**< Shift value for DAC_GAIN */
|
||||
#define _DAC_CAL_GAIN_MASK 0x7F0000UL /**< Bit mask for DAC_GAIN */
|
||||
#define _DAC_CAL_GAIN_DEFAULT 0x00000040UL /**< Mode DEFAULT for DAC_CAL */
|
||||
#define DAC_CAL_GAIN_DEFAULT (_DAC_CAL_GAIN_DEFAULT << 16) /**< Shifted mode DEFAULT for DAC_CAL */
|
||||
|
||||
/* Bit fields for DAC BIASPROG */
|
||||
#define _DAC_BIASPROG_RESETVALUE 0x00000047UL /**< Default value for DAC_BIASPROG */
|
||||
#define _DAC_BIASPROG_MASK 0x0000004FUL /**< Mask for DAC_BIASPROG */
|
||||
#define _DAC_BIASPROG_BIASPROG_SHIFT 0 /**< Shift value for DAC_BIASPROG */
|
||||
#define _DAC_BIASPROG_BIASPROG_MASK 0xFUL /**< Bit mask for DAC_BIASPROG */
|
||||
#define _DAC_BIASPROG_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for DAC_BIASPROG */
|
||||
#define DAC_BIASPROG_BIASPROG_DEFAULT (_DAC_BIASPROG_BIASPROG_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_BIASPROG */
|
||||
#define DAC_BIASPROG_HALFBIAS (0x1UL << 6) /**< Half Bias Current */
|
||||
#define _DAC_BIASPROG_HALFBIAS_SHIFT 6 /**< Shift value for DAC_HALFBIAS */
|
||||
#define _DAC_BIASPROG_HALFBIAS_MASK 0x40UL /**< Bit mask for DAC_HALFBIAS */
|
||||
#define _DAC_BIASPROG_HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DAC_BIASPROG */
|
||||
#define DAC_BIASPROG_HALFBIAS_DEFAULT (_DAC_BIASPROG_HALFBIAS_DEFAULT << 6) /**< Shifted mode DEFAULT for DAC_BIASPROG */
|
||||
|
||||
/** @} End of group EFM32G_DAC */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,139 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief efm32g_devinfo Register and Bit Field definitions
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_DEVINFO
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__I uint32_t CAL; /**< Calibration temperature and checksum */
|
||||
__I uint32_t ADC0CAL0; /**< ADC0 Calibration register 0 */
|
||||
__I uint32_t ADC0CAL1; /**< ADC0 Calibration register 1 */
|
||||
__I uint32_t ADC0CAL2; /**< ADC0 Calibration register 2 */
|
||||
uint32_t RESERVED0[2]; /**< Reserved */
|
||||
__I uint32_t DAC0CAL0; /**< DAC calibrartion register 0 */
|
||||
__I uint32_t DAC0CAL1; /**< DAC calibrartion register 1 */
|
||||
__I uint32_t DAC0CAL2; /**< DAC calibrartion register 2 */
|
||||
uint32_t RESERVED1[2]; /**< Reserved */
|
||||
__I uint32_t HFRCOCAL0; /**< HFRCO calibration register 0 */
|
||||
__I uint32_t HFRCOCAL1; /**< HFRCO calibration register 1 */
|
||||
uint32_t RESERVED2[3]; /**< Reserved */
|
||||
__I uint32_t UNIQUEL; /**< Low 32 bits of device unique number */
|
||||
__I uint32_t UNIQUEH; /**< High 32 bits of device unique number */
|
||||
__I uint32_t MSIZE; /**< Flash and SRAM Memory size in KiloBytes */
|
||||
__I uint32_t PART; /**< Part description */
|
||||
} DEVINFO_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_DEVINFO_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
/* Bit fields for EFM32G_DEVINFO */
|
||||
#define _DEVINFO_CAL_CRC_MASK 0x0000FFFFUL /**< Integrity CRC checksum mask */
|
||||
#define _DEVINFO_CAL_CRC_SHIFT 0 /**< Integrity CRC checksum shift */
|
||||
#define _DEVINFO_CAL_TEMP_MASK 0x00FF0000UL /**< Calibration temperature, DegC, mask */
|
||||
#define _DEVINFO_CAL_TEMP_SHIFT 16 /**< Calibration temperature shift */
|
||||
#define _DEVINFO_ADC0CAL0_1V25_GAIN_MASK 0x00007F00UL /**< Gain for 1V25 reference, mask */
|
||||
#define _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT 8 /**< Gain for 1V25 reference, shift */
|
||||
#define _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK 0x0000007FUL /**< Offset for 1V25 reference, mask */
|
||||
#define _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT 0 /**< Offset for 1V25 reference, shift */
|
||||
#define _DEVINFO_ADC0CAL0_2V5_GAIN_MASK 0x7F000000UL /**< Gain for 2V5 reference, mask */
|
||||
#define _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT 24 /**< Gain for 2V5 reference, shift */
|
||||
#define _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK 0x007F0000UL /**< Offset for 2V5 reference, mask */
|
||||
#define _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT 16 /**< Offset for 2V5 reference, shift */
|
||||
#define _DEVINFO_ADC0CAL1_VDD_GAIN_MASK 0x00007F00UL /**< Gain for VDD reference, mask */
|
||||
#define _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT 8 /**< Gain for VDD reference, shift */
|
||||
#define _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK 0x0000007FUL /**< Offset for VDD reference, mask */
|
||||
#define _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT 0 /**< Offset for VDD reference, shift */
|
||||
#define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK 0x7F000000UL /**< Gain 5VDIFF for 5VDIFF reference, mask */
|
||||
#define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT 24 /**< Gain for 5VDIFF reference, mask */
|
||||
#define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK 0x007F0000UL /**< Offset for 5VDIFF reference, mask */
|
||||
#define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT 16 /**< Offset for 5VDIFF reference, shift */
|
||||
#define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK 0x0000007FUL /**< Offset for 2XVDDVSS reference, mask */
|
||||
#define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT 0 /**< Offset for 2XVDDVSS reference, shift */
|
||||
#define _DEVINFO_ADC0CAL2_TEMP1V25_MASK 0xFFF00000UL /**< Temperature reading at 1V25 reference, mask */
|
||||
#define _DEVINFO_ADC0CAL2_TEMP1V25_SHIFT 20 /**< Temperature reading at 1V25 reference, DegC */
|
||||
#define _DEVINFO_DAC0CAL0_1V25_GAIN_MASK 0x007F0000UL /**< Gain for 1V25 reference, mask */
|
||||
#define _DEVINFO_DAC0CAL0_1V25_GAIN_SHIFT 16 /**< Gain for 1V25 reference, shift */
|
||||
#define _DEVINFO_DAC0CAL0_1V25_CH1_OFFSET_MASK 0x00003F00UL /**< Channel 1 offset for 1V25 reference, mask */
|
||||
#define _DEVINFO_DAC0CAL0_1V25_CH1_OFFSET_SHIFT 8 /**< Channel 1 offset for 1V25 reference, shift */
|
||||
#define _DEVINFO_DAC0CAL0_1V25_CH0_OFFSET_MASK 0x0000003FUL /**< Channel 0 offset for 1V25 reference, mask */
|
||||
#define _DEVINFO_DAC0CAL0_1V25_CH0_OFFSET_SHIFT 0 /**< Channel 0 offset for 1V25 reference, shift */
|
||||
#define _DEVINFO_DAC0CAL1_2V5_GAIN_MASK 0x007F0000UL /**< Gain for 2V5 reference, mask */
|
||||
#define _DEVINFO_DAC0CAL1_2V5_GAIN_SHIFT 16 /**< Gain for 2V5 reference, shift */
|
||||
#define _DEVINFO_DAC0CAL1_2V5_CH1_OFFSET_MASK 0x00003F00UL /**< Channel 1 offset for 2V5 reference, mask */
|
||||
#define _DEVINFO_DAC0CAL1_2V5_CH1_OFFSET_SHIFT 8 /**< Channel 1 offset for 2V5 reference, shift */
|
||||
#define _DEVINFO_DAC0CAL1_2V5_CH0_OFFSET_MASK 0x0000003FUL /**< Channel 0 offset for 2V5 reference, mask */
|
||||
#define _DEVINFO_DAC0CAL1_2V5_CH0_OFFSET_SHIFT 0 /**< Channel 0 offset for 2V5 reference, shift */
|
||||
#define _DEVINFO_DAC0CAL2_VDD_GAIN_MASK 0x007F0000UL /**< Gain for VDD reference, mask */
|
||||
#define _DEVINFO_DAC0CAL2_VDD_GAIN_SHIFT 16 /**< Gain for VDD reference, shift */
|
||||
#define _DEVINFO_DAC0CAL2_VDD_CH1_OFFSET_MASK 0x00003F00UL /**< Channel 1 offset for VDD reference, mask */
|
||||
#define _DEVINFO_DAC0CAL2_VDD_CH1_OFFSET_SHIFT 8 /**< Channel 1 offset for VDD reference, shift */
|
||||
#define _DEVINFO_DAC0CAL2_VDD_CH0_OFFSET_MASK 0x0000003FUL /**< Channel 0 offset for VDD reference, mask */
|
||||
#define _DEVINFO_DAC0CAL2_VDD_CH0_OFFSET_SHIFT 0 /**< Channel 0 offset for VDD reference, shift*/
|
||||
#define _DEVINFO_HFRCOCAL0_BAND1_MASK 0x000000FFUL /**< 1MHz tuning value for HFRCO, mask */
|
||||
#define _DEVINFO_HFRCOCAL0_BAND1_SHIFT 0 /**< 1MHz tuning value for HFRCO, shift */
|
||||
#define _DEVINFO_HFRCOCAL0_BAND7_MASK 0x0000FF00UL /**< 7MHz tuning value for HFRCO, mask */
|
||||
#define _DEVINFO_HFRCOCAL0_BAND7_SHIFT 8 /**< 7MHz tuning value for HFRCO, shift */
|
||||
#define _DEVINFO_HFRCOCAL0_BAND11_MASK 0x00FF0000UL /**< 11MHz tuning value for HFRCO, mask */
|
||||
#define _DEVINFO_HFRCOCAL0_BAND11_SHIFT 16 /**< 11MHz tuning value for HFRCO, shift */
|
||||
#define _DEVINFO_HFRCOCAL0_BAND14_MASK 0xFF000000UL /**< 14MHz tuning value for HFRCO, mask */
|
||||
#define _DEVINFO_HFRCOCAL0_BAND14_SHIFT 24 /**< 14MHz tuning value for HFRCO, shift */
|
||||
#define _DEVINFO_HFRCOCAL1_BAND21_MASK 0x000000FFUL /**< 21MHz tuning value for HFRCO, mask */
|
||||
#define _DEVINFO_HFRCOCAL1_BAND21_SHIFT 0 /**< 21MHz tuning value for HFRCO, shift */
|
||||
#define _DEVINFO_HFRCOCAL1_BAND28_MASK 0x0000FF00UL /**< 28MHz tuning value for HFRCO, shift */
|
||||
#define _DEVINFO_HFRCOCAL1_BAND28_SHIFT 8 /**< 28MHz tuning value for HFRCO, mask */
|
||||
#define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL /**< Lower part of 64-bit device unique number */
|
||||
#define _DEVINFO_UNIQUEL_SHIFT 0 /**< Unique Low 32-bit shift */
|
||||
#define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL /**< High part of 64-bit device unique number */
|
||||
#define _DEVINFO_UNIQUEH_SHIFT 0 /**< Unique High 32-bit shift */
|
||||
#define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL /**< Flash size in kilobytes */
|
||||
#define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Bit position for flash size */
|
||||
#define _DEVINFO_MSIZE_FLASH_MASK 0x0000FFFFUL /**< SRAM size in kilobytes */
|
||||
#define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Bit position for SRAM size */
|
||||
#define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL /**< Production revision */
|
||||
#define _DEVINFO_PART_PROD_REV_SHIFT 24 /**< Bit position for production revision */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_MASK 0x00FF0000UL /**< Device Family, 0x47 for Gecko */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16 /**< Bit position for device family */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_G 71 /**< Gecko Device Family */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_GG 72 /**< Giant Gecko Device Family */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_TG 73 /**< Tiny Gecko Device Family */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_LG 74 /**< Leopard Gecko Device Family */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_WG 75 /**< Wonder Gecko Device Family */
|
||||
#define _DEVINFO_PART_DEVICE_FAMILY_ZG 76 /**< Zero Gecko Device Family */
|
||||
#define _DEVINFO_PART_DEVICE_NUMBER_MASK 0x0000FFFFUL /**< Device number */
|
||||
#define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /**< Bit position for device number */
|
||||
|
||||
/** @} End of group EFM32G_DEVINFO */
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,40 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief efm32g_dma_.h Register and Bit Field definitions
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @brief DMA_CH EFM32G DMA CH
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Channel Control Register */
|
||||
} DMA_CH_TypeDef;
|
||||
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief efm32g_dma_descriptor Register and Bit Field definitions
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_DMA_DESCRIPTOR
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
/* Note! Use of double __IO (volatile) qualifier to ensure that both */
|
||||
/* pointer and referenced memory are declared volatile. */
|
||||
__IO void * __IO SRCEND; /**< DMA source address end */
|
||||
__IO void * __IO DSTEND; /**< DMA destination address end */
|
||||
__IO uint32_t CTRL; /**< DMA control register */
|
||||
__IO uint32_t USER; /**< DMA padding register, available for user */
|
||||
} DMA_DESCRIPTOR_TypeDef; /** @} */
|
||||
|
||||
|
|
@ -0,0 +1,137 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief efm32g_dmactrl Register and Bit Field definitions
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_DMACTRL_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define _DMA_CTRL_DST_INC_MASK 0xC0000000UL /**< Data increment for destination, bit mask */
|
||||
#define _DMA_CTRL_DST_INC_SHIFT 30 /**< Data increment for destination, shift value */
|
||||
#define _DMA_CTRL_DST_INC_BYTE 0x00 /**< Byte/8-bit increment */
|
||||
#define _DMA_CTRL_DST_INC_HALFWORD 0x01 /**< Half word/16-bit increment */
|
||||
#define _DMA_CTRL_DST_INC_WORD 0x02 /**< Word/32-bit increment */
|
||||
#define _DMA_CTRL_DST_INC_NONE 0x03 /**< No increment */
|
||||
#define DMA_CTRL_DST_INC_BYTE 0x00000000UL /**< Byte/8-bit increment */
|
||||
#define DMA_CTRL_DST_INC_HALFWORD 0x40000000UL /**< Half word/16-bit increment */
|
||||
#define DMA_CTRL_DST_INC_WORD 0x80000000UL /**< Word/32-bit increment */
|
||||
#define DMA_CTRL_DST_INC_NONE 0xC0000000UL /**< No increment */
|
||||
#define _DMA_CTRL_DST_SIZE_MASK 0x30000000UL /**< Data size for destination - MUST be the same as source, bit mask */
|
||||
#define _DMA_CTRL_DST_SIZE_SHIFT 28 /**< Data size for destination - MUST be the same as source, shift value */
|
||||
#define _DMA_CTRL_DST_SIZE_BYTE 0x00 /**< Byte/8-bit data size */
|
||||
#define _DMA_CTRL_DST_SIZE_HALFWORD 0x01 /**< Half word/16-bit data size */
|
||||
#define _DMA_CTRL_DST_SIZE_WORD 0x02 /**< Word/32-bit data size */
|
||||
#define _DMA_CTRL_DST_SIZE_RSVD 0x03 /**< Reserved */
|
||||
#define DMA_CTRL_DST_SIZE_BYTE 0x00000000UL /**< Byte/8-bit data size */
|
||||
#define DMA_CTRL_DST_SIZE_HALFWORD 0x10000000UL /**< Half word/16-bit data size */
|
||||
#define DMA_CTRL_DST_SIZE_WORD 0x20000000UL /**< Word/32-bit data size */
|
||||
#define DMA_CTRL_DST_SIZE_RSVD 0x30000000UL /**< Reserved - do not use */
|
||||
#define _DMA_CTRL_SRC_INC_MASK 0x0C000000UL /**< Data increment for source, bit mask */
|
||||
#define _DMA_CTRL_SRC_INC_SHIFT 26 /**< Data increment for source, shift value */
|
||||
#define _DMA_CTRL_SRC_INC_BYTE 0x00 /**< Byte/8-bit increment */
|
||||
#define _DMA_CTRL_SRC_INC_HALFWORD 0x01 /**< Half word/16-bit increment */
|
||||
#define _DMA_CTRL_SRC_INC_WORD 0x02 /**< Word/32-bit increment */
|
||||
#define _DMA_CTRL_SRC_INC_NONE 0x03 /**< No increment */
|
||||
#define DMA_CTRL_SRC_INC_BYTE 0x00000000UL /**< Byte/8-bit increment */
|
||||
#define DMA_CTRL_SRC_INC_HALFWORD 0x04000000UL /**< Half word/16-bit increment */
|
||||
#define DMA_CTRL_SRC_INC_WORD 0x08000000UL /**< Word/32-bit increment */
|
||||
#define DMA_CTRL_SRC_INC_NONE 0x0C000000UL /**< No increment */
|
||||
#define _DMA_CTRL_SRC_SIZE_MASK 0x03000000UL /**< Data size for source - MUST be the same as destination, bit mask */
|
||||
#define _DMA_CTRL_SRC_SIZE_SHIFT 24 /**< Data size for source - MUST be the same as destination, shift value */
|
||||
#define _DMA_CTRL_SRC_SIZE_BYTE 0x00 /**< Byte/8-bit data size */
|
||||
#define _DMA_CTRL_SRC_SIZE_HALFWORD 0x01 /**< Half word/16-bit data size */
|
||||
#define _DMA_CTRL_SRC_SIZE_WORD 0x02 /**< Word/32-bit data size */
|
||||
#define _DMA_CTRL_SRC_SIZE_RSVD 0x03 /**< Reserved */
|
||||
#define DMA_CTRL_SRC_SIZE_BYTE 0x00000000UL /**< Byte/8-bit data size */
|
||||
#define DMA_CTRL_SRC_SIZE_HALFWORD 0x01000000UL /**< Half word/16-bit data size */
|
||||
#define DMA_CTRL_SRC_SIZE_WORD 0x02000000UL /**< Word/32-bit data size */
|
||||
#define DMA_CTRL_SRC_SIZE_RSVD 0x03000000UL /**< Reserved - do not use */
|
||||
#define _DMA_CTRL_DST_PROT_CTRL_MASK 0x00E00000UL /**< Protection flag for destination, bit mask */
|
||||
#define _DMA_CTRL_DST_PROT_CTRL_SHIFT 21 /**< Protection flag for destination, shift value */
|
||||
#define DMA_CTRL_DST_PROT_PRIVILEGED 0x00200000UL /**< Privileged mode for destination */
|
||||
#define DMA_CTRL_DST_PROT_NON_PRIVILEGED 0x00000000UL /**< Non-privileged mode for estination */
|
||||
#define _DMA_CTRL_SRC_PROT_CTRL_MASK 0x001C0000UL /**< Protection flag for source, bit mask */
|
||||
#define _DMA_CTRL_SRC_PROT_CTRL_SHIFT 18 /**< Protection flag for source, shift value */
|
||||
#define DMA_CTRL_SRC_PROT_PRIVILEGED 0x00040000UL /**< Privileged mode for destination */
|
||||
#define DMA_CTRL_SRC_PROT_NON_PRIVILEGED 0x00000000UL /**< Non-privileged mode for estination */
|
||||
#define _DMA_CTRL_PROT_NON_PRIVILEGED 0x00 /**< Protection bits to indicate non-privileged access */
|
||||
#define _DMA_CTRL_PROT_PRIVILEGED 0x01 /**< Protection bits to indicate privileged access */
|
||||
#define _DMA_CTRL_R_POWER_MASK 0x0003C000UL /**< DMA arbitration mask */
|
||||
#define _DMA_CTRL_R_POWER_SHIFT 14 /**< Number of DMA cycles before controller does new arbitration in 2^R */
|
||||
#define _DMA_CTRL_R_POWER_1 0x00 /**< Arbitrate after each transfer */
|
||||
#define _DMA_CTRL_R_POWER_2 0x01 /**< Arbitrate after every 2 transfers */
|
||||
#define _DMA_CTRL_R_POWER_4 0x02 /**< Arbitrate after every 4 transfers */
|
||||
#define _DMA_CTRL_R_POWER_8 0x03 /**< Arbitrate after every 8 transfers */
|
||||
#define _DMA_CTRL_R_POWER_16 0x04 /**< Arbitrate after every 16 transfers */
|
||||
#define _DMA_CTRL_R_POWER_32 0x05 /**< Arbitrate after every 32 transfers */
|
||||
#define _DMA_CTRL_R_POWER_64 0x06 /**< Arbitrate after every 64 transfers */
|
||||
#define _DMA_CTRL_R_POWER_128 0x07 /**< Arbitrate after every 128 transfers */
|
||||
#define _DMA_CTRL_R_POWER_256 0x08 /**< Arbitrate after every 256 transfers */
|
||||
#define _DMA_CTRL_R_POWER_512 0x09 /**< Arbitrate after every 512 transfers */
|
||||
#define _DMA_CTRL_R_POWER_1024 0x0a /**< Arbitrate after every 1024 transfers */
|
||||
#define DMA_CTRL_R_POWER_1 0x00000000UL /**< Arbitrate after each transfer */
|
||||
#define DMA_CTRL_R_POWER_2 0x00004000UL /**< Arbitrate after every 2 transfers */
|
||||
#define DMA_CTRL_R_POWER_4 0x00008000UL /**< Arbitrate after every 4 transfers */
|
||||
#define DMA_CTRL_R_POWER_8 0x0000c000UL /**< Arbitrate after every 8 transfers */
|
||||
#define DMA_CTRL_R_POWER_16 0x00010000UL /**< Arbitrate after every 16 transfers */
|
||||
#define DMA_CTRL_R_POWER_32 0x00014000UL /**< Arbitrate after every 32 transfers */
|
||||
#define DMA_CTRL_R_POWER_64 0x00018000UL /**< Arbitrate after every 64 transfers */
|
||||
#define DMA_CTRL_R_POWER_128 0x0001c000UL /**< Arbitrate after every 128 transfers */
|
||||
#define DMA_CTRL_R_POWER_256 0x00020000UL /**< Arbitrate after every 256 transfers */
|
||||
#define DMA_CTRL_R_POWER_512 0x00024000UL /**< Arbitrate after every 512 transfers */
|
||||
#define DMA_CTRL_R_POWER_1024 0x00028000UL /**< Arbitrate after every 1024 transfers */
|
||||
#define _DMA_CTRL_N_MINUS_1_MASK 0x00003FF0UL /**< Number of DMA transfers minus 1, bit mask. See PL230 documentation */
|
||||
#define _DMA_CTRL_N_MINUS_1_SHIFT 4 /**< Number of DMA transfers minus 1, shift mask. See PL230 documentation */
|
||||
#define _DMA_CTRL_NEXT_USEBURST_MASK 0x00000008UL /**< DMA useburst_set[C] is 1 when using scatter-gather DMA and using alternate data */
|
||||
#define _DMA_CTRL_NEXT_USEBURST_SHIFT 3 /**< DMA useburst shift */
|
||||
#define _DMA_CTRL_CYCLE_CTRL_MASK 0x00000007UL /**< DMA Cycle control bit mask - basic/auto/ping-poing/scath-gath */
|
||||
#define _DMA_CTRL_CYCLE_CTRL_SHIFT 0 /**< DMA Cycle control bit shift */
|
||||
#define _DMA_CTRL_CYCLE_CTRL_INVALID 0x00 /**< Invalid cycle type */
|
||||
#define _DMA_CTRL_CYCLE_CTRL_BASIC 0x01 /**< Basic cycle type */
|
||||
#define _DMA_CTRL_CYCLE_CTRL_AUTO 0x02 /**< Auto cycle type */
|
||||
#define _DMA_CTRL_CYCLE_CTRL_PINGPONG 0x03 /**< PingPong cycle type */
|
||||
#define _DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER 0x04 /**< Memory scatter gather cycle type */
|
||||
#define _DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT 0x05 /**< Memory scatter gather using alternate structure */
|
||||
#define _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER 0x06 /**< Peripheral scatter gather cycle type */
|
||||
#define _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT 0x07 /**< Peripheral scatter gather cycle type using alternate structure */
|
||||
#define DMA_CTRL_CYCLE_CTRL_INVALID 0x00000000UL /**< Invalid cycle type */
|
||||
#define DMA_CTRL_CYCLE_CTRL_BASIC 0x00000001UL /**< Basic cycle type */
|
||||
#define DMA_CTRL_CYCLE_CTRL_AUTO 0x00000002UL /**< Auto cycle type */
|
||||
#define DMA_CTRL_CYCLE_CTRL_PINGPONG 0x00000003UL /**< PingPong cycle type */
|
||||
#define DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER 0x000000004UL /**< Memory scatter gather cycle type */
|
||||
#define DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT 0x000000005UL /**< Memory scatter gather using alternate structure */
|
||||
#define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER 0x000000006UL /**< Peripheral scatter gather cycle type */
|
||||
#define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT 0x000000007UL /**< Peripheral scatter gather cycle type using alternate structure */
|
||||
|
||||
/** @} End of group EFM32G_DMA */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief efm32g_dmareq Register and Bit Field definitions
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_DMAREQ_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
#define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) /**< DMA channel select for ADC0_SINGLE */
|
||||
#define DMAREQ_ADC0_SCAN ((8 << 16) + 1) /**< DMA channel select for ADC0_SCAN */
|
||||
#define DMAREQ_DAC0_CH0 ((10 << 16) + 0) /**< DMA channel select for DAC0_CH0 */
|
||||
#define DMAREQ_DAC0_CH1 ((10 << 16) + 1) /**< DMA channel select for DAC0_CH1 */
|
||||
#define DMAREQ_USART0_RXDATAV ((12 << 16) + 0) /**< DMA channel select for USART0_RXDATAV */
|
||||
#define DMAREQ_USART0_TXBL ((12 << 16) + 1) /**< DMA channel select for USART0_TXBL */
|
||||
#define DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) /**< DMA channel select for USART0_TXEMPTY */
|
||||
#define DMAREQ_USART1_RXDATAV ((13 << 16) + 0) /**< DMA channel select for USART1_RXDATAV */
|
||||
#define DMAREQ_USART1_TXBL ((13 << 16) + 1) /**< DMA channel select for USART1_TXBL */
|
||||
#define DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) /**< DMA channel select for USART1_TXEMPTY */
|
||||
#define DMAREQ_USART2_RXDATAV ((14 << 16) + 0) /**< DMA channel select for USART2_RXDATAV */
|
||||
#define DMAREQ_USART2_TXBL ((14 << 16) + 1) /**< DMA channel select for USART2_TXBL */
|
||||
#define DMAREQ_USART2_TXEMPTY ((14 << 16) + 2) /**< DMA channel select for USART2_TXEMPTY */
|
||||
#define DMAREQ_LEUART0_RXDATAV ((16 << 16) + 0) /**< DMA channel select for LEUART0_RXDATAV */
|
||||
#define DMAREQ_LEUART0_TXBL ((16 << 16) + 1) /**< DMA channel select for LEUART0_TXBL */
|
||||
#define DMAREQ_LEUART0_TXEMPTY ((16 << 16) + 2) /**< DMA channel select for LEUART0_TXEMPTY */
|
||||
#define DMAREQ_LEUART1_RXDATAV ((17 << 16) + 0) /**< DMA channel select for LEUART1_RXDATAV */
|
||||
#define DMAREQ_LEUART1_TXBL ((17 << 16) + 1) /**< DMA channel select for LEUART1_TXBL */
|
||||
#define DMAREQ_LEUART1_TXEMPTY ((17 << 16) + 2) /**< DMA channel select for LEUART1_TXEMPTY */
|
||||
#define DMAREQ_I2C0_RXDATAV ((20 << 16) + 0) /**< DMA channel select for I2C0_RXDATAV */
|
||||
#define DMAREQ_I2C0_TXBL ((20 << 16) + 1) /**< DMA channel select for I2C0_TXBL */
|
||||
#define DMAREQ_TIMER0_UFOF ((24 << 16) + 0) /**< DMA channel select for TIMER0_UFOF */
|
||||
#define DMAREQ_TIMER0_CC0 ((24 << 16) + 1) /**< DMA channel select for TIMER0_CC0 */
|
||||
#define DMAREQ_TIMER0_CC1 ((24 << 16) + 2) /**< DMA channel select for TIMER0_CC1 */
|
||||
#define DMAREQ_TIMER0_CC2 ((24 << 16) + 3) /**< DMA channel select for TIMER0_CC2 */
|
||||
#define DMAREQ_TIMER1_UFOF ((25 << 16) + 0) /**< DMA channel select for TIMER1_UFOF */
|
||||
#define DMAREQ_TIMER1_CC0 ((25 << 16) + 1) /**< DMA channel select for TIMER1_CC0 */
|
||||
#define DMAREQ_TIMER1_CC1 ((25 << 16) + 2) /**< DMA channel select for TIMER1_CC1 */
|
||||
#define DMAREQ_TIMER1_CC2 ((25 << 16) + 3) /**< DMA channel select for TIMER1_CC2 */
|
||||
#define DMAREQ_TIMER2_UFOF ((26 << 16) + 0) /**< DMA channel select for TIMER2_UFOF */
|
||||
#define DMAREQ_TIMER2_CC0 ((26 << 16) + 1) /**< DMA channel select for TIMER2_CC0 */
|
||||
#define DMAREQ_TIMER2_CC1 ((26 << 16) + 2) /**< DMA channel select for TIMER2_CC1 */
|
||||
#define DMAREQ_TIMER2_CC2 ((26 << 16) + 3) /**< DMA channel select for TIMER2_CC2 */
|
||||
#define DMAREQ_UART0_RXDATAV ((44 << 16) + 0) /**< DMA channel select for UART0_RXDATAV */
|
||||
#define DMAREQ_UART0_TXBL ((44 << 16) + 1) /**< DMA channel select for UART0_TXBL */
|
||||
#define DMAREQ_UART0_TXEMPTY ((44 << 16) + 2) /**< DMA channel select for UART0_TXEMPTY */
|
||||
#define DMAREQ_MSC_WDATA ((48 << 16) + 0) /**< DMA channel select for MSC_WDATA */
|
||||
#define DMAREQ_AES_DATAWR ((49 << 16) + 0) /**< DMA channel select for AES_DATAWR */
|
||||
#define DMAREQ_AES_XORDATAWR ((49 << 16) + 1) /**< DMA channel select for AES_XORDATAWR */
|
||||
#define DMAREQ_AES_DATARD ((49 << 16) + 2) /**< DMA channel select for AES_DATARD */
|
||||
#define DMAREQ_AES_KEYWR ((49 << 16) + 3) /**< DMA channel select for AES_KEYWR */
|
||||
|
||||
/** @} End of group EFM32G_DMAREQ */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,231 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief efm32g_ebi Register and Bit Field definitions
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_EBI
|
||||
* @{
|
||||
* @brief EFM32G_EBI Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__IO uint32_t ADDRTIMING; /**< Address Timing Register */
|
||||
__IO uint32_t RDTIMING; /**< Read Timing Register */
|
||||
__IO uint32_t WRTIMING; /**< Write Timing Register */
|
||||
__IO uint32_t POLARITY; /**< Polarity Register */
|
||||
__IO uint32_t ROUTE; /**< I/O Routing Register */
|
||||
} EBI_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_EBI_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/* Bit fields for EBI CTRL */
|
||||
#define _EBI_CTRL_RESETVALUE 0x00000000UL /**< Default value for EBI_CTRL */
|
||||
#define _EBI_CTRL_MASK 0x00030F03UL /**< Mask for EBI_CTRL */
|
||||
#define _EBI_CTRL_MODE_SHIFT 0 /**< Shift value for EBI_MODE */
|
||||
#define _EBI_CTRL_MODE_MASK 0x3UL /**< Bit mask for EBI_MODE */
|
||||
#define _EBI_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
|
||||
#define _EBI_CTRL_MODE_D8A8 0x00000000UL /**< Mode D8A8 for EBI_CTRL */
|
||||
#define _EBI_CTRL_MODE_D16A16ALE 0x00000001UL /**< Mode D16A16ALE for EBI_CTRL */
|
||||
#define _EBI_CTRL_MODE_D8A24ALE 0x00000002UL /**< Mode D8A24ALE for EBI_CTRL */
|
||||
#define EBI_CTRL_MODE_DEFAULT (_EBI_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_CTRL */
|
||||
#define EBI_CTRL_MODE_D8A8 (_EBI_CTRL_MODE_D8A8 << 0) /**< Shifted mode D8A8 for EBI_CTRL */
|
||||
#define EBI_CTRL_MODE_D16A16ALE (_EBI_CTRL_MODE_D16A16ALE << 0) /**< Shifted mode D16A16ALE for EBI_CTRL */
|
||||
#define EBI_CTRL_MODE_D8A24ALE (_EBI_CTRL_MODE_D8A24ALE << 0) /**< Shifted mode D8A24ALE for EBI_CTRL */
|
||||
#define EBI_CTRL_BANK0EN (0x1UL << 8) /**< Bank 0 Enable */
|
||||
#define _EBI_CTRL_BANK0EN_SHIFT 8 /**< Shift value for EBI_BANK0EN */
|
||||
#define _EBI_CTRL_BANK0EN_MASK 0x100UL /**< Bit mask for EBI_BANK0EN */
|
||||
#define _EBI_CTRL_BANK0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
|
||||
#define EBI_CTRL_BANK0EN_DEFAULT (_EBI_CTRL_BANK0EN_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_CTRL */
|
||||
#define EBI_CTRL_BANK1EN (0x1UL << 9) /**< Bank 1 Enable */
|
||||
#define _EBI_CTRL_BANK1EN_SHIFT 9 /**< Shift value for EBI_BANK1EN */
|
||||
#define _EBI_CTRL_BANK1EN_MASK 0x200UL /**< Bit mask for EBI_BANK1EN */
|
||||
#define _EBI_CTRL_BANK1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
|
||||
#define EBI_CTRL_BANK1EN_DEFAULT (_EBI_CTRL_BANK1EN_DEFAULT << 9) /**< Shifted mode DEFAULT for EBI_CTRL */
|
||||
#define EBI_CTRL_BANK2EN (0x1UL << 10) /**< Bank 2 Enable */
|
||||
#define _EBI_CTRL_BANK2EN_SHIFT 10 /**< Shift value for EBI_BANK2EN */
|
||||
#define _EBI_CTRL_BANK2EN_MASK 0x400UL /**< Bit mask for EBI_BANK2EN */
|
||||
#define _EBI_CTRL_BANK2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
|
||||
#define EBI_CTRL_BANK2EN_DEFAULT (_EBI_CTRL_BANK2EN_DEFAULT << 10) /**< Shifted mode DEFAULT for EBI_CTRL */
|
||||
#define EBI_CTRL_BANK3EN (0x1UL << 11) /**< Bank 3 Enable */
|
||||
#define _EBI_CTRL_BANK3EN_SHIFT 11 /**< Shift value for EBI_BANK3EN */
|
||||
#define _EBI_CTRL_BANK3EN_MASK 0x800UL /**< Bit mask for EBI_BANK3EN */
|
||||
#define _EBI_CTRL_BANK3EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
|
||||
#define EBI_CTRL_BANK3EN_DEFAULT (_EBI_CTRL_BANK3EN_DEFAULT << 11) /**< Shifted mode DEFAULT for EBI_CTRL */
|
||||
#define EBI_CTRL_ARDYEN (0x1UL << 16) /**< ARDY Enable */
|
||||
#define _EBI_CTRL_ARDYEN_SHIFT 16 /**< Shift value for EBI_ARDYEN */
|
||||
#define _EBI_CTRL_ARDYEN_MASK 0x10000UL /**< Bit mask for EBI_ARDYEN */
|
||||
#define _EBI_CTRL_ARDYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
|
||||
#define EBI_CTRL_ARDYEN_DEFAULT (_EBI_CTRL_ARDYEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_CTRL */
|
||||
#define EBI_CTRL_ARDYTODIS (0x1UL << 17) /**< ARDY Timeout Disable */
|
||||
#define _EBI_CTRL_ARDYTODIS_SHIFT 17 /**< Shift value for EBI_ARDYTODIS */
|
||||
#define _EBI_CTRL_ARDYTODIS_MASK 0x20000UL /**< Bit mask for EBI_ARDYTODIS */
|
||||
#define _EBI_CTRL_ARDYTODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_CTRL */
|
||||
#define EBI_CTRL_ARDYTODIS_DEFAULT (_EBI_CTRL_ARDYTODIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EBI_CTRL */
|
||||
|
||||
/* Bit fields for EBI ADDRTIMING */
|
||||
#define _EBI_ADDRTIMING_RESETVALUE 0x00000100UL /**< Default value for EBI_ADDRTIMING */
|
||||
#define _EBI_ADDRTIMING_MASK 0x00000303UL /**< Mask for EBI_ADDRTIMING */
|
||||
#define _EBI_ADDRTIMING_ADDRSETUP_SHIFT 0 /**< Shift value for EBI_ADDRSETUP */
|
||||
#define _EBI_ADDRTIMING_ADDRSETUP_MASK 0x3UL /**< Bit mask for EBI_ADDRSETUP */
|
||||
#define _EBI_ADDRTIMING_ADDRSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ADDRTIMING */
|
||||
#define EBI_ADDRTIMING_ADDRSETUP_DEFAULT (_EBI_ADDRTIMING_ADDRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ADDRTIMING */
|
||||
#define _EBI_ADDRTIMING_ADDRHOLD_SHIFT 8 /**< Shift value for EBI_ADDRHOLD */
|
||||
#define _EBI_ADDRTIMING_ADDRHOLD_MASK 0x300UL /**< Bit mask for EBI_ADDRHOLD */
|
||||
#define _EBI_ADDRTIMING_ADDRHOLD_DEFAULT 0x00000001UL /**< Mode DEFAULT for EBI_ADDRTIMING */
|
||||
#define EBI_ADDRTIMING_ADDRHOLD_DEFAULT (_EBI_ADDRTIMING_ADDRHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_ADDRTIMING */
|
||||
|
||||
/* Bit fields for EBI RDTIMING */
|
||||
#define _EBI_RDTIMING_RESETVALUE 0x00000000UL /**< Default value for EBI_RDTIMING */
|
||||
#define _EBI_RDTIMING_MASK 0x00030F03UL /**< Mask for EBI_RDTIMING */
|
||||
#define _EBI_RDTIMING_RDSETUP_SHIFT 0 /**< Shift value for EBI_RDSETUP */
|
||||
#define _EBI_RDTIMING_RDSETUP_MASK 0x3UL /**< Bit mask for EBI_RDSETUP */
|
||||
#define _EBI_RDTIMING_RDSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING */
|
||||
#define EBI_RDTIMING_RDSETUP_DEFAULT (_EBI_RDTIMING_RDSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_RDTIMING */
|
||||
#define _EBI_RDTIMING_RDSTRB_SHIFT 8 /**< Shift value for EBI_RDSTRB */
|
||||
#define _EBI_RDTIMING_RDSTRB_MASK 0xF00UL /**< Bit mask for EBI_RDSTRB */
|
||||
#define _EBI_RDTIMING_RDSTRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING */
|
||||
#define EBI_RDTIMING_RDSTRB_DEFAULT (_EBI_RDTIMING_RDSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_RDTIMING */
|
||||
#define _EBI_RDTIMING_RDHOLD_SHIFT 16 /**< Shift value for EBI_RDHOLD */
|
||||
#define _EBI_RDTIMING_RDHOLD_MASK 0x30000UL /**< Bit mask for EBI_RDHOLD */
|
||||
#define _EBI_RDTIMING_RDHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_RDTIMING */
|
||||
#define EBI_RDTIMING_RDHOLD_DEFAULT (_EBI_RDTIMING_RDHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_RDTIMING */
|
||||
|
||||
/* Bit fields for EBI WRTIMING */
|
||||
#define _EBI_WRTIMING_RESETVALUE 0x00010000UL /**< Default value for EBI_WRTIMING */
|
||||
#define _EBI_WRTIMING_MASK 0x00030F03UL /**< Mask for EBI_WRTIMING */
|
||||
#define _EBI_WRTIMING_WRSETUP_SHIFT 0 /**< Shift value for EBI_WRSETUP */
|
||||
#define _EBI_WRTIMING_WRSETUP_MASK 0x3UL /**< Bit mask for EBI_WRSETUP */
|
||||
#define _EBI_WRTIMING_WRSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING */
|
||||
#define EBI_WRTIMING_WRSETUP_DEFAULT (_EBI_WRTIMING_WRSETUP_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_WRTIMING */
|
||||
#define _EBI_WRTIMING_WRSTRB_SHIFT 8 /**< Shift value for EBI_WRSTRB */
|
||||
#define _EBI_WRTIMING_WRSTRB_MASK 0xF00UL /**< Bit mask for EBI_WRSTRB */
|
||||
#define _EBI_WRTIMING_WRSTRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_WRTIMING */
|
||||
#define EBI_WRTIMING_WRSTRB_DEFAULT (_EBI_WRTIMING_WRSTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for EBI_WRTIMING */
|
||||
#define _EBI_WRTIMING_WRHOLD_SHIFT 16 /**< Shift value for EBI_WRHOLD */
|
||||
#define _EBI_WRTIMING_WRHOLD_MASK 0x30000UL /**< Bit mask for EBI_WRHOLD */
|
||||
#define _EBI_WRTIMING_WRHOLD_DEFAULT 0x00000001UL /**< Mode DEFAULT for EBI_WRTIMING */
|
||||
#define EBI_WRTIMING_WRHOLD_DEFAULT (_EBI_WRTIMING_WRHOLD_DEFAULT << 16) /**< Shifted mode DEFAULT for EBI_WRTIMING */
|
||||
|
||||
/* Bit fields for EBI POLARITY */
|
||||
#define _EBI_POLARITY_RESETVALUE 0x00000000UL /**< Default value for EBI_POLARITY */
|
||||
#define _EBI_POLARITY_MASK 0x0000001FUL /**< Mask for EBI_POLARITY */
|
||||
#define EBI_POLARITY_CSPOL (0x1UL << 0) /**< Chip Select Polarity */
|
||||
#define _EBI_POLARITY_CSPOL_SHIFT 0 /**< Shift value for EBI_CSPOL */
|
||||
#define _EBI_POLARITY_CSPOL_MASK 0x1UL /**< Bit mask for EBI_CSPOL */
|
||||
#define _EBI_POLARITY_CSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */
|
||||
#define _EBI_POLARITY_CSPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */
|
||||
#define _EBI_POLARITY_CSPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */
|
||||
#define EBI_POLARITY_CSPOL_DEFAULT (_EBI_POLARITY_CSPOL_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_POLARITY */
|
||||
#define EBI_POLARITY_CSPOL_ACTIVELOW (_EBI_POLARITY_CSPOL_ACTIVELOW << 0) /**< Shifted mode ACTIVELOW for EBI_POLARITY */
|
||||
#define EBI_POLARITY_CSPOL_ACTIVEHIGH (_EBI_POLARITY_CSPOL_ACTIVEHIGH << 0) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */
|
||||
#define EBI_POLARITY_REPOL (0x1UL << 1) /**< Read Enable Polarity */
|
||||
#define _EBI_POLARITY_REPOL_SHIFT 1 /**< Shift value for EBI_REPOL */
|
||||
#define _EBI_POLARITY_REPOL_MASK 0x2UL /**< Bit mask for EBI_REPOL */
|
||||
#define _EBI_POLARITY_REPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */
|
||||
#define _EBI_POLARITY_REPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */
|
||||
#define _EBI_POLARITY_REPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */
|
||||
#define EBI_POLARITY_REPOL_DEFAULT (_EBI_POLARITY_REPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_POLARITY */
|
||||
#define EBI_POLARITY_REPOL_ACTIVELOW (_EBI_POLARITY_REPOL_ACTIVELOW << 1) /**< Shifted mode ACTIVELOW for EBI_POLARITY */
|
||||
#define EBI_POLARITY_REPOL_ACTIVEHIGH (_EBI_POLARITY_REPOL_ACTIVEHIGH << 1) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */
|
||||
#define EBI_POLARITY_WEPOL (0x1UL << 2) /**< Write Enable Polarity */
|
||||
#define _EBI_POLARITY_WEPOL_SHIFT 2 /**< Shift value for EBI_WEPOL */
|
||||
#define _EBI_POLARITY_WEPOL_MASK 0x4UL /**< Bit mask for EBI_WEPOL */
|
||||
#define _EBI_POLARITY_WEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */
|
||||
#define _EBI_POLARITY_WEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */
|
||||
#define _EBI_POLARITY_WEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */
|
||||
#define EBI_POLARITY_WEPOL_DEFAULT (_EBI_POLARITY_WEPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_POLARITY */
|
||||
#define EBI_POLARITY_WEPOL_ACTIVELOW (_EBI_POLARITY_WEPOL_ACTIVELOW << 2) /**< Shifted mode ACTIVELOW for EBI_POLARITY */
|
||||
#define EBI_POLARITY_WEPOL_ACTIVEHIGH (_EBI_POLARITY_WEPOL_ACTIVEHIGH << 2) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */
|
||||
#define EBI_POLARITY_ALEPOL (0x1UL << 3) /**< Address Latch Polarity */
|
||||
#define _EBI_POLARITY_ALEPOL_SHIFT 3 /**< Shift value for EBI_ALEPOL */
|
||||
#define _EBI_POLARITY_ALEPOL_MASK 0x8UL /**< Bit mask for EBI_ALEPOL */
|
||||
#define _EBI_POLARITY_ALEPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */
|
||||
#define _EBI_POLARITY_ALEPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */
|
||||
#define _EBI_POLARITY_ALEPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */
|
||||
#define EBI_POLARITY_ALEPOL_DEFAULT (_EBI_POLARITY_ALEPOL_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_POLARITY */
|
||||
#define EBI_POLARITY_ALEPOL_ACTIVELOW (_EBI_POLARITY_ALEPOL_ACTIVELOW << 3) /**< Shifted mode ACTIVELOW for EBI_POLARITY */
|
||||
#define EBI_POLARITY_ALEPOL_ACTIVEHIGH (_EBI_POLARITY_ALEPOL_ACTIVEHIGH << 3) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */
|
||||
#define EBI_POLARITY_ARDYPOL (0x1UL << 4) /**< ARDY Polarity */
|
||||
#define _EBI_POLARITY_ARDYPOL_SHIFT 4 /**< Shift value for EBI_ARDYPOL */
|
||||
#define _EBI_POLARITY_ARDYPOL_MASK 0x10UL /**< Bit mask for EBI_ARDYPOL */
|
||||
#define _EBI_POLARITY_ARDYPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_POLARITY */
|
||||
#define _EBI_POLARITY_ARDYPOL_ACTIVELOW 0x00000000UL /**< Mode ACTIVELOW for EBI_POLARITY */
|
||||
#define _EBI_POLARITY_ARDYPOL_ACTIVEHIGH 0x00000001UL /**< Mode ACTIVEHIGH for EBI_POLARITY */
|
||||
#define EBI_POLARITY_ARDYPOL_DEFAULT (_EBI_POLARITY_ARDYPOL_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_POLARITY */
|
||||
#define EBI_POLARITY_ARDYPOL_ACTIVELOW (_EBI_POLARITY_ARDYPOL_ACTIVELOW << 4) /**< Shifted mode ACTIVELOW for EBI_POLARITY */
|
||||
#define EBI_POLARITY_ARDYPOL_ACTIVEHIGH (_EBI_POLARITY_ARDYPOL_ACTIVEHIGH << 4) /**< Shifted mode ACTIVEHIGH for EBI_POLARITY */
|
||||
|
||||
/* Bit fields for EBI ROUTE */
|
||||
#define _EBI_ROUTE_RESETVALUE 0x00000000UL /**< Default value for EBI_ROUTE */
|
||||
#define _EBI_ROUTE_MASK 0x0000007FUL /**< Mask for EBI_ROUTE */
|
||||
#define EBI_ROUTE_EBIPEN (0x1UL << 0) /**< EBI Pin Enable */
|
||||
#define _EBI_ROUTE_EBIPEN_SHIFT 0 /**< Shift value for EBI_EBIPEN */
|
||||
#define _EBI_ROUTE_EBIPEN_MASK 0x1UL /**< Bit mask for EBI_EBIPEN */
|
||||
#define _EBI_ROUTE_EBIPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
|
||||
#define EBI_ROUTE_EBIPEN_DEFAULT (_EBI_ROUTE_EBIPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EBI_ROUTE */
|
||||
#define EBI_ROUTE_CS0PEN (0x1UL << 1) /**< EBI_CS0 Pin Enable */
|
||||
#define _EBI_ROUTE_CS0PEN_SHIFT 1 /**< Shift value for EBI_CS0PEN */
|
||||
#define _EBI_ROUTE_CS0PEN_MASK 0x2UL /**< Bit mask for EBI_CS0PEN */
|
||||
#define _EBI_ROUTE_CS0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
|
||||
#define EBI_ROUTE_CS0PEN_DEFAULT (_EBI_ROUTE_CS0PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EBI_ROUTE */
|
||||
#define EBI_ROUTE_CS1PEN (0x1UL << 2) /**< EBI_CS1 Pin Enable */
|
||||
#define _EBI_ROUTE_CS1PEN_SHIFT 2 /**< Shift value for EBI_CS1PEN */
|
||||
#define _EBI_ROUTE_CS1PEN_MASK 0x4UL /**< Bit mask for EBI_CS1PEN */
|
||||
#define _EBI_ROUTE_CS1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
|
||||
#define EBI_ROUTE_CS1PEN_DEFAULT (_EBI_ROUTE_CS1PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EBI_ROUTE */
|
||||
#define EBI_ROUTE_CS2PEN (0x1UL << 3) /**< EBI_CS2 Pin Enable */
|
||||
#define _EBI_ROUTE_CS2PEN_SHIFT 3 /**< Shift value for EBI_CS2PEN */
|
||||
#define _EBI_ROUTE_CS2PEN_MASK 0x8UL /**< Bit mask for EBI_CS2PEN */
|
||||
#define _EBI_ROUTE_CS2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
|
||||
#define EBI_ROUTE_CS2PEN_DEFAULT (_EBI_ROUTE_CS2PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for EBI_ROUTE */
|
||||
#define EBI_ROUTE_CS3PEN (0x1UL << 4) /**< EBI_CS3 Pin Enable */
|
||||
#define _EBI_ROUTE_CS3PEN_SHIFT 4 /**< Shift value for EBI_CS3PEN */
|
||||
#define _EBI_ROUTE_CS3PEN_MASK 0x10UL /**< Bit mask for EBI_CS3PEN */
|
||||
#define _EBI_ROUTE_CS3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
|
||||
#define EBI_ROUTE_CS3PEN_DEFAULT (_EBI_ROUTE_CS3PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EBI_ROUTE */
|
||||
#define EBI_ROUTE_ALEPEN (0x1UL << 5) /**< EBI_ALE Pin Enable */
|
||||
#define _EBI_ROUTE_ALEPEN_SHIFT 5 /**< Shift value for EBI_ALEPEN */
|
||||
#define _EBI_ROUTE_ALEPEN_MASK 0x20UL /**< Bit mask for EBI_ALEPEN */
|
||||
#define _EBI_ROUTE_ALEPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
|
||||
#define EBI_ROUTE_ALEPEN_DEFAULT (_EBI_ROUTE_ALEPEN_DEFAULT << 5) /**< Shifted mode DEFAULT for EBI_ROUTE */
|
||||
#define EBI_ROUTE_ARDYPEN (0x1UL << 6) /**< EBI_ARDY Pin Enable */
|
||||
#define _EBI_ROUTE_ARDYPEN_SHIFT 6 /**< Shift value for EBI_ARDYPEN */
|
||||
#define _EBI_ROUTE_ARDYPEN_MASK 0x40UL /**< Bit mask for EBI_ARDYPEN */
|
||||
#define _EBI_ROUTE_ARDYPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EBI_ROUTE */
|
||||
#define EBI_ROUTE_ARDYPEN_DEFAULT (_EBI_ROUTE_ARDYPEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EBI_ROUTE */
|
||||
|
||||
/** @} End of group EFM32G_EBI */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,116 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief efm32g_emu Register and Bit Field definitions
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_EMU
|
||||
* @{
|
||||
* @brief EFM32G_EMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__IO uint32_t MEMCTRL; /**< Memory Control Register */
|
||||
__IO uint32_t LOCK; /**< Configuration Lock Register */
|
||||
|
||||
uint32_t RESERVED0[6]; /**< Reserved for future use **/
|
||||
__IO uint32_t AUXCTRL; /**< Auxiliary Control Register */
|
||||
} EMU_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_EMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/* Bit fields for EMU CTRL */
|
||||
#define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
|
||||
#define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
|
||||
#define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
|
||||
#define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
|
||||
#define _EMU_CTRL_EMVREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
|
||||
#define _EMU_CTRL_EMVREG_REDUCED 0x00000000UL /**< Mode REDUCED for EMU_CTRL */
|
||||
#define _EMU_CTRL_EMVREG_FULL 0x00000001UL /**< Mode FULL for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG_DEFAULT (_EMU_CTRL_EMVREG_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG_REDUCED (_EMU_CTRL_EMVREG_REDUCED << 0) /**< Shifted mode REDUCED for EMU_CTRL */
|
||||
#define EMU_CTRL_EMVREG_FULL (_EMU_CTRL_EMVREG_FULL << 0) /**< Shifted mode FULL for EMU_CTRL */
|
||||
#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */
|
||||
#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */
|
||||
#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */
|
||||
#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
|
||||
#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */
|
||||
#define _EMU_CTRL_EM4CTRL_SHIFT 2 /**< Shift value for EMU_EM4CTRL */
|
||||
#define _EMU_CTRL_EM4CTRL_MASK 0xCUL /**< Bit mask for EMU_EM4CTRL */
|
||||
#define _EMU_CTRL_EM4CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
|
||||
#define EMU_CTRL_EM4CTRL_DEFAULT (_EMU_CTRL_EM4CTRL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */
|
||||
|
||||
/* Bit fields for EMU MEMCTRL */
|
||||
#define _EMU_MEMCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_MEMCTRL */
|
||||
#define _EMU_MEMCTRL_MASK 0x00000007UL /**< Mask for EMU_MEMCTRL */
|
||||
#define _EMU_MEMCTRL_POWERDOWN_SHIFT 0 /**< Shift value for EMU_POWERDOWN */
|
||||
#define _EMU_MEMCTRL_POWERDOWN_MASK 0x7UL /**< Bit mask for EMU_POWERDOWN */
|
||||
#define _EMU_MEMCTRL_POWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_MEMCTRL */
|
||||
#define _EMU_MEMCTRL_POWERDOWN_BLK3 0x00000004UL /**< Mode BLK3 for EMU_MEMCTRL */
|
||||
#define _EMU_MEMCTRL_POWERDOWN_BLK23 0x00000006UL /**< Mode BLK23 for EMU_MEMCTRL */
|
||||
#define _EMU_MEMCTRL_POWERDOWN_BLK123 0x00000007UL /**< Mode BLK123 for EMU_MEMCTRL */
|
||||
#define EMU_MEMCTRL_POWERDOWN_DEFAULT (_EMU_MEMCTRL_POWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_MEMCTRL */
|
||||
#define EMU_MEMCTRL_POWERDOWN_BLK3 (_EMU_MEMCTRL_POWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_MEMCTRL */
|
||||
#define EMU_MEMCTRL_POWERDOWN_BLK23 (_EMU_MEMCTRL_POWERDOWN_BLK23 << 0) /**< Shifted mode BLK23 for EMU_MEMCTRL */
|
||||
#define EMU_MEMCTRL_POWERDOWN_BLK123 (_EMU_MEMCTRL_POWERDOWN_BLK123 << 0) /**< Shifted mode BLK123 for EMU_MEMCTRL */
|
||||
|
||||
/* Bit fields for EMU LOCK */
|
||||
#define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */
|
||||
#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */
|
||||
#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
|
||||
#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
|
||||
#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */
|
||||
#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */
|
||||
#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */
|
||||
#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */
|
||||
#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */
|
||||
#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */
|
||||
#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */
|
||||
#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */
|
||||
#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */
|
||||
#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */
|
||||
|
||||
/* Bit fields for EMU AUXCTRL */
|
||||
#define _EMU_AUXCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_AUXCTRL */
|
||||
#define _EMU_AUXCTRL_MASK 0x00000001UL /**< Mask for EMU_AUXCTRL */
|
||||
#define EMU_AUXCTRL_HRCCLR (0x1UL << 0) /**< Hard Reset Cause Clear */
|
||||
#define _EMU_AUXCTRL_HRCCLR_SHIFT 0 /**< Shift value for EMU_HRCCLR */
|
||||
#define _EMU_AUXCTRL_HRCCLR_MASK 0x1UL /**< Bit mask for EMU_HRCCLR */
|
||||
#define _EMU_AUXCTRL_HRCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_AUXCTRL */
|
||||
#define EMU_AUXCTRL_HRCCLR_DEFAULT (_EMU_AUXCTRL_HRCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_AUXCTRL */
|
||||
|
||||
/** @} End of group EFM32G_EMU */
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,48 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief efm32g_gpio_p Register and Bit Field definitions
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @brief GPIO_P EFM32G GPIO P
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Port Control Register */
|
||||
__IO uint32_t MODEL; /**< Port Pin Mode Low Register */
|
||||
__IO uint32_t MODEH; /**< Port Pin Mode High Register */
|
||||
__IO uint32_t DOUT; /**< Port Data Out Register */
|
||||
__O uint32_t DOUTSET; /**< Port Data Out Set Register */
|
||||
__O uint32_t DOUTCLR; /**< Port Data Out Clear Register */
|
||||
__O uint32_t DOUTTGL; /**< Port Data Out Toggle Register */
|
||||
__I uint32_t DIN; /**< Port Data In Register */
|
||||
__IO uint32_t PINLOCKN; /**< Port Unlocked Pins Register */
|
||||
} GPIO_P_TypeDef;
|
||||
|
||||
|
|
@ -0,0 +1,696 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief efm32g_i2c Register and Bit Field definitions
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_I2C
|
||||
* @{
|
||||
* @brief EFM32G_I2C Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__IO uint32_t CMD; /**< Command Register */
|
||||
__I uint32_t STATE; /**< State Register */
|
||||
__I uint32_t STATUS; /**< Status Register */
|
||||
__IO uint32_t CLKDIV; /**< Clock Division Register */
|
||||
__IO uint32_t SADDR; /**< Slave Address Register */
|
||||
__IO uint32_t SADDRMASK; /**< Slave Address Mask Register */
|
||||
__I uint32_t RXDATA; /**< Receive Buffer Data Register */
|
||||
__I uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */
|
||||
__IO uint32_t TXDATA; /**< Transmit Buffer Data Register */
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IO uint32_t ROUTE; /**< I/O Routing Register */
|
||||
} I2C_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_I2C_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/* Bit fields for I2C CTRL */
|
||||
#define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */
|
||||
#define _I2C_CTRL_MASK 0x0007B37FUL /**< Mask for I2C_CTRL */
|
||||
#define I2C_CTRL_EN (0x1UL << 0) /**< I2C Enable */
|
||||
#define _I2C_CTRL_EN_SHIFT 0 /**< Shift value for I2C_EN */
|
||||
#define _I2C_CTRL_EN_MASK 0x1UL /**< Bit mask for I2C_EN */
|
||||
#define _I2C_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_EN_DEFAULT (_I2C_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Slave */
|
||||
#define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */
|
||||
#define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */
|
||||
#define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */
|
||||
#define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */
|
||||
#define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */
|
||||
#define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */
|
||||
#define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */
|
||||
#define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */
|
||||
#define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */
|
||||
#define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */
|
||||
#define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */
|
||||
#define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */
|
||||
#define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */
|
||||
#define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */
|
||||
#define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */
|
||||
#define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */
|
||||
#define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */
|
||||
#define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */
|
||||
#define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */
|
||||
#define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */
|
||||
#define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */
|
||||
#define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */
|
||||
#define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */
|
||||
#define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */
|
||||
#define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */
|
||||
#define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */
|
||||
#define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */
|
||||
#define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */
|
||||
#define _I2C_CTRL_BITO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */
|
||||
#define _I2C_CTRL_BITO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */
|
||||
#define _I2C_CTRL_BITO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */
|
||||
#define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */
|
||||
#define I2C_CTRL_BITO_40PCC (_I2C_CTRL_BITO_40PCC << 12) /**< Shifted mode 40PCC for I2C_CTRL */
|
||||
#define I2C_CTRL_BITO_80PCC (_I2C_CTRL_BITO_80PCC << 12) /**< Shifted mode 80PCC for I2C_CTRL */
|
||||
#define I2C_CTRL_BITO_160PCC (_I2C_CTRL_BITO_160PCC << 12) /**< Shifted mode 160PCC for I2C_CTRL */
|
||||
#define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */
|
||||
#define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */
|
||||
#define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */
|
||||
#define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */
|
||||
#define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */
|
||||
#define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */
|
||||
#define _I2C_CTRL_CLTO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */
|
||||
#define _I2C_CTRL_CLTO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */
|
||||
#define _I2C_CTRL_CLTO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */
|
||||
#define _I2C_CTRL_CLTO_320PPC 0x00000004UL /**< Mode 320PPC for I2C_CTRL */
|
||||
#define _I2C_CTRL_CLTO_1024PPC 0x00000005UL /**< Mode 1024PPC for I2C_CTRL */
|
||||
#define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */
|
||||
#define I2C_CTRL_CLTO_40PCC (_I2C_CTRL_CLTO_40PCC << 16) /**< Shifted mode 40PCC for I2C_CTRL */
|
||||
#define I2C_CTRL_CLTO_80PCC (_I2C_CTRL_CLTO_80PCC << 16) /**< Shifted mode 80PCC for I2C_CTRL */
|
||||
#define I2C_CTRL_CLTO_160PCC (_I2C_CTRL_CLTO_160PCC << 16) /**< Shifted mode 160PCC for I2C_CTRL */
|
||||
#define I2C_CTRL_CLTO_320PPC (_I2C_CTRL_CLTO_320PPC << 16) /**< Shifted mode 320PPC for I2C_CTRL */
|
||||
#define I2C_CTRL_CLTO_1024PPC (_I2C_CTRL_CLTO_1024PPC << 16) /**< Shifted mode 1024PPC for I2C_CTRL */
|
||||
|
||||
/* Bit fields for I2C CMD */
|
||||
#define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */
|
||||
#define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */
|
||||
#define I2C_CMD_START (0x1UL << 0) /**< Send start condition */
|
||||
#define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */
|
||||
#define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */
|
||||
#define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */
|
||||
#define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */
|
||||
#define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */
|
||||
#define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */
|
||||
#define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */
|
||||
#define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */
|
||||
#define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */
|
||||
#define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */
|
||||
#define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */
|
||||
#define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */
|
||||
#define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */
|
||||
#define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */
|
||||
#define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */
|
||||
#define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */
|
||||
#define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */
|
||||
#define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */
|
||||
#define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */
|
||||
#define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */
|
||||
#define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */
|
||||
#define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */
|
||||
#define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */
|
||||
#define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */
|
||||
|
||||
/* Bit fields for I2C STATE */
|
||||
#define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */
|
||||
#define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */
|
||||
#define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */
|
||||
#define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */
|
||||
#define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */
|
||||
#define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */
|
||||
#define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */
|
||||
#define I2C_STATE_MASTER (0x1UL << 1) /**< Master */
|
||||
#define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */
|
||||
#define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */
|
||||
#define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
|
||||
#define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */
|
||||
#define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */
|
||||
#define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */
|
||||
#define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */
|
||||
#define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
|
||||
#define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */
|
||||
#define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */
|
||||
#define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */
|
||||
#define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */
|
||||
#define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
|
||||
#define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */
|
||||
#define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */
|
||||
#define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */
|
||||
#define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */
|
||||
#define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
|
||||
#define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */
|
||||
#define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */
|
||||
#define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */
|
||||
#define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
|
||||
#define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */
|
||||
#define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */
|
||||
#define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */
|
||||
#define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */
|
||||
#define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */
|
||||
#define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */
|
||||
#define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */
|
||||
#define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */
|
||||
#define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */
|
||||
#define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */
|
||||
#define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */
|
||||
#define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */
|
||||
#define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */
|
||||
#define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */
|
||||
#define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */
|
||||
|
||||
/* Bit fields for I2C STATUS */
|
||||
#define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */
|
||||
#define _I2C_STATUS_MASK 0x000001FFUL /**< Mask for I2C_STATUS */
|
||||
#define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */
|
||||
#define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */
|
||||
#define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */
|
||||
#define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */
|
||||
#define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */
|
||||
#define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */
|
||||
#define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */
|
||||
#define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */
|
||||
#define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */
|
||||
#define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */
|
||||
#define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */
|
||||
#define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */
|
||||
#define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */
|
||||
#define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */
|
||||
#define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */
|
||||
#define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */
|
||||
#define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */
|
||||
#define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */
|
||||
#define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */
|
||||
#define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */
|
||||
#define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */
|
||||
#define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */
|
||||
#define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */
|
||||
#define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */
|
||||
#define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */
|
||||
#define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */
|
||||
#define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */
|
||||
#define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */
|
||||
|
||||
/* Bit fields for I2C CLKDIV */
|
||||
#define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */
|
||||
#define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */
|
||||
#define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */
|
||||
#define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */
|
||||
#define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */
|
||||
#define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */
|
||||
|
||||
/* Bit fields for I2C SADDR */
|
||||
#define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */
|
||||
#define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */
|
||||
#define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */
|
||||
#define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */
|
||||
#define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */
|
||||
#define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */
|
||||
|
||||
/* Bit fields for I2C SADDRMASK */
|
||||
#define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */
|
||||
#define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */
|
||||
#define _I2C_SADDRMASK_MASK_SHIFT 1 /**< Shift value for I2C_MASK */
|
||||
#define _I2C_SADDRMASK_MASK_MASK 0xFEUL /**< Bit mask for I2C_MASK */
|
||||
#define _I2C_SADDRMASK_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */
|
||||
#define I2C_SADDRMASK_MASK_DEFAULT (_I2C_SADDRMASK_MASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */
|
||||
|
||||
/* Bit fields for I2C RXDATA */
|
||||
#define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */
|
||||
#define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */
|
||||
#define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */
|
||||
#define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */
|
||||
#define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */
|
||||
#define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */
|
||||
|
||||
/* Bit fields for I2C RXDATAP */
|
||||
#define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */
|
||||
#define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */
|
||||
#define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */
|
||||
#define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */
|
||||
#define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */
|
||||
#define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */
|
||||
|
||||
/* Bit fields for I2C TXDATA */
|
||||
#define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */
|
||||
#define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */
|
||||
#define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */
|
||||
#define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */
|
||||
#define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */
|
||||
#define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */
|
||||
|
||||
/* Bit fields for I2C IF */
|
||||
#define _I2C_IF_RESETVALUE 0x00000010UL /**< Default value for I2C_IF */
|
||||
#define _I2C_IF_MASK 0x0001FFFFUL /**< Mask for I2C_IF */
|
||||
#define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */
|
||||
#define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */
|
||||
#define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */
|
||||
#define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */
|
||||
#define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
|
||||
#define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
|
||||
#define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */
|
||||
#define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
|
||||
#define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
|
||||
#define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */
|
||||
#define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
|
||||
#define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
|
||||
#define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */
|
||||
#define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */
|
||||
#define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */
|
||||
#define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */
|
||||
#define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */
|
||||
#define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */
|
||||
#define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */
|
||||
#define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
|
||||
#define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
|
||||
#define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */
|
||||
#define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
|
||||
#define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
|
||||
#define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_MSTOP (0x1UL << 8) /**< Master STOP Condition Interrupt Flag */
|
||||
#define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
|
||||
#define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
|
||||
#define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */
|
||||
#define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
|
||||
#define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
|
||||
#define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */
|
||||
#define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
|
||||
#define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
|
||||
#define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */
|
||||
#define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
|
||||
#define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
|
||||
#define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */
|
||||
#define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
|
||||
#define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
|
||||
#define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */
|
||||
#define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
|
||||
#define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
|
||||
#define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */
|
||||
#define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
|
||||
#define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
|
||||
#define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */
|
||||
#define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
|
||||
#define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
|
||||
#define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_SSTOP (0x1UL << 16) /**< Slave STOP condition Interrupt Flag */
|
||||
#define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
|
||||
#define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
|
||||
#define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
|
||||
/* Bit fields for I2C IFS */
|
||||
#define _I2C_IFS_RESETVALUE 0x00000000UL /**< Default value for I2C_IFS */
|
||||
#define _I2C_IFS_MASK 0x0001FFCFUL /**< Mask for I2C_IFS */
|
||||
#define I2C_IFS_START (0x1UL << 0) /**< Set START Interrupt Flag */
|
||||
#define _I2C_IFS_START_SHIFT 0 /**< Shift value for I2C_START */
|
||||
#define _I2C_IFS_START_MASK 0x1UL /**< Bit mask for I2C_START */
|
||||
#define _I2C_IFS_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_START_DEFAULT (_I2C_IFS_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_RSTART (0x1UL << 1) /**< Set Repeated START Interrupt Flag */
|
||||
#define _I2C_IFS_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
|
||||
#define _I2C_IFS_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
|
||||
#define _I2C_IFS_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_RSTART_DEFAULT (_I2C_IFS_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_ADDR (0x1UL << 2) /**< Set Address Interrupt Flag */
|
||||
#define _I2C_IFS_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
|
||||
#define _I2C_IFS_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
|
||||
#define _I2C_IFS_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_ADDR_DEFAULT (_I2C_IFS_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_TXC (0x1UL << 3) /**< Set Transfer Completed Interrupt Flag */
|
||||
#define _I2C_IFS_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
|
||||
#define _I2C_IFS_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
|
||||
#define _I2C_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_TXC_DEFAULT (_I2C_IFS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_ACK (0x1UL << 6) /**< Set Acknowledge Received Interrupt Flag */
|
||||
#define _I2C_IFS_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
|
||||
#define _I2C_IFS_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
|
||||
#define _I2C_IFS_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_ACK_DEFAULT (_I2C_IFS_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_NACK (0x1UL << 7) /**< Set Not Acknowledge Received Interrupt Flag */
|
||||
#define _I2C_IFS_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
|
||||
#define _I2C_IFS_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
|
||||
#define _I2C_IFS_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_NACK_DEFAULT (_I2C_IFS_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_MSTOP (0x1UL << 8) /**< Set MSTOP Interrupt Flag */
|
||||
#define _I2C_IFS_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
|
||||
#define _I2C_IFS_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
|
||||
#define _I2C_IFS_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_MSTOP_DEFAULT (_I2C_IFS_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_ARBLOST (0x1UL << 9) /**< Set Arbitration Lost Interrupt Flag */
|
||||
#define _I2C_IFS_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
|
||||
#define _I2C_IFS_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
|
||||
#define _I2C_IFS_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_ARBLOST_DEFAULT (_I2C_IFS_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_BUSERR (0x1UL << 10) /**< Set Bus Error Interrupt Flag */
|
||||
#define _I2C_IFS_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
|
||||
#define _I2C_IFS_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
|
||||
#define _I2C_IFS_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_BUSERR_DEFAULT (_I2C_IFS_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_BUSHOLD (0x1UL << 11) /**< Set Bus Held Interrupt Flag */
|
||||
#define _I2C_IFS_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
|
||||
#define _I2C_IFS_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
|
||||
#define _I2C_IFS_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_BUSHOLD_DEFAULT (_I2C_IFS_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_TXOF (0x1UL << 12) /**< Set Transmit Buffer Overflow Interrupt Flag */
|
||||
#define _I2C_IFS_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
|
||||
#define _I2C_IFS_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
|
||||
#define _I2C_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_TXOF_DEFAULT (_I2C_IFS_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_RXUF (0x1UL << 13) /**< Set Receive Buffer Underflow Interrupt Flag */
|
||||
#define _I2C_IFS_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
|
||||
#define _I2C_IFS_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
|
||||
#define _I2C_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_RXUF_DEFAULT (_I2C_IFS_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_BITO (0x1UL << 14) /**< Set Bus Idle Timeout Interrupt Flag */
|
||||
#define _I2C_IFS_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
|
||||
#define _I2C_IFS_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
|
||||
#define _I2C_IFS_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_BITO_DEFAULT (_I2C_IFS_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_CLTO (0x1UL << 15) /**< Set Clock Low Interrupt Flag */
|
||||
#define _I2C_IFS_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
|
||||
#define _I2C_IFS_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
|
||||
#define _I2C_IFS_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_CLTO_DEFAULT (_I2C_IFS_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_SSTOP (0x1UL << 16) /**< Set SSTOP Interrupt Flag */
|
||||
#define _I2C_IFS_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
|
||||
#define _I2C_IFS_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
|
||||
#define _I2C_IFS_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_SSTOP_DEFAULT (_I2C_IFS_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
|
||||
/* Bit fields for I2C IFC */
|
||||
#define _I2C_IFC_RESETVALUE 0x00000000UL /**< Default value for I2C_IFC */
|
||||
#define _I2C_IFC_MASK 0x0001FFCFUL /**< Mask for I2C_IFC */
|
||||
#define I2C_IFC_START (0x1UL << 0) /**< Clear START Interrupt Flag */
|
||||
#define _I2C_IFC_START_SHIFT 0 /**< Shift value for I2C_START */
|
||||
#define _I2C_IFC_START_MASK 0x1UL /**< Bit mask for I2C_START */
|
||||
#define _I2C_IFC_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_START_DEFAULT (_I2C_IFC_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_RSTART (0x1UL << 1) /**< Clear Repeated START Interrupt Flag */
|
||||
#define _I2C_IFC_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
|
||||
#define _I2C_IFC_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
|
||||
#define _I2C_IFC_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_RSTART_DEFAULT (_I2C_IFC_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_ADDR (0x1UL << 2) /**< Clear Address Interrupt Flag */
|
||||
#define _I2C_IFC_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
|
||||
#define _I2C_IFC_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
|
||||
#define _I2C_IFC_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_ADDR_DEFAULT (_I2C_IFC_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_TXC (0x1UL << 3) /**< Clear Transfer Completed Interrupt Flag */
|
||||
#define _I2C_IFC_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
|
||||
#define _I2C_IFC_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
|
||||
#define _I2C_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_TXC_DEFAULT (_I2C_IFC_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_ACK (0x1UL << 6) /**< Clear Acknowledge Received Interrupt Flag */
|
||||
#define _I2C_IFC_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
|
||||
#define _I2C_IFC_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
|
||||
#define _I2C_IFC_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_ACK_DEFAULT (_I2C_IFC_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_NACK (0x1UL << 7) /**< Clear Not Acknowledge Received Interrupt Flag */
|
||||
#define _I2C_IFC_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
|
||||
#define _I2C_IFC_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
|
||||
#define _I2C_IFC_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_NACK_DEFAULT (_I2C_IFC_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_MSTOP (0x1UL << 8) /**< Clear MSTOP Interrupt Flag */
|
||||
#define _I2C_IFC_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
|
||||
#define _I2C_IFC_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
|
||||
#define _I2C_IFC_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_MSTOP_DEFAULT (_I2C_IFC_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_ARBLOST (0x1UL << 9) /**< Clear Arbitration Lost Interrupt Flag */
|
||||
#define _I2C_IFC_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
|
||||
#define _I2C_IFC_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
|
||||
#define _I2C_IFC_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_ARBLOST_DEFAULT (_I2C_IFC_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_BUSERR (0x1UL << 10) /**< Clear Bus Error Interrupt Flag */
|
||||
#define _I2C_IFC_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
|
||||
#define _I2C_IFC_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
|
||||
#define _I2C_IFC_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_BUSERR_DEFAULT (_I2C_IFC_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_BUSHOLD (0x1UL << 11) /**< Clear Bus Held Interrupt Flag */
|
||||
#define _I2C_IFC_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
|
||||
#define _I2C_IFC_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
|
||||
#define _I2C_IFC_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_BUSHOLD_DEFAULT (_I2C_IFC_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_TXOF (0x1UL << 12) /**< Clear Transmit Buffer Overflow Interrupt Flag */
|
||||
#define _I2C_IFC_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
|
||||
#define _I2C_IFC_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
|
||||
#define _I2C_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_TXOF_DEFAULT (_I2C_IFC_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_RXUF (0x1UL << 13) /**< Clear Receive Buffer Underflow Interrupt Flag */
|
||||
#define _I2C_IFC_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
|
||||
#define _I2C_IFC_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
|
||||
#define _I2C_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_RXUF_DEFAULT (_I2C_IFC_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_BITO (0x1UL << 14) /**< Clear Bus Idle Timeout Interrupt Flag */
|
||||
#define _I2C_IFC_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
|
||||
#define _I2C_IFC_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
|
||||
#define _I2C_IFC_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_BITO_DEFAULT (_I2C_IFC_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_CLTO (0x1UL << 15) /**< Clear Clock Low Interrupt Flag */
|
||||
#define _I2C_IFC_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
|
||||
#define _I2C_IFC_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
|
||||
#define _I2C_IFC_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_CLTO_DEFAULT (_I2C_IFC_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_SSTOP (0x1UL << 16) /**< Clear SSTOP Interrupt Flag */
|
||||
#define _I2C_IFC_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
|
||||
#define _I2C_IFC_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
|
||||
#define _I2C_IFC_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_SSTOP_DEFAULT (_I2C_IFC_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
|
||||
/* Bit fields for I2C IEN */
|
||||
#define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */
|
||||
#define _I2C_IEN_MASK 0x0001FFFFUL /**< Mask for I2C_IEN */
|
||||
#define I2C_IEN_START (0x1UL << 0) /**< START Condition Interrupt Enable */
|
||||
#define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */
|
||||
#define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */
|
||||
#define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Enable */
|
||||
#define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
|
||||
#define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
|
||||
#define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_ADDR (0x1UL << 2) /**< Address Interrupt Enable */
|
||||
#define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
|
||||
#define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
|
||||
#define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Enable */
|
||||
#define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
|
||||
#define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
|
||||
#define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_TXBL (0x1UL << 4) /**< Transmit Buffer level Interrupt Enable */
|
||||
#define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */
|
||||
#define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */
|
||||
#define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Enable */
|
||||
#define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */
|
||||
#define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */
|
||||
#define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Enable */
|
||||
#define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
|
||||
#define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
|
||||
#define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Enable */
|
||||
#define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
|
||||
#define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
|
||||
#define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_MSTOP (0x1UL << 8) /**< MSTOP Interrupt Enable */
|
||||
#define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
|
||||
#define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
|
||||
#define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Enable */
|
||||
#define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
|
||||
#define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
|
||||
#define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Enable */
|
||||
#define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
|
||||
#define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
|
||||
#define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Enable */
|
||||
#define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
|
||||
#define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
|
||||
#define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Enable */
|
||||
#define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
|
||||
#define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
|
||||
#define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Enable */
|
||||
#define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
|
||||
#define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
|
||||
#define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Enable */
|
||||
#define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
|
||||
#define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
|
||||
#define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_CLTO (0x1UL << 15) /**< Clock Low Interrupt Enable */
|
||||
#define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
|
||||
#define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
|
||||
#define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_SSTOP (0x1UL << 16) /**< SSTOP Interrupt Enable */
|
||||
#define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
|
||||
#define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
|
||||
#define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
|
||||
/* Bit fields for I2C ROUTE */
|
||||
#define _I2C_ROUTE_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTE */
|
||||
#define _I2C_ROUTE_MASK 0x00000303UL /**< Mask for I2C_ROUTE */
|
||||
#define I2C_ROUTE_SDAPEN (0x1UL << 0) /**< SDA Pin Enable */
|
||||
#define _I2C_ROUTE_SDAPEN_SHIFT 0 /**< Shift value for I2C_SDAPEN */
|
||||
#define _I2C_ROUTE_SDAPEN_MASK 0x1UL /**< Bit mask for I2C_SDAPEN */
|
||||
#define _I2C_ROUTE_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTE */
|
||||
#define I2C_ROUTE_SDAPEN_DEFAULT (_I2C_ROUTE_SDAPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTE */
|
||||
#define I2C_ROUTE_SCLPEN (0x1UL << 1) /**< SCL Pin Enable */
|
||||
#define _I2C_ROUTE_SCLPEN_SHIFT 1 /**< Shift value for I2C_SCLPEN */
|
||||
#define _I2C_ROUTE_SCLPEN_MASK 0x2UL /**< Bit mask for I2C_SCLPEN */
|
||||
#define _I2C_ROUTE_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTE */
|
||||
#define I2C_ROUTE_SCLPEN_DEFAULT (_I2C_ROUTE_SCLPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_ROUTE */
|
||||
#define _I2C_ROUTE_LOCATION_SHIFT 8 /**< Shift value for I2C_LOCATION */
|
||||
#define _I2C_ROUTE_LOCATION_MASK 0x300UL /**< Bit mask for I2C_LOCATION */
|
||||
#define _I2C_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTE */
|
||||
#define _I2C_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTE */
|
||||
#define _I2C_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTE */
|
||||
#define _I2C_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTE */
|
||||
#define _I2C_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTE */
|
||||
#define I2C_ROUTE_LOCATION_DEFAULT (_I2C_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_ROUTE */
|
||||
#define I2C_ROUTE_LOCATION_LOC0 (_I2C_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for I2C_ROUTE */
|
||||
#define I2C_ROUTE_LOCATION_LOC1 (_I2C_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for I2C_ROUTE */
|
||||
#define I2C_ROUTE_LOCATION_LOC2 (_I2C_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for I2C_ROUTE */
|
||||
#define I2C_ROUTE_LOCATION_LOC3 (_I2C_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for I2C_ROUTE */
|
||||
|
||||
/** @} End of group EFM32G_I2C */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,456 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief efm32g_lcd Register and Bit Field definitions
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_LCD
|
||||
* @{
|
||||
* @brief EFM32G_LCD Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__IO uint32_t DISPCTRL; /**< Display Control Register */
|
||||
__IO uint32_t SEGEN; /**< Segment Enable Register */
|
||||
__IO uint32_t BACTRL; /**< Blink and Animation Control Register */
|
||||
__I uint32_t STATUS; /**< Status Register */
|
||||
__IO uint32_t AREGA; /**< Animation Register A */
|
||||
__IO uint32_t AREGB; /**< Animation Register B */
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
|
||||
uint32_t RESERVED0[5]; /**< Reserved for future use **/
|
||||
__IO uint32_t SEGD0L; /**< Segment Data Low Register 0 */
|
||||
__IO uint32_t SEGD1L; /**< Segment Data Low Register 1 */
|
||||
__IO uint32_t SEGD2L; /**< Segment Data Low Register 2 */
|
||||
__IO uint32_t SEGD3L; /**< Segment Data Low Register 3 */
|
||||
__IO uint32_t SEGD0H; /**< Segment Data High Register 0 */
|
||||
__IO uint32_t SEGD1H; /**< Segment Data High Register 1 */
|
||||
__IO uint32_t SEGD2H; /**< Segment Data High Register 2 */
|
||||
__IO uint32_t SEGD3H; /**< Segment Data High Register 3 */
|
||||
|
||||
__IO uint32_t FREEZE; /**< Freeze Register */
|
||||
__I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
} LCD_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_LCD_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/* Bit fields for LCD CTRL */
|
||||
#define _LCD_CTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_CTRL */
|
||||
#define _LCD_CTRL_MASK 0x00000007UL /**< Mask for LCD_CTRL */
|
||||
#define LCD_CTRL_EN (0x1UL << 0) /**< LCD Enable */
|
||||
#define _LCD_CTRL_EN_SHIFT 0 /**< Shift value for LCD_EN */
|
||||
#define _LCD_CTRL_EN_MASK 0x1UL /**< Bit mask for LCD_EN */
|
||||
#define _LCD_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */
|
||||
#define LCD_CTRL_EN_DEFAULT (_LCD_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_CTRL */
|
||||
#define _LCD_CTRL_UDCTRL_SHIFT 1 /**< Shift value for LCD_UDCTRL */
|
||||
#define _LCD_CTRL_UDCTRL_MASK 0x6UL /**< Bit mask for LCD_UDCTRL */
|
||||
#define _LCD_CTRL_UDCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */
|
||||
#define _LCD_CTRL_UDCTRL_REGULAR 0x00000000UL /**< Mode REGULAR for LCD_CTRL */
|
||||
#define _LCD_CTRL_UDCTRL_FCEVENT 0x00000001UL /**< Mode FCEVENT for LCD_CTRL */
|
||||
#define _LCD_CTRL_UDCTRL_FRAMESTART 0x00000002UL /**< Mode FRAMESTART for LCD_CTRL */
|
||||
#define LCD_CTRL_UDCTRL_DEFAULT (_LCD_CTRL_UDCTRL_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_CTRL */
|
||||
#define LCD_CTRL_UDCTRL_REGULAR (_LCD_CTRL_UDCTRL_REGULAR << 1) /**< Shifted mode REGULAR for LCD_CTRL */
|
||||
#define LCD_CTRL_UDCTRL_FCEVENT (_LCD_CTRL_UDCTRL_FCEVENT << 1) /**< Shifted mode FCEVENT for LCD_CTRL */
|
||||
#define LCD_CTRL_UDCTRL_FRAMESTART (_LCD_CTRL_UDCTRL_FRAMESTART << 1) /**< Shifted mode FRAMESTART for LCD_CTRL */
|
||||
|
||||
/* Bit fields for LCD DISPCTRL */
|
||||
#define _LCD_DISPCTRL_RESETVALUE 0x000C1F00UL /**< Default value for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_MASK 0x001D9F1FUL /**< Mask for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_MUX_SHIFT 0 /**< Shift value for LCD_MUX */
|
||||
#define _LCD_DISPCTRL_MUX_MASK 0x3UL /**< Bit mask for LCD_MUX */
|
||||
#define _LCD_DISPCTRL_MUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_MUX_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_MUX_DUPLEX 0x00000001UL /**< Mode DUPLEX for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_MUX_TRIPLEX 0x00000002UL /**< Mode TRIPLEX for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_MUX_QUADRUPLEX 0x00000003UL /**< Mode QUADRUPLEX for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_MUX_DEFAULT (_LCD_DISPCTRL_MUX_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_MUX_STATIC (_LCD_DISPCTRL_MUX_STATIC << 0) /**< Shifted mode STATIC for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_MUX_DUPLEX (_LCD_DISPCTRL_MUX_DUPLEX << 0) /**< Shifted mode DUPLEX for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_MUX_TRIPLEX (_LCD_DISPCTRL_MUX_TRIPLEX << 0) /**< Shifted mode TRIPLEX for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_MUX_QUADRUPLEX (_LCD_DISPCTRL_MUX_QUADRUPLEX << 0) /**< Shifted mode QUADRUPLEX for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_BIAS_SHIFT 2 /**< Shift value for LCD_BIAS */
|
||||
#define _LCD_DISPCTRL_BIAS_MASK 0xCUL /**< Bit mask for LCD_BIAS */
|
||||
#define _LCD_DISPCTRL_BIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_BIAS_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_BIAS_ONEHALF 0x00000001UL /**< Mode ONEHALF for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_BIAS_ONETHIRD 0x00000002UL /**< Mode ONETHIRD for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_BIAS_DEFAULT (_LCD_DISPCTRL_BIAS_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_BIAS_STATIC (_LCD_DISPCTRL_BIAS_STATIC << 2) /**< Shifted mode STATIC for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_BIAS_ONEHALF (_LCD_DISPCTRL_BIAS_ONEHALF << 2) /**< Shifted mode ONEHALF for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_BIAS_ONETHIRD (_LCD_DISPCTRL_BIAS_ONETHIRD << 2) /**< Shifted mode ONETHIRD for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_WAVE (0x1UL << 4) /**< Waveform Selection */
|
||||
#define _LCD_DISPCTRL_WAVE_SHIFT 4 /**< Shift value for LCD_WAVE */
|
||||
#define _LCD_DISPCTRL_WAVE_MASK 0x10UL /**< Bit mask for LCD_WAVE */
|
||||
#define _LCD_DISPCTRL_WAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_WAVE_LOWPOWER 0x00000000UL /**< Mode LOWPOWER for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_WAVE_NORMAL 0x00000001UL /**< Mode NORMAL for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_WAVE_DEFAULT (_LCD_DISPCTRL_WAVE_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_WAVE_LOWPOWER (_LCD_DISPCTRL_WAVE_LOWPOWER << 4) /**< Shifted mode LOWPOWER for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_WAVE_NORMAL (_LCD_DISPCTRL_WAVE_NORMAL << 4) /**< Shifted mode NORMAL for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_CONLEV_SHIFT 8 /**< Shift value for LCD_CONLEV */
|
||||
#define _LCD_DISPCTRL_CONLEV_MASK 0x1F00UL /**< Bit mask for LCD_CONLEV */
|
||||
#define _LCD_DISPCTRL_CONLEV_MIN 0x00000000UL /**< Mode MIN for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_CONLEV_DEFAULT 0x0000001FUL /**< Mode DEFAULT for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_CONLEV_MAX 0x0000001FUL /**< Mode MAX for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_CONLEV_MIN (_LCD_DISPCTRL_CONLEV_MIN << 8) /**< Shifted mode MIN for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_CONLEV_DEFAULT (_LCD_DISPCTRL_CONLEV_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_CONLEV_MAX (_LCD_DISPCTRL_CONLEV_MAX << 8) /**< Shifted mode MAX for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_CONCONF (0x1UL << 15) /**< Contrast Configuration */
|
||||
#define _LCD_DISPCTRL_CONCONF_SHIFT 15 /**< Shift value for LCD_CONCONF */
|
||||
#define _LCD_DISPCTRL_CONCONF_MASK 0x8000UL /**< Bit mask for LCD_CONCONF */
|
||||
#define _LCD_DISPCTRL_CONCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_CONCONF_VLCD 0x00000000UL /**< Mode VLCD for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_CONCONF_GND 0x00000001UL /**< Mode GND for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_CONCONF_DEFAULT (_LCD_DISPCTRL_CONCONF_DEFAULT << 15) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_CONCONF_VLCD (_LCD_DISPCTRL_CONCONF_VLCD << 15) /**< Shifted mode VLCD for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_CONCONF_GND (_LCD_DISPCTRL_CONCONF_GND << 15) /**< Shifted mode GND for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_VLCDSEL (0x1UL << 16) /**< VLCD Selection */
|
||||
#define _LCD_DISPCTRL_VLCDSEL_SHIFT 16 /**< Shift value for LCD_VLCDSEL */
|
||||
#define _LCD_DISPCTRL_VLCDSEL_MASK 0x10000UL /**< Bit mask for LCD_VLCDSEL */
|
||||
#define _LCD_DISPCTRL_VLCDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_VLCDSEL_VDD 0x00000000UL /**< Mode VDD for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_VLCDSEL_VEXTBOOST 0x00000001UL /**< Mode VEXTBOOST for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_VLCDSEL_DEFAULT (_LCD_DISPCTRL_VLCDSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_VLCDSEL_VDD (_LCD_DISPCTRL_VLCDSEL_VDD << 16) /**< Shifted mode VDD for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_VLCDSEL_VEXTBOOST (_LCD_DISPCTRL_VLCDSEL_VEXTBOOST << 16) /**< Shifted mode VEXTBOOST for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_VBLEV_SHIFT 18 /**< Shift value for LCD_VBLEV */
|
||||
#define _LCD_DISPCTRL_VBLEV_MASK 0x1C0000UL /**< Bit mask for LCD_VBLEV */
|
||||
#define _LCD_DISPCTRL_VBLEV_LEVEL0 0x00000000UL /**< Mode LEVEL0 for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_VBLEV_LEVEL1 0x00000001UL /**< Mode LEVEL1 for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_VBLEV_LEVEL2 0x00000002UL /**< Mode LEVEL2 for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_VBLEV_DEFAULT 0x00000003UL /**< Mode DEFAULT for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_VBLEV_LEVEL3 0x00000003UL /**< Mode LEVEL3 for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_VBLEV_LEVEL4 0x00000004UL /**< Mode LEVEL4 for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_VBLEV_LEVEL5 0x00000005UL /**< Mode LEVEL5 for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_VBLEV_LEVEL6 0x00000006UL /**< Mode LEVEL6 for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_VBLEV_LEVEL7 0x00000007UL /**< Mode LEVEL7 for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_VBLEV_LEVEL0 (_LCD_DISPCTRL_VBLEV_LEVEL0 << 18) /**< Shifted mode LEVEL0 for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_VBLEV_LEVEL1 (_LCD_DISPCTRL_VBLEV_LEVEL1 << 18) /**< Shifted mode LEVEL1 for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_VBLEV_LEVEL2 (_LCD_DISPCTRL_VBLEV_LEVEL2 << 18) /**< Shifted mode LEVEL2 for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_VBLEV_DEFAULT (_LCD_DISPCTRL_VBLEV_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_VBLEV_LEVEL3 (_LCD_DISPCTRL_VBLEV_LEVEL3 << 18) /**< Shifted mode LEVEL3 for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_VBLEV_LEVEL4 (_LCD_DISPCTRL_VBLEV_LEVEL4 << 18) /**< Shifted mode LEVEL4 for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_VBLEV_LEVEL5 (_LCD_DISPCTRL_VBLEV_LEVEL5 << 18) /**< Shifted mode LEVEL5 for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_VBLEV_LEVEL6 (_LCD_DISPCTRL_VBLEV_LEVEL6 << 18) /**< Shifted mode LEVEL6 for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_VBLEV_LEVEL7 (_LCD_DISPCTRL_VBLEV_LEVEL7 << 18) /**< Shifted mode LEVEL7 for LCD_DISPCTRL */
|
||||
|
||||
/* Bit fields for LCD SEGEN */
|
||||
#define _LCD_SEGEN_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGEN */
|
||||
#define _LCD_SEGEN_MASK 0x000003FFUL /**< Mask for LCD_SEGEN */
|
||||
#define _LCD_SEGEN_SEGEN_SHIFT 0 /**< Shift value for LCD_SEGEN */
|
||||
#define _LCD_SEGEN_SEGEN_MASK 0x3FFUL /**< Bit mask for LCD_SEGEN */
|
||||
#define _LCD_SEGEN_SEGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGEN */
|
||||
#define LCD_SEGEN_SEGEN_DEFAULT (_LCD_SEGEN_SEGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGEN */
|
||||
|
||||
/* Bit fields for LCD BACTRL */
|
||||
#define _LCD_BACTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_MASK 0x00FF01FFUL /**< Mask for LCD_BACTRL */
|
||||
#define LCD_BACTRL_BLINKEN (0x1UL << 0) /**< Blink Enable */
|
||||
#define _LCD_BACTRL_BLINKEN_SHIFT 0 /**< Shift value for LCD_BLINKEN */
|
||||
#define _LCD_BACTRL_BLINKEN_MASK 0x1UL /**< Bit mask for LCD_BLINKEN */
|
||||
#define _LCD_BACTRL_BLINKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_BLINKEN_DEFAULT (_LCD_BACTRL_BLINKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_BLANK (0x1UL << 1) /**< Blank Display */
|
||||
#define _LCD_BACTRL_BLANK_SHIFT 1 /**< Shift value for LCD_BLANK */
|
||||
#define _LCD_BACTRL_BLANK_MASK 0x2UL /**< Bit mask for LCD_BLANK */
|
||||
#define _LCD_BACTRL_BLANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_BLANK_DEFAULT (_LCD_BACTRL_BLANK_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_AEN (0x1UL << 2) /**< Animation Enable */
|
||||
#define _LCD_BACTRL_AEN_SHIFT 2 /**< Shift value for LCD_AEN */
|
||||
#define _LCD_BACTRL_AEN_MASK 0x4UL /**< Bit mask for LCD_AEN */
|
||||
#define _LCD_BACTRL_AEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_AEN_DEFAULT (_LCD_BACTRL_AEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_AREGASC_SHIFT 3 /**< Shift value for LCD_AREGASC */
|
||||
#define _LCD_BACTRL_AREGASC_MASK 0x18UL /**< Bit mask for LCD_AREGASC */
|
||||
#define _LCD_BACTRL_AREGASC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_AREGASC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_AREGASC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_AREGASC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_AREGASC_DEFAULT (_LCD_BACTRL_AREGASC_DEFAULT << 3) /**< Shifted mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_AREGASC_NOSHIFT (_LCD_BACTRL_AREGASC_NOSHIFT << 3) /**< Shifted mode NOSHIFT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_AREGASC_SHIFTLEFT (_LCD_BACTRL_AREGASC_SHIFTLEFT << 3) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_AREGASC_SHIFTRIGHT (_LCD_BACTRL_AREGASC_SHIFTRIGHT << 3) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_AREGBSC_SHIFT 5 /**< Shift value for LCD_AREGBSC */
|
||||
#define _LCD_BACTRL_AREGBSC_MASK 0x60UL /**< Bit mask for LCD_AREGBSC */
|
||||
#define _LCD_BACTRL_AREGBSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_AREGBSC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_AREGBSC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_AREGBSC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_AREGBSC_DEFAULT (_LCD_BACTRL_AREGBSC_DEFAULT << 5) /**< Shifted mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_AREGBSC_NOSHIFT (_LCD_BACTRL_AREGBSC_NOSHIFT << 5) /**< Shifted mode NOSHIFT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_AREGBSC_SHIFTLEFT (_LCD_BACTRL_AREGBSC_SHIFTLEFT << 5) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_AREGBSC_SHIFTRIGHT (_LCD_BACTRL_AREGBSC_SHIFTRIGHT << 5) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_ALOGSEL (0x1UL << 7) /**< Animate Logic Function Select */
|
||||
#define _LCD_BACTRL_ALOGSEL_SHIFT 7 /**< Shift value for LCD_ALOGSEL */
|
||||
#define _LCD_BACTRL_ALOGSEL_MASK 0x80UL /**< Bit mask for LCD_ALOGSEL */
|
||||
#define _LCD_BACTRL_ALOGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_ALOGSEL_AND 0x00000000UL /**< Mode AND for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_ALOGSEL_OR 0x00000001UL /**< Mode OR for LCD_BACTRL */
|
||||
#define LCD_BACTRL_ALOGSEL_DEFAULT (_LCD_BACTRL_ALOGSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_ALOGSEL_AND (_LCD_BACTRL_ALOGSEL_AND << 7) /**< Shifted mode AND for LCD_BACTRL */
|
||||
#define LCD_BACTRL_ALOGSEL_OR (_LCD_BACTRL_ALOGSEL_OR << 7) /**< Shifted mode OR for LCD_BACTRL */
|
||||
#define LCD_BACTRL_FCEN (0x1UL << 8) /**< Frame Counter Enable */
|
||||
#define _LCD_BACTRL_FCEN_SHIFT 8 /**< Shift value for LCD_FCEN */
|
||||
#define _LCD_BACTRL_FCEN_MASK 0x100UL /**< Bit mask for LCD_FCEN */
|
||||
#define _LCD_BACTRL_FCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_FCEN_DEFAULT (_LCD_BACTRL_FCEN_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_FCPRESC_SHIFT 16 /**< Shift value for LCD_FCPRESC */
|
||||
#define _LCD_BACTRL_FCPRESC_MASK 0x30000UL /**< Bit mask for LCD_FCPRESC */
|
||||
#define _LCD_BACTRL_FCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_FCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_FCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_FCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_FCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LCD_BACTRL */
|
||||
#define LCD_BACTRL_FCPRESC_DEFAULT (_LCD_BACTRL_FCPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_FCPRESC_DIV1 (_LCD_BACTRL_FCPRESC_DIV1 << 16) /**< Shifted mode DIV1 for LCD_BACTRL */
|
||||
#define LCD_BACTRL_FCPRESC_DIV2 (_LCD_BACTRL_FCPRESC_DIV2 << 16) /**< Shifted mode DIV2 for LCD_BACTRL */
|
||||
#define LCD_BACTRL_FCPRESC_DIV4 (_LCD_BACTRL_FCPRESC_DIV4 << 16) /**< Shifted mode DIV4 for LCD_BACTRL */
|
||||
#define LCD_BACTRL_FCPRESC_DIV8 (_LCD_BACTRL_FCPRESC_DIV8 << 16) /**< Shifted mode DIV8 for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_FCTOP_SHIFT 18 /**< Shift value for LCD_FCTOP */
|
||||
#define _LCD_BACTRL_FCTOP_MASK 0xFC0000UL /**< Bit mask for LCD_FCTOP */
|
||||
#define _LCD_BACTRL_FCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_FCTOP_DEFAULT (_LCD_BACTRL_FCTOP_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_BACTRL */
|
||||
|
||||
/* Bit fields for LCD STATUS */
|
||||
#define _LCD_STATUS_RESETVALUE 0x00000000UL /**< Default value for LCD_STATUS */
|
||||
#define _LCD_STATUS_MASK 0x0000010FUL /**< Mask for LCD_STATUS */
|
||||
#define _LCD_STATUS_ASTATE_SHIFT 0 /**< Shift value for LCD_ASTATE */
|
||||
#define _LCD_STATUS_ASTATE_MASK 0xFUL /**< Bit mask for LCD_ASTATE */
|
||||
#define _LCD_STATUS_ASTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */
|
||||
#define LCD_STATUS_ASTATE_DEFAULT (_LCD_STATUS_ASTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_STATUS */
|
||||
#define LCD_STATUS_BLINK (0x1UL << 8) /**< Blink State */
|
||||
#define _LCD_STATUS_BLINK_SHIFT 8 /**< Shift value for LCD_BLINK */
|
||||
#define _LCD_STATUS_BLINK_MASK 0x100UL /**< Bit mask for LCD_BLINK */
|
||||
#define _LCD_STATUS_BLINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */
|
||||
#define LCD_STATUS_BLINK_DEFAULT (_LCD_STATUS_BLINK_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_STATUS */
|
||||
|
||||
/* Bit fields for LCD AREGA */
|
||||
#define _LCD_AREGA_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGA */
|
||||
#define _LCD_AREGA_MASK 0x000000FFUL /**< Mask for LCD_AREGA */
|
||||
#define _LCD_AREGA_AREGA_SHIFT 0 /**< Shift value for LCD_AREGA */
|
||||
#define _LCD_AREGA_AREGA_MASK 0xFFUL /**< Bit mask for LCD_AREGA */
|
||||
#define _LCD_AREGA_AREGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGA */
|
||||
#define LCD_AREGA_AREGA_DEFAULT (_LCD_AREGA_AREGA_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_AREGA */
|
||||
|
||||
/* Bit fields for LCD AREGB */
|
||||
#define _LCD_AREGB_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGB */
|
||||
#define _LCD_AREGB_MASK 0x000000FFUL /**< Mask for LCD_AREGB */
|
||||
#define _LCD_AREGB_AREGB_SHIFT 0 /**< Shift value for LCD_AREGB */
|
||||
#define _LCD_AREGB_AREGB_MASK 0xFFUL /**< Bit mask for LCD_AREGB */
|
||||
#define _LCD_AREGB_AREGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGB */
|
||||
#define LCD_AREGB_AREGB_DEFAULT (_LCD_AREGB_AREGB_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_AREGB */
|
||||
|
||||
/* Bit fields for LCD IF */
|
||||
#define _LCD_IF_RESETVALUE 0x00000000UL /**< Default value for LCD_IF */
|
||||
#define _LCD_IF_MASK 0x00000001UL /**< Mask for LCD_IF */
|
||||
#define LCD_IF_FC (0x1UL << 0) /**< Frame Counter Interrupt Flag */
|
||||
#define _LCD_IF_FC_SHIFT 0 /**< Shift value for LCD_FC */
|
||||
#define _LCD_IF_FC_MASK 0x1UL /**< Bit mask for LCD_FC */
|
||||
#define _LCD_IF_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IF */
|
||||
#define LCD_IF_FC_DEFAULT (_LCD_IF_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IF */
|
||||
|
||||
/* Bit fields for LCD IFS */
|
||||
#define _LCD_IFS_RESETVALUE 0x00000000UL /**< Default value for LCD_IFS */
|
||||
#define _LCD_IFS_MASK 0x00000001UL /**< Mask for LCD_IFS */
|
||||
#define LCD_IFS_FC (0x1UL << 0) /**< Frame Counter Interrupt Flag Set */
|
||||
#define _LCD_IFS_FC_SHIFT 0 /**< Shift value for LCD_FC */
|
||||
#define _LCD_IFS_FC_MASK 0x1UL /**< Bit mask for LCD_FC */
|
||||
#define _LCD_IFS_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IFS */
|
||||
#define LCD_IFS_FC_DEFAULT (_LCD_IFS_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IFS */
|
||||
|
||||
/* Bit fields for LCD IFC */
|
||||
#define _LCD_IFC_RESETVALUE 0x00000000UL /**< Default value for LCD_IFC */
|
||||
#define _LCD_IFC_MASK 0x00000001UL /**< Mask for LCD_IFC */
|
||||
#define LCD_IFC_FC (0x1UL << 0) /**< Frame Counter Interrupt Flag Clear */
|
||||
#define _LCD_IFC_FC_SHIFT 0 /**< Shift value for LCD_FC */
|
||||
#define _LCD_IFC_FC_MASK 0x1UL /**< Bit mask for LCD_FC */
|
||||
#define _LCD_IFC_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IFC */
|
||||
#define LCD_IFC_FC_DEFAULT (_LCD_IFC_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IFC */
|
||||
|
||||
/* Bit fields for LCD IEN */
|
||||
#define _LCD_IEN_RESETVALUE 0x00000000UL /**< Default value for LCD_IEN */
|
||||
#define _LCD_IEN_MASK 0x00000001UL /**< Mask for LCD_IEN */
|
||||
#define LCD_IEN_FC (0x1UL << 0) /**< Frame Counter Interrupt Enable */
|
||||
#define _LCD_IEN_FC_SHIFT 0 /**< Shift value for LCD_FC */
|
||||
#define _LCD_IEN_FC_MASK 0x1UL /**< Bit mask for LCD_FC */
|
||||
#define _LCD_IEN_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IEN */
|
||||
#define LCD_IEN_FC_DEFAULT (_LCD_IEN_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IEN */
|
||||
|
||||
/* Bit fields for LCD SEGD0L */
|
||||
#define _LCD_SEGD0L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD0L */
|
||||
#define _LCD_SEGD0L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD0L */
|
||||
#define _LCD_SEGD0L_SEGD0L_SHIFT 0 /**< Shift value for LCD_SEGD0L */
|
||||
#define _LCD_SEGD0L_SEGD0L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD0L */
|
||||
#define _LCD_SEGD0L_SEGD0L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD0L */
|
||||
#define LCD_SEGD0L_SEGD0L_DEFAULT (_LCD_SEGD0L_SEGD0L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD0L */
|
||||
|
||||
/* Bit fields for LCD SEGD1L */
|
||||
#define _LCD_SEGD1L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD1L */
|
||||
#define _LCD_SEGD1L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD1L */
|
||||
#define _LCD_SEGD1L_SEGD1L_SHIFT 0 /**< Shift value for LCD_SEGD1L */
|
||||
#define _LCD_SEGD1L_SEGD1L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD1L */
|
||||
#define _LCD_SEGD1L_SEGD1L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD1L */
|
||||
#define LCD_SEGD1L_SEGD1L_DEFAULT (_LCD_SEGD1L_SEGD1L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD1L */
|
||||
|
||||
/* Bit fields for LCD SEGD2L */
|
||||
#define _LCD_SEGD2L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD2L */
|
||||
#define _LCD_SEGD2L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD2L */
|
||||
#define _LCD_SEGD2L_SEGD2L_SHIFT 0 /**< Shift value for LCD_SEGD2L */
|
||||
#define _LCD_SEGD2L_SEGD2L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD2L */
|
||||
#define _LCD_SEGD2L_SEGD2L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD2L */
|
||||
#define LCD_SEGD2L_SEGD2L_DEFAULT (_LCD_SEGD2L_SEGD2L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD2L */
|
||||
|
||||
/* Bit fields for LCD SEGD3L */
|
||||
#define _LCD_SEGD3L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD3L */
|
||||
#define _LCD_SEGD3L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD3L */
|
||||
#define _LCD_SEGD3L_SEGD3L_SHIFT 0 /**< Shift value for LCD_SEGD3L */
|
||||
#define _LCD_SEGD3L_SEGD3L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD3L */
|
||||
#define _LCD_SEGD3L_SEGD3L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD3L */
|
||||
#define LCD_SEGD3L_SEGD3L_DEFAULT (_LCD_SEGD3L_SEGD3L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD3L */
|
||||
|
||||
/* Bit fields for LCD SEGD0H */
|
||||
#define _LCD_SEGD0H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD0H */
|
||||
#define _LCD_SEGD0H_MASK 0x000000FFUL /**< Mask for LCD_SEGD0H */
|
||||
#define _LCD_SEGD0H_SEGD0H_SHIFT 0 /**< Shift value for LCD_SEGD0H */
|
||||
#define _LCD_SEGD0H_SEGD0H_MASK 0xFFUL /**< Bit mask for LCD_SEGD0H */
|
||||
#define _LCD_SEGD0H_SEGD0H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD0H */
|
||||
#define LCD_SEGD0H_SEGD0H_DEFAULT (_LCD_SEGD0H_SEGD0H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD0H */
|
||||
|
||||
/* Bit fields for LCD SEGD1H */
|
||||
#define _LCD_SEGD1H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD1H */
|
||||
#define _LCD_SEGD1H_MASK 0x000000FFUL /**< Mask for LCD_SEGD1H */
|
||||
#define _LCD_SEGD1H_SEGD1H_SHIFT 0 /**< Shift value for LCD_SEGD1H */
|
||||
#define _LCD_SEGD1H_SEGD1H_MASK 0xFFUL /**< Bit mask for LCD_SEGD1H */
|
||||
#define _LCD_SEGD1H_SEGD1H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD1H */
|
||||
#define LCD_SEGD1H_SEGD1H_DEFAULT (_LCD_SEGD1H_SEGD1H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD1H */
|
||||
|
||||
/* Bit fields for LCD SEGD2H */
|
||||
#define _LCD_SEGD2H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD2H */
|
||||
#define _LCD_SEGD2H_MASK 0x000000FFUL /**< Mask for LCD_SEGD2H */
|
||||
#define _LCD_SEGD2H_SEGD2H_SHIFT 0 /**< Shift value for LCD_SEGD2H */
|
||||
#define _LCD_SEGD2H_SEGD2H_MASK 0xFFUL /**< Bit mask for LCD_SEGD2H */
|
||||
#define _LCD_SEGD2H_SEGD2H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD2H */
|
||||
#define LCD_SEGD2H_SEGD2H_DEFAULT (_LCD_SEGD2H_SEGD2H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD2H */
|
||||
|
||||
/* Bit fields for LCD SEGD3H */
|
||||
#define _LCD_SEGD3H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD3H */
|
||||
#define _LCD_SEGD3H_MASK 0x000000FFUL /**< Mask for LCD_SEGD3H */
|
||||
#define _LCD_SEGD3H_SEGD3H_SHIFT 0 /**< Shift value for LCD_SEGD3H */
|
||||
#define _LCD_SEGD3H_SEGD3H_MASK 0xFFUL /**< Bit mask for LCD_SEGD3H */
|
||||
#define _LCD_SEGD3H_SEGD3H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD3H */
|
||||
#define LCD_SEGD3H_SEGD3H_DEFAULT (_LCD_SEGD3H_SEGD3H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD3H */
|
||||
|
||||
/* Bit fields for LCD FREEZE */
|
||||
#define _LCD_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LCD_FREEZE */
|
||||
#define _LCD_FREEZE_MASK 0x00000001UL /**< Mask for LCD_FREEZE */
|
||||
#define LCD_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
|
||||
#define _LCD_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LCD_REGFREEZE */
|
||||
#define _LCD_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LCD_REGFREEZE */
|
||||
#define _LCD_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_FREEZE */
|
||||
#define _LCD_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LCD_FREEZE */
|
||||
#define _LCD_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LCD_FREEZE */
|
||||
#define LCD_FREEZE_REGFREEZE_DEFAULT (_LCD_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_FREEZE */
|
||||
#define LCD_FREEZE_REGFREEZE_UPDATE (_LCD_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for LCD_FREEZE */
|
||||
#define LCD_FREEZE_REGFREEZE_FREEZE (_LCD_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for LCD_FREEZE */
|
||||
|
||||
/* Bit fields for LCD SYNCBUSY */
|
||||
#define _LCD_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LCD_SYNCBUSY */
|
||||
#define _LCD_SYNCBUSY_MASK 0x00000FFFUL /**< Mask for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_CTRL (0x1UL << 0) /**< LCD_CTRL Register Busy */
|
||||
#define _LCD_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LCD_CTRL */
|
||||
#define _LCD_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LCD_CTRL */
|
||||
#define _LCD_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_CTRL_DEFAULT (_LCD_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_BACTRL (0x1UL << 1) /**< LCD_BACTRL Register Busy */
|
||||
#define _LCD_SYNCBUSY_BACTRL_SHIFT 1 /**< Shift value for LCD_BACTRL */
|
||||
#define _LCD_SYNCBUSY_BACTRL_MASK 0x2UL /**< Bit mask for LCD_BACTRL */
|
||||
#define _LCD_SYNCBUSY_BACTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_BACTRL_DEFAULT (_LCD_SYNCBUSY_BACTRL_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_AREGA (0x1UL << 2) /**< LCD_AREGA Register Busy */
|
||||
#define _LCD_SYNCBUSY_AREGA_SHIFT 2 /**< Shift value for LCD_AREGA */
|
||||
#define _LCD_SYNCBUSY_AREGA_MASK 0x4UL /**< Bit mask for LCD_AREGA */
|
||||
#define _LCD_SYNCBUSY_AREGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_AREGA_DEFAULT (_LCD_SYNCBUSY_AREGA_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_AREGB (0x1UL << 3) /**< LCD_AREGB Register Busy */
|
||||
#define _LCD_SYNCBUSY_AREGB_SHIFT 3 /**< Shift value for LCD_AREGB */
|
||||
#define _LCD_SYNCBUSY_AREGB_MASK 0x8UL /**< Bit mask for LCD_AREGB */
|
||||
#define _LCD_SYNCBUSY_AREGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_AREGB_DEFAULT (_LCD_SYNCBUSY_AREGB_DEFAULT << 3) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD0L (0x1UL << 4) /**< LCD_SEGD0L Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD0L_SHIFT 4 /**< Shift value for LCD_SEGD0L */
|
||||
#define _LCD_SYNCBUSY_SEGD0L_MASK 0x10UL /**< Bit mask for LCD_SEGD0L */
|
||||
#define _LCD_SYNCBUSY_SEGD0L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD0L_DEFAULT (_LCD_SYNCBUSY_SEGD0L_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD1L (0x1UL << 5) /**< LCD_SEGD1L Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD1L_SHIFT 5 /**< Shift value for LCD_SEGD1L */
|
||||
#define _LCD_SYNCBUSY_SEGD1L_MASK 0x20UL /**< Bit mask for LCD_SEGD1L */
|
||||
#define _LCD_SYNCBUSY_SEGD1L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD1L_DEFAULT (_LCD_SYNCBUSY_SEGD1L_DEFAULT << 5) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD2L (0x1UL << 6) /**< LCD_SEGD2L Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD2L_SHIFT 6 /**< Shift value for LCD_SEGD2L */
|
||||
#define _LCD_SYNCBUSY_SEGD2L_MASK 0x40UL /**< Bit mask for LCD_SEGD2L */
|
||||
#define _LCD_SYNCBUSY_SEGD2L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD2L_DEFAULT (_LCD_SYNCBUSY_SEGD2L_DEFAULT << 6) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD3L (0x1UL << 7) /**< LCD_SEGD3L Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD3L_SHIFT 7 /**< Shift value for LCD_SEGD3L */
|
||||
#define _LCD_SYNCBUSY_SEGD3L_MASK 0x80UL /**< Bit mask for LCD_SEGD3L */
|
||||
#define _LCD_SYNCBUSY_SEGD3L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD3L_DEFAULT (_LCD_SYNCBUSY_SEGD3L_DEFAULT << 7) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD0H (0x1UL << 8) /**< LCD_SEGD0H Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD0H_SHIFT 8 /**< Shift value for LCD_SEGD0H */
|
||||
#define _LCD_SYNCBUSY_SEGD0H_MASK 0x100UL /**< Bit mask for LCD_SEGD0H */
|
||||
#define _LCD_SYNCBUSY_SEGD0H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD0H_DEFAULT (_LCD_SYNCBUSY_SEGD0H_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD1H (0x1UL << 9) /**< LCD_SEGD1H Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD1H_SHIFT 9 /**< Shift value for LCD_SEGD1H */
|
||||
#define _LCD_SYNCBUSY_SEGD1H_MASK 0x200UL /**< Bit mask for LCD_SEGD1H */
|
||||
#define _LCD_SYNCBUSY_SEGD1H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD1H_DEFAULT (_LCD_SYNCBUSY_SEGD1H_DEFAULT << 9) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD2H (0x1UL << 10) /**< LCD_SEGD2H Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD2H_SHIFT 10 /**< Shift value for LCD_SEGD2H */
|
||||
#define _LCD_SYNCBUSY_SEGD2H_MASK 0x400UL /**< Bit mask for LCD_SEGD2H */
|
||||
#define _LCD_SYNCBUSY_SEGD2H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD2H_DEFAULT (_LCD_SYNCBUSY_SEGD2H_DEFAULT << 10) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD3H (0x1UL << 11) /**< LCD_SEGD3H Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD3H_SHIFT 11 /**< Shift value for LCD_SEGD3H */
|
||||
#define _LCD_SYNCBUSY_SEGD3H_MASK 0x800UL /**< Bit mask for LCD_SEGD3H */
|
||||
#define _LCD_SYNCBUSY_SEGD3H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD3H_DEFAULT (_LCD_SYNCBUSY_SEGD3H_DEFAULT << 11) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
|
||||
/** @} End of group EFM32G_LCD */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,409 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief efm32g_letimer Register and Bit Field definitions
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_LETIMER
|
||||
* @{
|
||||
* @brief EFM32G_LETIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__IO uint32_t CMD; /**< Command Register */
|
||||
__I uint32_t STATUS; /**< Status Register */
|
||||
__I uint32_t CNT; /**< Counter Value Register */
|
||||
__IO uint32_t COMP0; /**< Compare Value Register 0 */
|
||||
__IO uint32_t COMP1; /**< Compare Value Register 1 */
|
||||
__IO uint32_t REP0; /**< Repeat Counter Register 0 */
|
||||
__IO uint32_t REP1; /**< Repeat Counter Register 1 */
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
|
||||
__IO uint32_t FREEZE; /**< Freeze Register */
|
||||
__I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
|
||||
uint32_t RESERVED0[2]; /**< Reserved for future use **/
|
||||
__IO uint32_t ROUTE; /**< I/O Routing Register */
|
||||
} LETIMER_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_LETIMER_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/* Bit fields for LETIMER CTRL */
|
||||
#define _LETIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CTRL */
|
||||
#define _LETIMER_CTRL_MASK 0x00001FFFUL /**< Mask for LETIMER_CTRL */
|
||||
#define _LETIMER_CTRL_REPMODE_SHIFT 0 /**< Shift value for LETIMER_REPMODE */
|
||||
#define _LETIMER_CTRL_REPMODE_MASK 0x3UL /**< Bit mask for LETIMER_REPMODE */
|
||||
#define _LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
|
||||
#define _LETIMER_CTRL_REPMODE_FREE 0x00000000UL /**< Mode FREE for LETIMER_CTRL */
|
||||
#define _LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LETIMER_CTRL */
|
||||
#define _LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL /**< Mode BUFFERED for LETIMER_CTRL */
|
||||
#define _LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL /**< Mode DOUBLE for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_REPMODE_DEFAULT (_LETIMER_CTRL_REPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_REPMODE_FREE (_LETIMER_CTRL_REPMODE_FREE << 0) /**< Shifted mode FREE for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_REPMODE_ONESHOT (_LETIMER_CTRL_REPMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_REPMODE_BUFFERED (_LETIMER_CTRL_REPMODE_BUFFERED << 0) /**< Shifted mode BUFFERED for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_REPMODE_DOUBLE (_LETIMER_CTRL_REPMODE_DOUBLE << 0) /**< Shifted mode DOUBLE for LETIMER_CTRL */
|
||||
#define _LETIMER_CTRL_UFOA0_SHIFT 2 /**< Shift value for LETIMER_UFOA0 */
|
||||
#define _LETIMER_CTRL_UFOA0_MASK 0xCUL /**< Bit mask for LETIMER_UFOA0 */
|
||||
#define _LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
|
||||
#define _LETIMER_CTRL_UFOA0_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */
|
||||
#define _LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */
|
||||
#define _LETIMER_CTRL_UFOA0_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */
|
||||
#define _LETIMER_CTRL_UFOA0_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_UFOA0_DEFAULT (_LETIMER_CTRL_UFOA0_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_UFOA0_NONE (_LETIMER_CTRL_UFOA0_NONE << 2) /**< Shifted mode NONE for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_UFOA0_TOGGLE (_LETIMER_CTRL_UFOA0_TOGGLE << 2) /**< Shifted mode TOGGLE for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_UFOA0_PULSE (_LETIMER_CTRL_UFOA0_PULSE << 2) /**< Shifted mode PULSE for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_UFOA0_PWM (_LETIMER_CTRL_UFOA0_PWM << 2) /**< Shifted mode PWM for LETIMER_CTRL */
|
||||
#define _LETIMER_CTRL_UFOA1_SHIFT 4 /**< Shift value for LETIMER_UFOA1 */
|
||||
#define _LETIMER_CTRL_UFOA1_MASK 0x30UL /**< Bit mask for LETIMER_UFOA1 */
|
||||
#define _LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
|
||||
#define _LETIMER_CTRL_UFOA1_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */
|
||||
#define _LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */
|
||||
#define _LETIMER_CTRL_UFOA1_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */
|
||||
#define _LETIMER_CTRL_UFOA1_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_UFOA1_DEFAULT (_LETIMER_CTRL_UFOA1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_UFOA1_NONE (_LETIMER_CTRL_UFOA1_NONE << 4) /**< Shifted mode NONE for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_UFOA1_TOGGLE (_LETIMER_CTRL_UFOA1_TOGGLE << 4) /**< Shifted mode TOGGLE for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_UFOA1_PULSE (_LETIMER_CTRL_UFOA1_PULSE << 4) /**< Shifted mode PULSE for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_UFOA1_PWM (_LETIMER_CTRL_UFOA1_PWM << 4) /**< Shifted mode PWM for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_OPOL0 (0x1UL << 6) /**< Output 0 Polarity */
|
||||
#define _LETIMER_CTRL_OPOL0_SHIFT 6 /**< Shift value for LETIMER_OPOL0 */
|
||||
#define _LETIMER_CTRL_OPOL0_MASK 0x40UL /**< Bit mask for LETIMER_OPOL0 */
|
||||
#define _LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_OPOL0_DEFAULT (_LETIMER_CTRL_OPOL0_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_OPOL1 (0x1UL << 7) /**< Output 1 Polarity */
|
||||
#define _LETIMER_CTRL_OPOL1_SHIFT 7 /**< Shift value for LETIMER_OPOL1 */
|
||||
#define _LETIMER_CTRL_OPOL1_MASK 0x80UL /**< Bit mask for LETIMER_OPOL1 */
|
||||
#define _LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_OPOL1_DEFAULT (_LETIMER_CTRL_OPOL1_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_BUFTOP (0x1UL << 8) /**< Buffered Top */
|
||||
#define _LETIMER_CTRL_BUFTOP_SHIFT 8 /**< Shift value for LETIMER_BUFTOP */
|
||||
#define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /**< Bit mask for LETIMER_BUFTOP */
|
||||
#define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_COMP0TOP (0x1UL << 9) /**< Compare Value 0 Is Top Value */
|
||||
#define _LETIMER_CTRL_COMP0TOP_SHIFT 9 /**< Shift value for LETIMER_COMP0TOP */
|
||||
#define _LETIMER_CTRL_COMP0TOP_MASK 0x200UL /**< Bit mask for LETIMER_COMP0TOP */
|
||||
#define _LETIMER_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_COMP0TOP_DEFAULT (_LETIMER_CTRL_COMP0TOP_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_RTCC0TEN (0x1UL << 10) /**< RTC Compare 0 Trigger Enable */
|
||||
#define _LETIMER_CTRL_RTCC0TEN_SHIFT 10 /**< Shift value for LETIMER_RTCC0TEN */
|
||||
#define _LETIMER_CTRL_RTCC0TEN_MASK 0x400UL /**< Bit mask for LETIMER_RTCC0TEN */
|
||||
#define _LETIMER_CTRL_RTCC0TEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_RTCC0TEN_DEFAULT (_LETIMER_CTRL_RTCC0TEN_DEFAULT << 10) /**< Shifted mode DEFAULT for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_RTCC1TEN (0x1UL << 11) /**< RTC Compare 1 Trigger Enable */
|
||||
#define _LETIMER_CTRL_RTCC1TEN_SHIFT 11 /**< Shift value for LETIMER_RTCC1TEN */
|
||||
#define _LETIMER_CTRL_RTCC1TEN_MASK 0x800UL /**< Bit mask for LETIMER_RTCC1TEN */
|
||||
#define _LETIMER_CTRL_RTCC1TEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_RTCC1TEN_DEFAULT (_LETIMER_CTRL_RTCC1TEN_DEFAULT << 11) /**< Shifted mode DEFAULT for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_DEBUGRUN (0x1UL << 12) /**< Debug Mode Run Enable */
|
||||
#define _LETIMER_CTRL_DEBUGRUN_SHIFT 12 /**< Shift value for LETIMER_DEBUGRUN */
|
||||
#define _LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL /**< Bit mask for LETIMER_DEBUGRUN */
|
||||
#define _LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_DEBUGRUN_DEFAULT (_LETIMER_CTRL_DEBUGRUN_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_CTRL */
|
||||
|
||||
/* Bit fields for LETIMER CMD */
|
||||
#define _LETIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CMD */
|
||||
#define _LETIMER_CMD_MASK 0x0000001FUL /**< Mask for LETIMER_CMD */
|
||||
#define LETIMER_CMD_START (0x1UL << 0) /**< Start LETIMER */
|
||||
#define _LETIMER_CMD_START_SHIFT 0 /**< Shift value for LETIMER_START */
|
||||
#define _LETIMER_CMD_START_MASK 0x1UL /**< Bit mask for LETIMER_START */
|
||||
#define _LETIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
|
||||
#define LETIMER_CMD_START_DEFAULT (_LETIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CMD */
|
||||
#define LETIMER_CMD_STOP (0x1UL << 1) /**< Stop LETIMER */
|
||||
#define _LETIMER_CMD_STOP_SHIFT 1 /**< Shift value for LETIMER_STOP */
|
||||
#define _LETIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for LETIMER_STOP */
|
||||
#define _LETIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
|
||||
#define LETIMER_CMD_STOP_DEFAULT (_LETIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_CMD */
|
||||
#define LETIMER_CMD_CLEAR (0x1UL << 2) /**< Clear LETIMER */
|
||||
#define _LETIMER_CMD_CLEAR_SHIFT 2 /**< Shift value for LETIMER_CLEAR */
|
||||
#define _LETIMER_CMD_CLEAR_MASK 0x4UL /**< Bit mask for LETIMER_CLEAR */
|
||||
#define _LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
|
||||
#define LETIMER_CMD_CLEAR_DEFAULT (_LETIMER_CMD_CLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CMD */
|
||||
#define LETIMER_CMD_CTO0 (0x1UL << 3) /**< Clear Toggle Output 0 */
|
||||
#define _LETIMER_CMD_CTO0_SHIFT 3 /**< Shift value for LETIMER_CTO0 */
|
||||
#define _LETIMER_CMD_CTO0_MASK 0x8UL /**< Bit mask for LETIMER_CTO0 */
|
||||
#define _LETIMER_CMD_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
|
||||
#define LETIMER_CMD_CTO0_DEFAULT (_LETIMER_CMD_CTO0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_CMD */
|
||||
#define LETIMER_CMD_CTO1 (0x1UL << 4) /**< Clear Toggle Output 1 */
|
||||
#define _LETIMER_CMD_CTO1_SHIFT 4 /**< Shift value for LETIMER_CTO1 */
|
||||
#define _LETIMER_CMD_CTO1_MASK 0x10UL /**< Bit mask for LETIMER_CTO1 */
|
||||
#define _LETIMER_CMD_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
|
||||
#define LETIMER_CMD_CTO1_DEFAULT (_LETIMER_CMD_CTO1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CMD */
|
||||
|
||||
/* Bit fields for LETIMER STATUS */
|
||||
#define _LETIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_STATUS */
|
||||
#define _LETIMER_STATUS_MASK 0x00000001UL /**< Mask for LETIMER_STATUS */
|
||||
#define LETIMER_STATUS_RUNNING (0x1UL << 0) /**< LETIMER Running */
|
||||
#define _LETIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for LETIMER_RUNNING */
|
||||
#define _LETIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for LETIMER_RUNNING */
|
||||
#define _LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */
|
||||
#define LETIMER_STATUS_RUNNING_DEFAULT (_LETIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_STATUS */
|
||||
|
||||
/* Bit fields for LETIMER CNT */
|
||||
#define _LETIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CNT */
|
||||
#define _LETIMER_CNT_MASK 0x0000FFFFUL /**< Mask for LETIMER_CNT */
|
||||
#define _LETIMER_CNT_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */
|
||||
#define _LETIMER_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for LETIMER_CNT */
|
||||
#define _LETIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CNT */
|
||||
#define LETIMER_CNT_CNT_DEFAULT (_LETIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CNT */
|
||||
|
||||
/* Bit fields for LETIMER COMP0 */
|
||||
#define _LETIMER_COMP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP0 */
|
||||
#define _LETIMER_COMP0_MASK 0x0000FFFFUL /**< Mask for LETIMER_COMP0 */
|
||||
#define _LETIMER_COMP0_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
|
||||
#define _LETIMER_COMP0_COMP0_MASK 0xFFFFUL /**< Bit mask for LETIMER_COMP0 */
|
||||
#define _LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP0 */
|
||||
#define LETIMER_COMP0_COMP0_DEFAULT (_LETIMER_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP0 */
|
||||
|
||||
/* Bit fields for LETIMER COMP1 */
|
||||
#define _LETIMER_COMP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP1 */
|
||||
#define _LETIMER_COMP1_MASK 0x0000FFFFUL /**< Mask for LETIMER_COMP1 */
|
||||
#define _LETIMER_COMP1_COMP1_SHIFT 0 /**< Shift value for LETIMER_COMP1 */
|
||||
#define _LETIMER_COMP1_COMP1_MASK 0xFFFFUL /**< Bit mask for LETIMER_COMP1 */
|
||||
#define _LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP1 */
|
||||
#define LETIMER_COMP1_COMP1_DEFAULT (_LETIMER_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP1 */
|
||||
|
||||
/* Bit fields for LETIMER REP0 */
|
||||
#define _LETIMER_REP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP0 */
|
||||
#define _LETIMER_REP0_MASK 0x000000FFUL /**< Mask for LETIMER_REP0 */
|
||||
#define _LETIMER_REP0_REP0_SHIFT 0 /**< Shift value for LETIMER_REP0 */
|
||||
#define _LETIMER_REP0_REP0_MASK 0xFFUL /**< Bit mask for LETIMER_REP0 */
|
||||
#define _LETIMER_REP0_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP0 */
|
||||
#define LETIMER_REP0_REP0_DEFAULT (_LETIMER_REP0_REP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP0 */
|
||||
|
||||
/* Bit fields for LETIMER REP1 */
|
||||
#define _LETIMER_REP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP1 */
|
||||
#define _LETIMER_REP1_MASK 0x000000FFUL /**< Mask for LETIMER_REP1 */
|
||||
#define _LETIMER_REP1_REP1_SHIFT 0 /**< Shift value for LETIMER_REP1 */
|
||||
#define _LETIMER_REP1_REP1_MASK 0xFFUL /**< Bit mask for LETIMER_REP1 */
|
||||
#define _LETIMER_REP1_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP1 */
|
||||
#define LETIMER_REP1_REP1_DEFAULT (_LETIMER_REP1_REP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP1 */
|
||||
|
||||
/* Bit fields for LETIMER IF */
|
||||
#define _LETIMER_IF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IF */
|
||||
#define _LETIMER_IF_MASK 0x0000001FUL /**< Mask for LETIMER_IF */
|
||||
#define LETIMER_IF_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Flag */
|
||||
#define _LETIMER_IF_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
|
||||
#define _LETIMER_IF_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */
|
||||
#define _LETIMER_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
|
||||
#define LETIMER_IF_COMP0_DEFAULT (_LETIMER_IF_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IF */
|
||||
#define LETIMER_IF_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Flag */
|
||||
#define _LETIMER_IF_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */
|
||||
#define _LETIMER_IF_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */
|
||||
#define _LETIMER_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
|
||||
#define LETIMER_IF_COMP1_DEFAULT (_LETIMER_IF_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IF */
|
||||
#define LETIMER_IF_UF (0x1UL << 2) /**< Underflow Interrupt Flag */
|
||||
#define _LETIMER_IF_UF_SHIFT 2 /**< Shift value for LETIMER_UF */
|
||||
#define _LETIMER_IF_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */
|
||||
#define _LETIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
|
||||
#define LETIMER_IF_UF_DEFAULT (_LETIMER_IF_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IF */
|
||||
#define LETIMER_IF_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Flag */
|
||||
#define _LETIMER_IF_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */
|
||||
#define _LETIMER_IF_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */
|
||||
#define _LETIMER_IF_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
|
||||
#define LETIMER_IF_REP0_DEFAULT (_LETIMER_IF_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IF */
|
||||
#define LETIMER_IF_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Flag */
|
||||
#define _LETIMER_IF_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */
|
||||
#define _LETIMER_IF_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */
|
||||
#define _LETIMER_IF_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
|
||||
#define LETIMER_IF_REP1_DEFAULT (_LETIMER_IF_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IF */
|
||||
|
||||
/* Bit fields for LETIMER IFS */
|
||||
#define _LETIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IFS */
|
||||
#define _LETIMER_IFS_MASK 0x0000001FUL /**< Mask for LETIMER_IFS */
|
||||
#define LETIMER_IFS_COMP0 (0x1UL << 0) /**< Set Compare Match 0 Interrupt Flag */
|
||||
#define _LETIMER_IFS_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
|
||||
#define _LETIMER_IFS_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */
|
||||
#define _LETIMER_IFS_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */
|
||||
#define LETIMER_IFS_COMP0_DEFAULT (_LETIMER_IFS_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IFS */
|
||||
#define LETIMER_IFS_COMP1 (0x1UL << 1) /**< Set Compare Match 1 Interrupt Flag */
|
||||
#define _LETIMER_IFS_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */
|
||||
#define _LETIMER_IFS_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */
|
||||
#define _LETIMER_IFS_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */
|
||||
#define LETIMER_IFS_COMP1_DEFAULT (_LETIMER_IFS_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IFS */
|
||||
#define LETIMER_IFS_UF (0x1UL << 2) /**< Set Underflow Interrupt Flag */
|
||||
#define _LETIMER_IFS_UF_SHIFT 2 /**< Shift value for LETIMER_UF */
|
||||
#define _LETIMER_IFS_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */
|
||||
#define _LETIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */
|
||||
#define LETIMER_IFS_UF_DEFAULT (_LETIMER_IFS_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IFS */
|
||||
#define LETIMER_IFS_REP0 (0x1UL << 3) /**< Set Repeat Counter 0 Interrupt Flag */
|
||||
#define _LETIMER_IFS_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */
|
||||
#define _LETIMER_IFS_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */
|
||||
#define _LETIMER_IFS_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */
|
||||
#define LETIMER_IFS_REP0_DEFAULT (_LETIMER_IFS_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IFS */
|
||||
#define LETIMER_IFS_REP1 (0x1UL << 4) /**< Set Repeat Counter 1 Interrupt Flag */
|
||||
#define _LETIMER_IFS_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */
|
||||
#define _LETIMER_IFS_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */
|
||||
#define _LETIMER_IFS_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */
|
||||
#define LETIMER_IFS_REP1_DEFAULT (_LETIMER_IFS_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IFS */
|
||||
|
||||
/* Bit fields for LETIMER IFC */
|
||||
#define _LETIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IFC */
|
||||
#define _LETIMER_IFC_MASK 0x0000001FUL /**< Mask for LETIMER_IFC */
|
||||
#define LETIMER_IFC_COMP0 (0x1UL << 0) /**< Clear Compare Match 0 Interrupt Flag */
|
||||
#define _LETIMER_IFC_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
|
||||
#define _LETIMER_IFC_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */
|
||||
#define _LETIMER_IFC_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */
|
||||
#define LETIMER_IFC_COMP0_DEFAULT (_LETIMER_IFC_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IFC */
|
||||
#define LETIMER_IFC_COMP1 (0x1UL << 1) /**< Clear Compare Match 1 Interrupt Flag */
|
||||
#define _LETIMER_IFC_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */
|
||||
#define _LETIMER_IFC_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */
|
||||
#define _LETIMER_IFC_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */
|
||||
#define LETIMER_IFC_COMP1_DEFAULT (_LETIMER_IFC_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IFC */
|
||||
#define LETIMER_IFC_UF (0x1UL << 2) /**< Clear Underflow Interrupt Flag */
|
||||
#define _LETIMER_IFC_UF_SHIFT 2 /**< Shift value for LETIMER_UF */
|
||||
#define _LETIMER_IFC_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */
|
||||
#define _LETIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */
|
||||
#define LETIMER_IFC_UF_DEFAULT (_LETIMER_IFC_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IFC */
|
||||
#define LETIMER_IFC_REP0 (0x1UL << 3) /**< Clear Repeat Counter 0 Interrupt Flag */
|
||||
#define _LETIMER_IFC_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */
|
||||
#define _LETIMER_IFC_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */
|
||||
#define _LETIMER_IFC_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */
|
||||
#define LETIMER_IFC_REP0_DEFAULT (_LETIMER_IFC_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IFC */
|
||||
#define LETIMER_IFC_REP1 (0x1UL << 4) /**< Clear Repeat Counter 1 Interrupt Flag */
|
||||
#define _LETIMER_IFC_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */
|
||||
#define _LETIMER_IFC_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */
|
||||
#define _LETIMER_IFC_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */
|
||||
#define LETIMER_IFC_REP1_DEFAULT (_LETIMER_IFC_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IFC */
|
||||
|
||||
/* Bit fields for LETIMER IEN */
|
||||
#define _LETIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IEN */
|
||||
#define _LETIMER_IEN_MASK 0x0000001FUL /**< Mask for LETIMER_IEN */
|
||||
#define LETIMER_IEN_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Enable */
|
||||
#define _LETIMER_IEN_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
|
||||
#define _LETIMER_IEN_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */
|
||||
#define _LETIMER_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
|
||||
#define LETIMER_IEN_COMP0_DEFAULT (_LETIMER_IEN_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IEN */
|
||||
#define LETIMER_IEN_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Enable */
|
||||
#define _LETIMER_IEN_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */
|
||||
#define _LETIMER_IEN_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */
|
||||
#define _LETIMER_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
|
||||
#define LETIMER_IEN_COMP1_DEFAULT (_LETIMER_IEN_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IEN */
|
||||
#define LETIMER_IEN_UF (0x1UL << 2) /**< Underflow Interrupt Enable */
|
||||
#define _LETIMER_IEN_UF_SHIFT 2 /**< Shift value for LETIMER_UF */
|
||||
#define _LETIMER_IEN_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */
|
||||
#define _LETIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
|
||||
#define LETIMER_IEN_UF_DEFAULT (_LETIMER_IEN_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IEN */
|
||||
#define LETIMER_IEN_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Enable */
|
||||
#define _LETIMER_IEN_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */
|
||||
#define _LETIMER_IEN_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */
|
||||
#define _LETIMER_IEN_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
|
||||
#define LETIMER_IEN_REP0_DEFAULT (_LETIMER_IEN_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IEN */
|
||||
#define LETIMER_IEN_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Enable */
|
||||
#define _LETIMER_IEN_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */
|
||||
#define _LETIMER_IEN_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */
|
||||
#define _LETIMER_IEN_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
|
||||
#define LETIMER_IEN_REP1_DEFAULT (_LETIMER_IEN_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IEN */
|
||||
|
||||
/* Bit fields for LETIMER FREEZE */
|
||||
#define _LETIMER_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LETIMER_FREEZE */
|
||||
#define _LETIMER_FREEZE_MASK 0x00000001UL /**< Mask for LETIMER_FREEZE */
|
||||
#define LETIMER_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
|
||||
#define _LETIMER_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LETIMER_REGFREEZE */
|
||||
#define _LETIMER_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LETIMER_REGFREEZE */
|
||||
#define _LETIMER_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_FREEZE */
|
||||
#define _LETIMER_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LETIMER_FREEZE */
|
||||
#define _LETIMER_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LETIMER_FREEZE */
|
||||
#define LETIMER_FREEZE_REGFREEZE_DEFAULT (_LETIMER_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_FREEZE */
|
||||
#define LETIMER_FREEZE_REGFREEZE_UPDATE (_LETIMER_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for LETIMER_FREEZE */
|
||||
#define LETIMER_FREEZE_REGFREEZE_FREEZE (_LETIMER_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for LETIMER_FREEZE */
|
||||
|
||||
/* Bit fields for LETIMER SYNCBUSY */
|
||||
#define _LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SYNCBUSY */
|
||||
#define _LETIMER_SYNCBUSY_MASK 0x0000003FUL /**< Mask for LETIMER_SYNCBUSY */
|
||||
#define LETIMER_SYNCBUSY_CTRL (0x1UL << 0) /**< LETIMERn_CTRL Register Busy */
|
||||
#define _LETIMER_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LETIMER_CTRL */
|
||||
#define _LETIMER_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LETIMER_CTRL */
|
||||
#define _LETIMER_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
|
||||
#define LETIMER_SYNCBUSY_CTRL_DEFAULT (_LETIMER_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
|
||||
#define LETIMER_SYNCBUSY_CMD (0x1UL << 1) /**< LETIMERn_CMD Register Busy */
|
||||
#define _LETIMER_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LETIMER_CMD */
|
||||
#define _LETIMER_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LETIMER_CMD */
|
||||
#define _LETIMER_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
|
||||
#define LETIMER_SYNCBUSY_CMD_DEFAULT (_LETIMER_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
|
||||
#define LETIMER_SYNCBUSY_COMP0 (0x1UL << 2) /**< LETIMERn_COMP0 Register Busy */
|
||||
#define _LETIMER_SYNCBUSY_COMP0_SHIFT 2 /**< Shift value for LETIMER_COMP0 */
|
||||
#define _LETIMER_SYNCBUSY_COMP0_MASK 0x4UL /**< Bit mask for LETIMER_COMP0 */
|
||||
#define _LETIMER_SYNCBUSY_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
|
||||
#define LETIMER_SYNCBUSY_COMP0_DEFAULT (_LETIMER_SYNCBUSY_COMP0_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
|
||||
#define LETIMER_SYNCBUSY_COMP1 (0x1UL << 3) /**< LETIMERn_COMP1 Register Busy */
|
||||
#define _LETIMER_SYNCBUSY_COMP1_SHIFT 3 /**< Shift value for LETIMER_COMP1 */
|
||||
#define _LETIMER_SYNCBUSY_COMP1_MASK 0x8UL /**< Bit mask for LETIMER_COMP1 */
|
||||
#define _LETIMER_SYNCBUSY_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
|
||||
#define LETIMER_SYNCBUSY_COMP1_DEFAULT (_LETIMER_SYNCBUSY_COMP1_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
|
||||
#define LETIMER_SYNCBUSY_REP0 (0x1UL << 4) /**< LETIMERn_REP0 Register Busy */
|
||||
#define _LETIMER_SYNCBUSY_REP0_SHIFT 4 /**< Shift value for LETIMER_REP0 */
|
||||
#define _LETIMER_SYNCBUSY_REP0_MASK 0x10UL /**< Bit mask for LETIMER_REP0 */
|
||||
#define _LETIMER_SYNCBUSY_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
|
||||
#define LETIMER_SYNCBUSY_REP0_DEFAULT (_LETIMER_SYNCBUSY_REP0_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
|
||||
#define LETIMER_SYNCBUSY_REP1 (0x1UL << 5) /**< LETIMERn_REP1 Register Busy */
|
||||
#define _LETIMER_SYNCBUSY_REP1_SHIFT 5 /**< Shift value for LETIMER_REP1 */
|
||||
#define _LETIMER_SYNCBUSY_REP1_MASK 0x20UL /**< Bit mask for LETIMER_REP1 */
|
||||
#define _LETIMER_SYNCBUSY_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
|
||||
#define LETIMER_SYNCBUSY_REP1_DEFAULT (_LETIMER_SYNCBUSY_REP1_DEFAULT << 5) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
|
||||
|
||||
/* Bit fields for LETIMER ROUTE */
|
||||
#define _LETIMER_ROUTE_RESETVALUE 0x00000000UL /**< Default value for LETIMER_ROUTE */
|
||||
#define _LETIMER_ROUTE_MASK 0x00000303UL /**< Mask for LETIMER_ROUTE */
|
||||
#define LETIMER_ROUTE_OUT0PEN (0x1UL << 0) /**< Output 0 Pin Enable */
|
||||
#define _LETIMER_ROUTE_OUT0PEN_SHIFT 0 /**< Shift value for LETIMER_OUT0PEN */
|
||||
#define _LETIMER_ROUTE_OUT0PEN_MASK 0x1UL /**< Bit mask for LETIMER_OUT0PEN */
|
||||
#define _LETIMER_ROUTE_OUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTE */
|
||||
#define LETIMER_ROUTE_OUT0PEN_DEFAULT (_LETIMER_ROUTE_OUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_ROUTE */
|
||||
#define LETIMER_ROUTE_OUT1PEN (0x1UL << 1) /**< Output 1 Pin Enable */
|
||||
#define _LETIMER_ROUTE_OUT1PEN_SHIFT 1 /**< Shift value for LETIMER_OUT1PEN */
|
||||
#define _LETIMER_ROUTE_OUT1PEN_MASK 0x2UL /**< Bit mask for LETIMER_OUT1PEN */
|
||||
#define _LETIMER_ROUTE_OUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTE */
|
||||
#define LETIMER_ROUTE_OUT1PEN_DEFAULT (_LETIMER_ROUTE_OUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_ROUTE */
|
||||
#define _LETIMER_ROUTE_LOCATION_SHIFT 8 /**< Shift value for LETIMER_LOCATION */
|
||||
#define _LETIMER_ROUTE_LOCATION_MASK 0x300UL /**< Bit mask for LETIMER_LOCATION */
|
||||
#define _LETIMER_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTE */
|
||||
#define _LETIMER_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for LETIMER_ROUTE */
|
||||
#define _LETIMER_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for LETIMER_ROUTE */
|
||||
#define _LETIMER_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for LETIMER_ROUTE */
|
||||
#define _LETIMER_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for LETIMER_ROUTE */
|
||||
#define LETIMER_ROUTE_LOCATION_DEFAULT (_LETIMER_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_ROUTE */
|
||||
#define LETIMER_ROUTE_LOCATION_LOC0 (_LETIMER_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for LETIMER_ROUTE */
|
||||
#define LETIMER_ROUTE_LOCATION_LOC1 (_LETIMER_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for LETIMER_ROUTE */
|
||||
#define LETIMER_ROUTE_LOCATION_LOC2 (_LETIMER_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for LETIMER_ROUTE */
|
||||
#define LETIMER_ROUTE_LOCATION_LOC3 (_LETIMER_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for LETIMER_ROUTE */
|
||||
|
||||
/** @} End of group EFM32G_LETIMER */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,659 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief efm32g_leuart Register and Bit Field definitions
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_LEUART
|
||||
* @{
|
||||
* @brief EFM32G_LEUART Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__IO uint32_t CMD; /**< Command Register */
|
||||
__I uint32_t STATUS; /**< Status Register */
|
||||
__IO uint32_t CLKDIV; /**< Clock Control Register */
|
||||
__IO uint32_t STARTFRAME; /**< Start Frame Register */
|
||||
__IO uint32_t SIGFRAME; /**< Signal Frame Register */
|
||||
__I uint32_t RXDATAX; /**< Receive Buffer Data Extended Register */
|
||||
__I uint32_t RXDATA; /**< Receive Buffer Data Register */
|
||||
__I uint32_t RXDATAXP; /**< Receive Buffer Data Extended Peek Register */
|
||||
__IO uint32_t TXDATAX; /**< Transmit Buffer Data Extended Register */
|
||||
__IO uint32_t TXDATA; /**< Transmit Buffer Data Register */
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IO uint32_t PULSECTRL; /**< Pulse Control Register */
|
||||
|
||||
__IO uint32_t FREEZE; /**< Freeze Register */
|
||||
__I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
|
||||
uint32_t RESERVED0[3]; /**< Reserved for future use **/
|
||||
__IO uint32_t ROUTE; /**< I/O Routing Register */
|
||||
} LEUART_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_LEUART_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/* Bit fields for LEUART CTRL */
|
||||
#define _LEUART_CTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_CTRL */
|
||||
#define _LEUART_CTRL_MASK 0x0000FFFFUL /**< Mask for LEUART_CTRL */
|
||||
#define LEUART_CTRL_AUTOTRI (0x1UL << 0) /**< Automatic Transmitter Tristate */
|
||||
#define _LEUART_CTRL_AUTOTRI_SHIFT 0 /**< Shift value for LEUART_AUTOTRI */
|
||||
#define _LEUART_CTRL_AUTOTRI_MASK 0x1UL /**< Bit mask for LEUART_AUTOTRI */
|
||||
#define _LEUART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_AUTOTRI_DEFAULT (_LEUART_CTRL_AUTOTRI_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_DATABITS (0x1UL << 1) /**< Data-Bit Mode */
|
||||
#define _LEUART_CTRL_DATABITS_SHIFT 1 /**< Shift value for LEUART_DATABITS */
|
||||
#define _LEUART_CTRL_DATABITS_MASK 0x2UL /**< Bit mask for LEUART_DATABITS */
|
||||
#define _LEUART_CTRL_DATABITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
|
||||
#define _LEUART_CTRL_DATABITS_EIGHT 0x00000000UL /**< Mode EIGHT for LEUART_CTRL */
|
||||
#define _LEUART_CTRL_DATABITS_NINE 0x00000001UL /**< Mode NINE for LEUART_CTRL */
|
||||
#define LEUART_CTRL_DATABITS_DEFAULT (_LEUART_CTRL_DATABITS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_DATABITS_EIGHT (_LEUART_CTRL_DATABITS_EIGHT << 1) /**< Shifted mode EIGHT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_DATABITS_NINE (_LEUART_CTRL_DATABITS_NINE << 1) /**< Shifted mode NINE for LEUART_CTRL */
|
||||
#define _LEUART_CTRL_PARITY_SHIFT 2 /**< Shift value for LEUART_PARITY */
|
||||
#define _LEUART_CTRL_PARITY_MASK 0xCUL /**< Bit mask for LEUART_PARITY */
|
||||
#define _LEUART_CTRL_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
|
||||
#define _LEUART_CTRL_PARITY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */
|
||||
#define _LEUART_CTRL_PARITY_EVEN 0x00000002UL /**< Mode EVEN for LEUART_CTRL */
|
||||
#define _LEUART_CTRL_PARITY_ODD 0x00000003UL /**< Mode ODD for LEUART_CTRL */
|
||||
#define LEUART_CTRL_PARITY_DEFAULT (_LEUART_CTRL_PARITY_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_PARITY_NONE (_LEUART_CTRL_PARITY_NONE << 2) /**< Shifted mode NONE for LEUART_CTRL */
|
||||
#define LEUART_CTRL_PARITY_EVEN (_LEUART_CTRL_PARITY_EVEN << 2) /**< Shifted mode EVEN for LEUART_CTRL */
|
||||
#define LEUART_CTRL_PARITY_ODD (_LEUART_CTRL_PARITY_ODD << 2) /**< Shifted mode ODD for LEUART_CTRL */
|
||||
#define LEUART_CTRL_STOPBITS (0x1UL << 4) /**< Stop-Bit Mode */
|
||||
#define _LEUART_CTRL_STOPBITS_SHIFT 4 /**< Shift value for LEUART_STOPBITS */
|
||||
#define _LEUART_CTRL_STOPBITS_MASK 0x10UL /**< Bit mask for LEUART_STOPBITS */
|
||||
#define _LEUART_CTRL_STOPBITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
|
||||
#define _LEUART_CTRL_STOPBITS_ONE 0x00000000UL /**< Mode ONE for LEUART_CTRL */
|
||||
#define _LEUART_CTRL_STOPBITS_TWO 0x00000001UL /**< Mode TWO for LEUART_CTRL */
|
||||
#define LEUART_CTRL_STOPBITS_DEFAULT (_LEUART_CTRL_STOPBITS_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_STOPBITS_ONE (_LEUART_CTRL_STOPBITS_ONE << 4) /**< Shifted mode ONE for LEUART_CTRL */
|
||||
#define LEUART_CTRL_STOPBITS_TWO (_LEUART_CTRL_STOPBITS_TWO << 4) /**< Shifted mode TWO for LEUART_CTRL */
|
||||
#define LEUART_CTRL_INV (0x1UL << 5) /**< Invert Input And Output */
|
||||
#define _LEUART_CTRL_INV_SHIFT 5 /**< Shift value for LEUART_INV */
|
||||
#define _LEUART_CTRL_INV_MASK 0x20UL /**< Bit mask for LEUART_INV */
|
||||
#define _LEUART_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_INV_DEFAULT (_LEUART_CTRL_INV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_ERRSDMA (0x1UL << 6) /**< Clear RX DMA On Error */
|
||||
#define _LEUART_CTRL_ERRSDMA_SHIFT 6 /**< Shift value for LEUART_ERRSDMA */
|
||||
#define _LEUART_CTRL_ERRSDMA_MASK 0x40UL /**< Bit mask for LEUART_ERRSDMA */
|
||||
#define _LEUART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_ERRSDMA_DEFAULT (_LEUART_CTRL_ERRSDMA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_LOOPBK (0x1UL << 7) /**< Loopback Enable */
|
||||
#define _LEUART_CTRL_LOOPBK_SHIFT 7 /**< Shift value for LEUART_LOOPBK */
|
||||
#define _LEUART_CTRL_LOOPBK_MASK 0x80UL /**< Bit mask for LEUART_LOOPBK */
|
||||
#define _LEUART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_LOOPBK_DEFAULT (_LEUART_CTRL_LOOPBK_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_SFUBRX (0x1UL << 8) /**< Start-Frame UnBlock RX */
|
||||
#define _LEUART_CTRL_SFUBRX_SHIFT 8 /**< Shift value for LEUART_SFUBRX */
|
||||
#define _LEUART_CTRL_SFUBRX_MASK 0x100UL /**< Bit mask for LEUART_SFUBRX */
|
||||
#define _LEUART_CTRL_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_SFUBRX_DEFAULT (_LEUART_CTRL_SFUBRX_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_MPM (0x1UL << 9) /**< Multi-Processor Mode */
|
||||
#define _LEUART_CTRL_MPM_SHIFT 9 /**< Shift value for LEUART_MPM */
|
||||
#define _LEUART_CTRL_MPM_MASK 0x200UL /**< Bit mask for LEUART_MPM */
|
||||
#define _LEUART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_MPM_DEFAULT (_LEUART_CTRL_MPM_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_MPAB (0x1UL << 10) /**< Multi-Processor Address-Bit */
|
||||
#define _LEUART_CTRL_MPAB_SHIFT 10 /**< Shift value for LEUART_MPAB */
|
||||
#define _LEUART_CTRL_MPAB_MASK 0x400UL /**< Bit mask for LEUART_MPAB */
|
||||
#define _LEUART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_MPAB_DEFAULT (_LEUART_CTRL_MPAB_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_BIT8DV (0x1UL << 11) /**< Bit 8 Default Value */
|
||||
#define _LEUART_CTRL_BIT8DV_SHIFT 11 /**< Shift value for LEUART_BIT8DV */
|
||||
#define _LEUART_CTRL_BIT8DV_MASK 0x800UL /**< Bit mask for LEUART_BIT8DV */
|
||||
#define _LEUART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_BIT8DV_DEFAULT (_LEUART_CTRL_BIT8DV_DEFAULT << 11) /**< Shifted mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_RXDMAWU (0x1UL << 12) /**< RX DMA Wakeup */
|
||||
#define _LEUART_CTRL_RXDMAWU_SHIFT 12 /**< Shift value for LEUART_RXDMAWU */
|
||||
#define _LEUART_CTRL_RXDMAWU_MASK 0x1000UL /**< Bit mask for LEUART_RXDMAWU */
|
||||
#define _LEUART_CTRL_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_RXDMAWU_DEFAULT (_LEUART_CTRL_RXDMAWU_DEFAULT << 12) /**< Shifted mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_TXDMAWU (0x1UL << 13) /**< TX DMA Wakeup */
|
||||
#define _LEUART_CTRL_TXDMAWU_SHIFT 13 /**< Shift value for LEUART_TXDMAWU */
|
||||
#define _LEUART_CTRL_TXDMAWU_MASK 0x2000UL /**< Bit mask for LEUART_TXDMAWU */
|
||||
#define _LEUART_CTRL_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_TXDMAWU_DEFAULT (_LEUART_CTRL_TXDMAWU_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_CTRL */
|
||||
#define _LEUART_CTRL_TXDELAY_SHIFT 14 /**< Shift value for LEUART_TXDELAY */
|
||||
#define _LEUART_CTRL_TXDELAY_MASK 0xC000UL /**< Bit mask for LEUART_TXDELAY */
|
||||
#define _LEUART_CTRL_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
|
||||
#define _LEUART_CTRL_TXDELAY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */
|
||||
#define _LEUART_CTRL_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for LEUART_CTRL */
|
||||
#define _LEUART_CTRL_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for LEUART_CTRL */
|
||||
#define _LEUART_CTRL_TXDELAY_TRIPLE 0x00000003UL /**< Mode TRIPLE for LEUART_CTRL */
|
||||
#define LEUART_CTRL_TXDELAY_DEFAULT (_LEUART_CTRL_TXDELAY_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_TXDELAY_NONE (_LEUART_CTRL_TXDELAY_NONE << 14) /**< Shifted mode NONE for LEUART_CTRL */
|
||||
#define LEUART_CTRL_TXDELAY_SINGLE (_LEUART_CTRL_TXDELAY_SINGLE << 14) /**< Shifted mode SINGLE for LEUART_CTRL */
|
||||
#define LEUART_CTRL_TXDELAY_DOUBLE (_LEUART_CTRL_TXDELAY_DOUBLE << 14) /**< Shifted mode DOUBLE for LEUART_CTRL */
|
||||
#define LEUART_CTRL_TXDELAY_TRIPLE (_LEUART_CTRL_TXDELAY_TRIPLE << 14) /**< Shifted mode TRIPLE for LEUART_CTRL */
|
||||
|
||||
/* Bit fields for LEUART CMD */
|
||||
#define _LEUART_CMD_RESETVALUE 0x00000000UL /**< Default value for LEUART_CMD */
|
||||
#define _LEUART_CMD_MASK 0x000000FFUL /**< Mask for LEUART_CMD */
|
||||
#define LEUART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */
|
||||
#define _LEUART_CMD_RXEN_SHIFT 0 /**< Shift value for LEUART_RXEN */
|
||||
#define _LEUART_CMD_RXEN_MASK 0x1UL /**< Bit mask for LEUART_RXEN */
|
||||
#define _LEUART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
|
||||
#define LEUART_CMD_RXEN_DEFAULT (_LEUART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CMD */
|
||||
#define LEUART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */
|
||||
#define _LEUART_CMD_RXDIS_SHIFT 1 /**< Shift value for LEUART_RXDIS */
|
||||
#define _LEUART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for LEUART_RXDIS */
|
||||
#define _LEUART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
|
||||
#define LEUART_CMD_RXDIS_DEFAULT (_LEUART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CMD */
|
||||
#define LEUART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */
|
||||
#define _LEUART_CMD_TXEN_SHIFT 2 /**< Shift value for LEUART_TXEN */
|
||||
#define _LEUART_CMD_TXEN_MASK 0x4UL /**< Bit mask for LEUART_TXEN */
|
||||
#define _LEUART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
|
||||
#define LEUART_CMD_TXEN_DEFAULT (_LEUART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CMD */
|
||||
#define LEUART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */
|
||||
#define _LEUART_CMD_TXDIS_SHIFT 3 /**< Shift value for LEUART_TXDIS */
|
||||
#define _LEUART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for LEUART_TXDIS */
|
||||
#define _LEUART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
|
||||
#define LEUART_CMD_TXDIS_DEFAULT (_LEUART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CMD */
|
||||
#define LEUART_CMD_RXBLOCKEN (0x1UL << 4) /**< Receiver Block Enable */
|
||||
#define _LEUART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for LEUART_RXBLOCKEN */
|
||||
#define _LEUART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for LEUART_RXBLOCKEN */
|
||||
#define _LEUART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
|
||||
#define LEUART_CMD_RXBLOCKEN_DEFAULT (_LEUART_CMD_RXBLOCKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CMD */
|
||||
#define LEUART_CMD_RXBLOCKDIS (0x1UL << 5) /**< Receiver Block Disable */
|
||||
#define _LEUART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for LEUART_RXBLOCKDIS */
|
||||
#define _LEUART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for LEUART_RXBLOCKDIS */
|
||||
#define _LEUART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
|
||||
#define LEUART_CMD_RXBLOCKDIS_DEFAULT (_LEUART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CMD */
|
||||
#define LEUART_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */
|
||||
#define _LEUART_CMD_CLEARTX_SHIFT 6 /**< Shift value for LEUART_CLEARTX */
|
||||
#define _LEUART_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for LEUART_CLEARTX */
|
||||
#define _LEUART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
|
||||
#define LEUART_CMD_CLEARTX_DEFAULT (_LEUART_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CMD */
|
||||
#define LEUART_CMD_CLEARRX (0x1UL << 7) /**< Clear RX */
|
||||
#define _LEUART_CMD_CLEARRX_SHIFT 7 /**< Shift value for LEUART_CLEARRX */
|
||||
#define _LEUART_CMD_CLEARRX_MASK 0x80UL /**< Bit mask for LEUART_CLEARRX */
|
||||
#define _LEUART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
|
||||
#define LEUART_CMD_CLEARRX_DEFAULT (_LEUART_CMD_CLEARRX_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CMD */
|
||||
|
||||
/* Bit fields for LEUART STATUS */
|
||||
#define _LEUART_STATUS_RESETVALUE 0x00000010UL /**< Default value for LEUART_STATUS */
|
||||
#define _LEUART_STATUS_MASK 0x0000003FUL /**< Mask for LEUART_STATUS */
|
||||
#define LEUART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */
|
||||
#define _LEUART_STATUS_RXENS_SHIFT 0 /**< Shift value for LEUART_RXENS */
|
||||
#define _LEUART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for LEUART_RXENS */
|
||||
#define _LEUART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
|
||||
#define LEUART_STATUS_RXENS_DEFAULT (_LEUART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STATUS */
|
||||
#define LEUART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */
|
||||
#define _LEUART_STATUS_TXENS_SHIFT 1 /**< Shift value for LEUART_TXENS */
|
||||
#define _LEUART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for LEUART_TXENS */
|
||||
#define _LEUART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
|
||||
#define LEUART_STATUS_TXENS_DEFAULT (_LEUART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_STATUS */
|
||||
#define LEUART_STATUS_RXBLOCK (0x1UL << 2) /**< Block Incoming Data */
|
||||
#define _LEUART_STATUS_RXBLOCK_SHIFT 2 /**< Shift value for LEUART_RXBLOCK */
|
||||
#define _LEUART_STATUS_RXBLOCK_MASK 0x4UL /**< Bit mask for LEUART_RXBLOCK */
|
||||
#define _LEUART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
|
||||
#define LEUART_STATUS_RXBLOCK_DEFAULT (_LEUART_STATUS_RXBLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_STATUS */
|
||||
#define LEUART_STATUS_TXC (0x1UL << 3) /**< TX Complete */
|
||||
#define _LEUART_STATUS_TXC_SHIFT 3 /**< Shift value for LEUART_TXC */
|
||||
#define _LEUART_STATUS_TXC_MASK 0x8UL /**< Bit mask for LEUART_TXC */
|
||||
#define _LEUART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
|
||||
#define LEUART_STATUS_TXC_DEFAULT (_LEUART_STATUS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_STATUS */
|
||||
#define LEUART_STATUS_TXBL (0x1UL << 4) /**< TX Buffer Level */
|
||||
#define _LEUART_STATUS_TXBL_SHIFT 4 /**< Shift value for LEUART_TXBL */
|
||||
#define _LEUART_STATUS_TXBL_MASK 0x10UL /**< Bit mask for LEUART_TXBL */
|
||||
#define _LEUART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_STATUS */
|
||||
#define LEUART_STATUS_TXBL_DEFAULT (_LEUART_STATUS_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_STATUS */
|
||||
#define LEUART_STATUS_RXDATAV (0x1UL << 5) /**< RX Data Valid */
|
||||
#define _LEUART_STATUS_RXDATAV_SHIFT 5 /**< Shift value for LEUART_RXDATAV */
|
||||
#define _LEUART_STATUS_RXDATAV_MASK 0x20UL /**< Bit mask for LEUART_RXDATAV */
|
||||
#define _LEUART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
|
||||
#define LEUART_STATUS_RXDATAV_DEFAULT (_LEUART_STATUS_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_STATUS */
|
||||
|
||||
/* Bit fields for LEUART CLKDIV */
|
||||
#define _LEUART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for LEUART_CLKDIV */
|
||||
#define _LEUART_CLKDIV_MASK 0x00007FF8UL /**< Mask for LEUART_CLKDIV */
|
||||
#define _LEUART_CLKDIV_DIV_SHIFT 3 /**< Shift value for LEUART_DIV */
|
||||
#define _LEUART_CLKDIV_DIV_MASK 0x7FF8UL /**< Bit mask for LEUART_DIV */
|
||||
#define _LEUART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CLKDIV */
|
||||
#define LEUART_CLKDIV_DIV_DEFAULT (_LEUART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CLKDIV */
|
||||
|
||||
/* Bit fields for LEUART STARTFRAME */
|
||||
#define _LEUART_STARTFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_STARTFRAME */
|
||||
#define _LEUART_STARTFRAME_MASK 0x000001FFUL /**< Mask for LEUART_STARTFRAME */
|
||||
#define _LEUART_STARTFRAME_STARTFRAME_SHIFT 0 /**< Shift value for LEUART_STARTFRAME */
|
||||
#define _LEUART_STARTFRAME_STARTFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_STARTFRAME */
|
||||
#define _LEUART_STARTFRAME_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STARTFRAME */
|
||||
#define LEUART_STARTFRAME_STARTFRAME_DEFAULT (_LEUART_STARTFRAME_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STARTFRAME */
|
||||
|
||||
/* Bit fields for LEUART SIGFRAME */
|
||||
#define _LEUART_SIGFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_SIGFRAME */
|
||||
#define _LEUART_SIGFRAME_MASK 0x000001FFUL /**< Mask for LEUART_SIGFRAME */
|
||||
#define _LEUART_SIGFRAME_SIGFRAME_SHIFT 0 /**< Shift value for LEUART_SIGFRAME */
|
||||
#define _LEUART_SIGFRAME_SIGFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_SIGFRAME */
|
||||
#define _LEUART_SIGFRAME_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SIGFRAME */
|
||||
#define LEUART_SIGFRAME_SIGFRAME_DEFAULT (_LEUART_SIGFRAME_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SIGFRAME */
|
||||
|
||||
/* Bit fields for LEUART RXDATAX */
|
||||
#define _LEUART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAX */
|
||||
#define _LEUART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAX */
|
||||
#define _LEUART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */
|
||||
#define _LEUART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATA */
|
||||
#define _LEUART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */
|
||||
#define LEUART_RXDATAX_RXDATA_DEFAULT (_LEUART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAX */
|
||||
#define LEUART_RXDATAX_PERR (0x1UL << 14) /**< Receive Data Parity Error */
|
||||
#define _LEUART_RXDATAX_PERR_SHIFT 14 /**< Shift value for LEUART_PERR */
|
||||
#define _LEUART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for LEUART_PERR */
|
||||
#define _LEUART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */
|
||||
#define LEUART_RXDATAX_PERR_DEFAULT (_LEUART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAX */
|
||||
#define LEUART_RXDATAX_FERR (0x1UL << 15) /**< Receive Data Framing Error */
|
||||
#define _LEUART_RXDATAX_FERR_SHIFT 15 /**< Shift value for LEUART_FERR */
|
||||
#define _LEUART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for LEUART_FERR */
|
||||
#define _LEUART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */
|
||||
#define LEUART_RXDATAX_FERR_DEFAULT (_LEUART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAX */
|
||||
|
||||
/* Bit fields for LEUART RXDATA */
|
||||
#define _LEUART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATA */
|
||||
#define _LEUART_RXDATA_MASK 0x000000FFUL /**< Mask for LEUART_RXDATA */
|
||||
#define _LEUART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */
|
||||
#define _LEUART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for LEUART_RXDATA */
|
||||
#define _LEUART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATA */
|
||||
#define LEUART_RXDATA_RXDATA_DEFAULT (_LEUART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATA */
|
||||
|
||||
/* Bit fields for LEUART RXDATAXP */
|
||||
#define _LEUART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAXP */
|
||||
#define _LEUART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAXP */
|
||||
#define _LEUART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for LEUART_RXDATAP */
|
||||
#define _LEUART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATAP */
|
||||
#define _LEUART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */
|
||||
#define LEUART_RXDATAXP_RXDATAP_DEFAULT (_LEUART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */
|
||||
#define LEUART_RXDATAXP_PERRP (0x1UL << 14) /**< Receive Data Parity Error Peek */
|
||||
#define _LEUART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for LEUART_PERRP */
|
||||
#define _LEUART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for LEUART_PERRP */
|
||||
#define _LEUART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */
|
||||
#define LEUART_RXDATAXP_PERRP_DEFAULT (_LEUART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */
|
||||
#define LEUART_RXDATAXP_FERRP (0x1UL << 15) /**< Receive Data Framing Error Peek */
|
||||
#define _LEUART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for LEUART_FERRP */
|
||||
#define _LEUART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for LEUART_FERRP */
|
||||
#define _LEUART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */
|
||||
#define LEUART_RXDATAXP_FERRP_DEFAULT (_LEUART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */
|
||||
|
||||
/* Bit fields for LEUART TXDATAX */
|
||||
#define _LEUART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATAX */
|
||||
#define _LEUART_TXDATAX_MASK 0x0000E1FFUL /**< Mask for LEUART_TXDATAX */
|
||||
#define _LEUART_TXDATAX_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */
|
||||
#define _LEUART_TXDATAX_TXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_TXDATA */
|
||||
#define _LEUART_TXDATAX_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
|
||||
#define LEUART_TXDATAX_TXDATA_DEFAULT (_LEUART_TXDATAX_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
|
||||
#define LEUART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */
|
||||
#define _LEUART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for LEUART_TXBREAK */
|
||||
#define _LEUART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for LEUART_TXBREAK */
|
||||
#define _LEUART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
|
||||
#define LEUART_TXDATAX_TXBREAK_DEFAULT (_LEUART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
|
||||
#define LEUART_TXDATAX_TXDISAT (0x1UL << 14) /**< Disable TX After Transmission */
|
||||
#define _LEUART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for LEUART_TXDISAT */
|
||||
#define _LEUART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for LEUART_TXDISAT */
|
||||
#define _LEUART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
|
||||
#define LEUART_TXDATAX_TXDISAT_DEFAULT (_LEUART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
|
||||
#define LEUART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */
|
||||
#define _LEUART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for LEUART_RXENAT */
|
||||
#define _LEUART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for LEUART_RXENAT */
|
||||
#define _LEUART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
|
||||
#define LEUART_TXDATAX_RXENAT_DEFAULT (_LEUART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
|
||||
|
||||
/* Bit fields for LEUART TXDATA */
|
||||
#define _LEUART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATA */
|
||||
#define _LEUART_TXDATA_MASK 0x000000FFUL /**< Mask for LEUART_TXDATA */
|
||||
#define _LEUART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */
|
||||
#define _LEUART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for LEUART_TXDATA */
|
||||
#define _LEUART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATA */
|
||||
#define LEUART_TXDATA_TXDATA_DEFAULT (_LEUART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATA */
|
||||
|
||||
/* Bit fields for LEUART IF */
|
||||
#define _LEUART_IF_RESETVALUE 0x00000002UL /**< Default value for LEUART_IF */
|
||||
#define _LEUART_IF_MASK 0x000007FFUL /**< Mask for LEUART_IF */
|
||||
#define LEUART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */
|
||||
#define _LEUART_IF_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */
|
||||
#define _LEUART_IF_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */
|
||||
#define _LEUART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_TXC_DEFAULT (_LEUART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */
|
||||
#define _LEUART_IF_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */
|
||||
#define _LEUART_IF_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */
|
||||
#define _LEUART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_TXBL_DEFAULT (_LEUART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */
|
||||
#define _LEUART_IF_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */
|
||||
#define _LEUART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */
|
||||
#define _LEUART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_RXDATAV_DEFAULT (_LEUART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_RXOF (0x1UL << 3) /**< RX Overflow Interrupt Flag */
|
||||
#define _LEUART_IF_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */
|
||||
#define _LEUART_IF_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */
|
||||
#define _LEUART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_RXOF_DEFAULT (_LEUART_IF_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_RXUF (0x1UL << 4) /**< RX Underflow Interrupt Flag */
|
||||
#define _LEUART_IF_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */
|
||||
#define _LEUART_IF_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */
|
||||
#define _LEUART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_RXUF_DEFAULT (_LEUART_IF_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_TXOF (0x1UL << 5) /**< TX Overflow Interrupt Flag */
|
||||
#define _LEUART_IF_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */
|
||||
#define _LEUART_IF_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */
|
||||
#define _LEUART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_TXOF_DEFAULT (_LEUART_IF_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_PERR (0x1UL << 6) /**< Parity Error Interrupt Flag */
|
||||
#define _LEUART_IF_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */
|
||||
#define _LEUART_IF_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */
|
||||
#define _LEUART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_PERR_DEFAULT (_LEUART_IF_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_FERR (0x1UL << 7) /**< Framing Error Interrupt Flag */
|
||||
#define _LEUART_IF_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */
|
||||
#define _LEUART_IF_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */
|
||||
#define _LEUART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_FERR_DEFAULT (_LEUART_IF_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_MPAF (0x1UL << 8) /**< Multi-Processor Address Frame Interrupt Flag */
|
||||
#define _LEUART_IF_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */
|
||||
#define _LEUART_IF_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */
|
||||
#define _LEUART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_MPAF_DEFAULT (_LEUART_IF_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_STARTF (0x1UL << 9) /**< Start Frame Interrupt Flag */
|
||||
#define _LEUART_IF_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */
|
||||
#define _LEUART_IF_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */
|
||||
#define _LEUART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_STARTF_DEFAULT (_LEUART_IF_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_SIGF (0x1UL << 10) /**< Signal Frame Interrupt Flag */
|
||||
#define _LEUART_IF_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */
|
||||
#define _LEUART_IF_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */
|
||||
#define _LEUART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_SIGF_DEFAULT (_LEUART_IF_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IF */
|
||||
|
||||
/* Bit fields for LEUART IFS */
|
||||
#define _LEUART_IFS_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFS */
|
||||
#define _LEUART_IFS_MASK 0x000007F9UL /**< Mask for LEUART_IFS */
|
||||
#define LEUART_IFS_TXC (0x1UL << 0) /**< Set TX Complete Interrupt Flag */
|
||||
#define _LEUART_IFS_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */
|
||||
#define _LEUART_IFS_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */
|
||||
#define _LEUART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_TXC_DEFAULT (_LEUART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_RXOF (0x1UL << 3) /**< Set RX Overflow Interrupt Flag */
|
||||
#define _LEUART_IFS_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */
|
||||
#define _LEUART_IFS_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */
|
||||
#define _LEUART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_RXOF_DEFAULT (_LEUART_IFS_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_RXUF (0x1UL << 4) /**< Set RX Underflow Interrupt Flag */
|
||||
#define _LEUART_IFS_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */
|
||||
#define _LEUART_IFS_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */
|
||||
#define _LEUART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_RXUF_DEFAULT (_LEUART_IFS_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_TXOF (0x1UL << 5) /**< Set TX Overflow Interrupt Flag */
|
||||
#define _LEUART_IFS_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */
|
||||
#define _LEUART_IFS_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */
|
||||
#define _LEUART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_TXOF_DEFAULT (_LEUART_IFS_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_PERR (0x1UL << 6) /**< Set Parity Error Interrupt Flag */
|
||||
#define _LEUART_IFS_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */
|
||||
#define _LEUART_IFS_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */
|
||||
#define _LEUART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_PERR_DEFAULT (_LEUART_IFS_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_FERR (0x1UL << 7) /**< Set Framing Error Interrupt Flag */
|
||||
#define _LEUART_IFS_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */
|
||||
#define _LEUART_IFS_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */
|
||||
#define _LEUART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_FERR_DEFAULT (_LEUART_IFS_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_MPAF (0x1UL << 8) /**< Set Multi-Processor Address Frame Interrupt Flag */
|
||||
#define _LEUART_IFS_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */
|
||||
#define _LEUART_IFS_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */
|
||||
#define _LEUART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_MPAF_DEFAULT (_LEUART_IFS_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_STARTF (0x1UL << 9) /**< Set Start Frame Interrupt Flag */
|
||||
#define _LEUART_IFS_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */
|
||||
#define _LEUART_IFS_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */
|
||||
#define _LEUART_IFS_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_STARTF_DEFAULT (_LEUART_IFS_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_SIGF (0x1UL << 10) /**< Set Signal Frame Interrupt Flag */
|
||||
#define _LEUART_IFS_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */
|
||||
#define _LEUART_IFS_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */
|
||||
#define _LEUART_IFS_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_SIGF_DEFAULT (_LEUART_IFS_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFS */
|
||||
|
||||
/* Bit fields for LEUART IFC */
|
||||
#define _LEUART_IFC_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFC */
|
||||
#define _LEUART_IFC_MASK 0x000007F9UL /**< Mask for LEUART_IFC */
|
||||
#define LEUART_IFC_TXC (0x1UL << 0) /**< Clear TX Complete Interrupt Flag */
|
||||
#define _LEUART_IFC_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */
|
||||
#define _LEUART_IFC_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */
|
||||
#define _LEUART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_TXC_DEFAULT (_LEUART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_RXOF (0x1UL << 3) /**< Clear RX Overflow Interrupt Flag */
|
||||
#define _LEUART_IFC_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */
|
||||
#define _LEUART_IFC_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */
|
||||
#define _LEUART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_RXOF_DEFAULT (_LEUART_IFC_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_RXUF (0x1UL << 4) /**< Clear RX Underflow Interrupt Flag */
|
||||
#define _LEUART_IFC_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */
|
||||
#define _LEUART_IFC_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */
|
||||
#define _LEUART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_RXUF_DEFAULT (_LEUART_IFC_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_TXOF (0x1UL << 5) /**< Clear TX Overflow Interrupt Flag */
|
||||
#define _LEUART_IFC_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */
|
||||
#define _LEUART_IFC_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */
|
||||
#define _LEUART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_TXOF_DEFAULT (_LEUART_IFC_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_PERR (0x1UL << 6) /**< Clear Parity Error Interrupt Flag */
|
||||
#define _LEUART_IFC_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */
|
||||
#define _LEUART_IFC_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */
|
||||
#define _LEUART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_PERR_DEFAULT (_LEUART_IFC_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_FERR (0x1UL << 7) /**< Clear Framing Error Interrupt Flag */
|
||||
#define _LEUART_IFC_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */
|
||||
#define _LEUART_IFC_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */
|
||||
#define _LEUART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_FERR_DEFAULT (_LEUART_IFC_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_MPAF (0x1UL << 8) /**< Clear Multi-Processor Address Frame Interrupt Flag */
|
||||
#define _LEUART_IFC_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */
|
||||
#define _LEUART_IFC_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */
|
||||
#define _LEUART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_MPAF_DEFAULT (_LEUART_IFC_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_STARTF (0x1UL << 9) /**< Clear Start-Frame Interrupt Flag */
|
||||
#define _LEUART_IFC_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */
|
||||
#define _LEUART_IFC_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */
|
||||
#define _LEUART_IFC_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_STARTF_DEFAULT (_LEUART_IFC_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_SIGF (0x1UL << 10) /**< Clear Signal-Frame Interrupt Flag */
|
||||
#define _LEUART_IFC_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */
|
||||
#define _LEUART_IFC_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */
|
||||
#define _LEUART_IFC_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_SIGF_DEFAULT (_LEUART_IFC_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFC */
|
||||
|
||||
/* Bit fields for LEUART IEN */
|
||||
#define _LEUART_IEN_RESETVALUE 0x00000000UL /**< Default value for LEUART_IEN */
|
||||
#define _LEUART_IEN_MASK 0x000007FFUL /**< Mask for LEUART_IEN */
|
||||
#define LEUART_IEN_TXC (0x1UL << 0) /**< TX Complete Interrupt Enable */
|
||||
#define _LEUART_IEN_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */
|
||||
#define _LEUART_IEN_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */
|
||||
#define _LEUART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_TXC_DEFAULT (_LEUART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Enable */
|
||||
#define _LEUART_IEN_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */
|
||||
#define _LEUART_IEN_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */
|
||||
#define _LEUART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_TXBL_DEFAULT (_LEUART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Enable */
|
||||
#define _LEUART_IEN_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */
|
||||
#define _LEUART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */
|
||||
#define _LEUART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_RXDATAV_DEFAULT (_LEUART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_RXOF (0x1UL << 3) /**< RX Overflow Interrupt Enable */
|
||||
#define _LEUART_IEN_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */
|
||||
#define _LEUART_IEN_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */
|
||||
#define _LEUART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_RXOF_DEFAULT (_LEUART_IEN_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_RXUF (0x1UL << 4) /**< RX Underflow Interrupt Enable */
|
||||
#define _LEUART_IEN_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */
|
||||
#define _LEUART_IEN_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */
|
||||
#define _LEUART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_RXUF_DEFAULT (_LEUART_IEN_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_TXOF (0x1UL << 5) /**< TX Overflow Interrupt Enable */
|
||||
#define _LEUART_IEN_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */
|
||||
#define _LEUART_IEN_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */
|
||||
#define _LEUART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_TXOF_DEFAULT (_LEUART_IEN_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_PERR (0x1UL << 6) /**< Parity Error Interrupt Enable */
|
||||
#define _LEUART_IEN_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */
|
||||
#define _LEUART_IEN_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */
|
||||
#define _LEUART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_PERR_DEFAULT (_LEUART_IEN_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_FERR (0x1UL << 7) /**< Framing Error Interrupt Enable */
|
||||
#define _LEUART_IEN_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */
|
||||
#define _LEUART_IEN_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */
|
||||
#define _LEUART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_FERR_DEFAULT (_LEUART_IEN_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_MPAF (0x1UL << 8) /**< Multi-Processor Address Frame Interrupt Enable */
|
||||
#define _LEUART_IEN_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */
|
||||
#define _LEUART_IEN_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */
|
||||
#define _LEUART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_MPAF_DEFAULT (_LEUART_IEN_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_STARTF (0x1UL << 9) /**< Start Frame Interrupt Enable */
|
||||
#define _LEUART_IEN_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */
|
||||
#define _LEUART_IEN_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */
|
||||
#define _LEUART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_STARTF_DEFAULT (_LEUART_IEN_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_SIGF (0x1UL << 10) /**< Signal Frame Interrupt Enable */
|
||||
#define _LEUART_IEN_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */
|
||||
#define _LEUART_IEN_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */
|
||||
#define _LEUART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_SIGF_DEFAULT (_LEUART_IEN_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IEN */
|
||||
|
||||
/* Bit fields for LEUART PULSECTRL */
|
||||
#define _LEUART_PULSECTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_PULSECTRL */
|
||||
#define _LEUART_PULSECTRL_MASK 0x0000003FUL /**< Mask for LEUART_PULSECTRL */
|
||||
#define _LEUART_PULSECTRL_PULSEW_SHIFT 0 /**< Shift value for LEUART_PULSEW */
|
||||
#define _LEUART_PULSECTRL_PULSEW_MASK 0xFUL /**< Bit mask for LEUART_PULSEW */
|
||||
#define _LEUART_PULSECTRL_PULSEW_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */
|
||||
#define LEUART_PULSECTRL_PULSEW_DEFAULT (_LEUART_PULSECTRL_PULSEW_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */
|
||||
#define LEUART_PULSECTRL_PULSEEN (0x1UL << 4) /**< Pulse Generator/Extender Enable */
|
||||
#define _LEUART_PULSECTRL_PULSEEN_SHIFT 4 /**< Shift value for LEUART_PULSEEN */
|
||||
#define _LEUART_PULSECTRL_PULSEEN_MASK 0x10UL /**< Bit mask for LEUART_PULSEEN */
|
||||
#define _LEUART_PULSECTRL_PULSEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */
|
||||
#define LEUART_PULSECTRL_PULSEEN_DEFAULT (_LEUART_PULSECTRL_PULSEEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */
|
||||
#define LEUART_PULSECTRL_PULSEFILT (0x1UL << 5) /**< Pulse Filter */
|
||||
#define _LEUART_PULSECTRL_PULSEFILT_SHIFT 5 /**< Shift value for LEUART_PULSEFILT */
|
||||
#define _LEUART_PULSECTRL_PULSEFILT_MASK 0x20UL /**< Bit mask for LEUART_PULSEFILT */
|
||||
#define _LEUART_PULSECTRL_PULSEFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */
|
||||
#define LEUART_PULSECTRL_PULSEFILT_DEFAULT (_LEUART_PULSECTRL_PULSEFILT_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */
|
||||
|
||||
/* Bit fields for LEUART FREEZE */
|
||||
#define _LEUART_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LEUART_FREEZE */
|
||||
#define _LEUART_FREEZE_MASK 0x00000001UL /**< Mask for LEUART_FREEZE */
|
||||
#define LEUART_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
|
||||
#define _LEUART_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LEUART_REGFREEZE */
|
||||
#define _LEUART_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LEUART_REGFREEZE */
|
||||
#define _LEUART_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_FREEZE */
|
||||
#define _LEUART_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LEUART_FREEZE */
|
||||
#define _LEUART_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LEUART_FREEZE */
|
||||
#define LEUART_FREEZE_REGFREEZE_DEFAULT (_LEUART_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_FREEZE */
|
||||
#define LEUART_FREEZE_REGFREEZE_UPDATE (_LEUART_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for LEUART_FREEZE */
|
||||
#define LEUART_FREEZE_REGFREEZE_FREEZE (_LEUART_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for LEUART_FREEZE */
|
||||
|
||||
/* Bit fields for LEUART SYNCBUSY */
|
||||
#define _LEUART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LEUART_SYNCBUSY */
|
||||
#define _LEUART_SYNCBUSY_MASK 0x000000FFUL /**< Mask for LEUART_SYNCBUSY */
|
||||
#define LEUART_SYNCBUSY_CTRL (0x1UL << 0) /**< LEUARTn_CTRL Register Busy */
|
||||
#define _LEUART_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LEUART_CTRL */
|
||||
#define _LEUART_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LEUART_CTRL */
|
||||
#define _LEUART_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
|
||||
#define LEUART_SYNCBUSY_CTRL_DEFAULT (_LEUART_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
|
||||
#define LEUART_SYNCBUSY_CMD (0x1UL << 1) /**< LEUARTn_CMD Register Busy */
|
||||
#define _LEUART_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LEUART_CMD */
|
||||
#define _LEUART_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LEUART_CMD */
|
||||
#define _LEUART_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
|
||||
#define LEUART_SYNCBUSY_CMD_DEFAULT (_LEUART_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
|
||||
#define LEUART_SYNCBUSY_CLKDIV (0x1UL << 2) /**< LEUARTn_CLKDIV Register Busy */
|
||||
#define _LEUART_SYNCBUSY_CLKDIV_SHIFT 2 /**< Shift value for LEUART_CLKDIV */
|
||||
#define _LEUART_SYNCBUSY_CLKDIV_MASK 0x4UL /**< Bit mask for LEUART_CLKDIV */
|
||||
#define _LEUART_SYNCBUSY_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
|
||||
#define LEUART_SYNCBUSY_CLKDIV_DEFAULT (_LEUART_SYNCBUSY_CLKDIV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
|
||||
#define LEUART_SYNCBUSY_STARTFRAME (0x1UL << 3) /**< LEUARTn_STARTFRAME Register Busy */
|
||||
#define _LEUART_SYNCBUSY_STARTFRAME_SHIFT 3 /**< Shift value for LEUART_STARTFRAME */
|
||||
#define _LEUART_SYNCBUSY_STARTFRAME_MASK 0x8UL /**< Bit mask for LEUART_STARTFRAME */
|
||||
#define _LEUART_SYNCBUSY_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
|
||||
#define LEUART_SYNCBUSY_STARTFRAME_DEFAULT (_LEUART_SYNCBUSY_STARTFRAME_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
|
||||
#define LEUART_SYNCBUSY_SIGFRAME (0x1UL << 4) /**< LEUARTn_SIGFRAME Register Busy */
|
||||
#define _LEUART_SYNCBUSY_SIGFRAME_SHIFT 4 /**< Shift value for LEUART_SIGFRAME */
|
||||
#define _LEUART_SYNCBUSY_SIGFRAME_MASK 0x10UL /**< Bit mask for LEUART_SIGFRAME */
|
||||
#define _LEUART_SYNCBUSY_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
|
||||
#define LEUART_SYNCBUSY_SIGFRAME_DEFAULT (_LEUART_SYNCBUSY_SIGFRAME_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
|
||||
#define LEUART_SYNCBUSY_TXDATAX (0x1UL << 5) /**< LEUARTn_TXDATAX Register Busy */
|
||||
#define _LEUART_SYNCBUSY_TXDATAX_SHIFT 5 /**< Shift value for LEUART_TXDATAX */
|
||||
#define _LEUART_SYNCBUSY_TXDATAX_MASK 0x20UL /**< Bit mask for LEUART_TXDATAX */
|
||||
#define _LEUART_SYNCBUSY_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
|
||||
#define LEUART_SYNCBUSY_TXDATAX_DEFAULT (_LEUART_SYNCBUSY_TXDATAX_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
|
||||
#define LEUART_SYNCBUSY_TXDATA (0x1UL << 6) /**< LEUARTn_TXDATA Register Busy */
|
||||
#define _LEUART_SYNCBUSY_TXDATA_SHIFT 6 /**< Shift value for LEUART_TXDATA */
|
||||
#define _LEUART_SYNCBUSY_TXDATA_MASK 0x40UL /**< Bit mask for LEUART_TXDATA */
|
||||
#define _LEUART_SYNCBUSY_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
|
||||
#define LEUART_SYNCBUSY_TXDATA_DEFAULT (_LEUART_SYNCBUSY_TXDATA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
|
||||
#define LEUART_SYNCBUSY_PULSECTRL (0x1UL << 7) /**< LEUARTn_PULSECTRL Register Busy */
|
||||
#define _LEUART_SYNCBUSY_PULSECTRL_SHIFT 7 /**< Shift value for LEUART_PULSECTRL */
|
||||
#define _LEUART_SYNCBUSY_PULSECTRL_MASK 0x80UL /**< Bit mask for LEUART_PULSECTRL */
|
||||
#define _LEUART_SYNCBUSY_PULSECTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
|
||||
#define LEUART_SYNCBUSY_PULSECTRL_DEFAULT (_LEUART_SYNCBUSY_PULSECTRL_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
|
||||
|
||||
/* Bit fields for LEUART ROUTE */
|
||||
#define _LEUART_ROUTE_RESETVALUE 0x00000000UL /**< Default value for LEUART_ROUTE */
|
||||
#define _LEUART_ROUTE_MASK 0x00000303UL /**< Mask for LEUART_ROUTE */
|
||||
#define LEUART_ROUTE_RXPEN (0x1UL << 0) /**< RX Pin Enable */
|
||||
#define _LEUART_ROUTE_RXPEN_SHIFT 0 /**< Shift value for LEUART_RXPEN */
|
||||
#define _LEUART_ROUTE_RXPEN_MASK 0x1UL /**< Bit mask for LEUART_RXPEN */
|
||||
#define _LEUART_ROUTE_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTE */
|
||||
#define LEUART_ROUTE_RXPEN_DEFAULT (_LEUART_ROUTE_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_ROUTE */
|
||||
#define LEUART_ROUTE_TXPEN (0x1UL << 1) /**< TX Pin Enable */
|
||||
#define _LEUART_ROUTE_TXPEN_SHIFT 1 /**< Shift value for LEUART_TXPEN */
|
||||
#define _LEUART_ROUTE_TXPEN_MASK 0x2UL /**< Bit mask for LEUART_TXPEN */
|
||||
#define _LEUART_ROUTE_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTE */
|
||||
#define LEUART_ROUTE_TXPEN_DEFAULT (_LEUART_ROUTE_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_ROUTE */
|
||||
#define _LEUART_ROUTE_LOCATION_SHIFT 8 /**< Shift value for LEUART_LOCATION */
|
||||
#define _LEUART_ROUTE_LOCATION_MASK 0x300UL /**< Bit mask for LEUART_LOCATION */
|
||||
#define _LEUART_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTE */
|
||||
#define _LEUART_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for LEUART_ROUTE */
|
||||
#define _LEUART_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for LEUART_ROUTE */
|
||||
#define _LEUART_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for LEUART_ROUTE */
|
||||
#define _LEUART_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for LEUART_ROUTE */
|
||||
#define LEUART_ROUTE_LOCATION_DEFAULT (_LEUART_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_ROUTE */
|
||||
#define LEUART_ROUTE_LOCATION_LOC0 (_LEUART_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for LEUART_ROUTE */
|
||||
#define LEUART_ROUTE_LOCATION_LOC1 (_LEUART_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for LEUART_ROUTE */
|
||||
#define LEUART_ROUTE_LOCATION_LOC2 (_LEUART_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for LEUART_ROUTE */
|
||||
#define LEUART_ROUTE_LOCATION_LOC3 (_LEUART_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for LEUART_ROUTE */
|
||||
|
||||
/** @} End of group EFM32G_LEUART */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,259 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief efm32g_msc Register and Bit Field definitions
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_MSC
|
||||
* @{
|
||||
* @brief EFM32G_MSC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Memory System Control Register */
|
||||
__IO uint32_t READCTRL; /**< Read Control Register */
|
||||
__IO uint32_t WRITECTRL; /**< Write Control Register */
|
||||
__IO uint32_t WRITECMD; /**< Write Command Register */
|
||||
__IO uint32_t ADDRB; /**< Page Erase/Write Address Buffer */
|
||||
|
||||
uint32_t RESERVED0[1]; /**< Reserved for future use **/
|
||||
__IO uint32_t WDATA; /**< Write Data Register */
|
||||
__I uint32_t STATUS; /**< Status Register */
|
||||
|
||||
uint32_t RESERVED1[3]; /**< Reserved for future use **/
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IO uint32_t LOCK; /**< Configuration Lock Register */
|
||||
} MSC_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_MSC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/* Bit fields for MSC CTRL */
|
||||
#define _MSC_CTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_CTRL */
|
||||
#define _MSC_CTRL_MASK 0x00000001UL /**< Mask for MSC_CTRL */
|
||||
#define MSC_CTRL_BUSFAULT (0x1UL << 0) /**< Bus Fault Response Enable */
|
||||
#define _MSC_CTRL_BUSFAULT_SHIFT 0 /**< Shift value for MSC_BUSFAULT */
|
||||
#define _MSC_CTRL_BUSFAULT_MASK 0x1UL /**< Bit mask for MSC_BUSFAULT */
|
||||
#define _MSC_CTRL_BUSFAULT_GENERATE 0x00000000UL /**< Mode GENERATE for MSC_CTRL */
|
||||
#define _MSC_CTRL_BUSFAULT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */
|
||||
#define _MSC_CTRL_BUSFAULT_IGNORE 0x00000001UL /**< Mode IGNORE for MSC_CTRL */
|
||||
#define MSC_CTRL_BUSFAULT_GENERATE (_MSC_CTRL_BUSFAULT_GENERATE << 0) /**< Shifted mode GENERATE for MSC_CTRL */
|
||||
#define MSC_CTRL_BUSFAULT_DEFAULT (_MSC_CTRL_BUSFAULT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */
|
||||
#define MSC_CTRL_BUSFAULT_IGNORE (_MSC_CTRL_BUSFAULT_IGNORE << 0) /**< Shifted mode IGNORE for MSC_CTRL */
|
||||
|
||||
/* Bit fields for MSC READCTRL */
|
||||
#define _MSC_READCTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_READCTRL */
|
||||
#define _MSC_READCTRL_MASK 0x00000007UL /**< Mask for MSC_READCTRL */
|
||||
#define _MSC_READCTRL_MODE_SHIFT 0 /**< Shift value for MSC_MODE */
|
||||
#define _MSC_READCTRL_MODE_MASK 0x7UL /**< Bit mask for MSC_MODE */
|
||||
#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */
|
||||
#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */
|
||||
#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */
|
||||
#define _MSC_READCTRL_MODE_WS0SCBTP 0x00000002UL /**< Mode WS0SCBTP for MSC_READCTRL */
|
||||
#define _MSC_READCTRL_MODE_WS1SCBTP 0x00000003UL /**< Mode WS1SCBTP for MSC_READCTRL */
|
||||
#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 0) /**< Shifted mode WS0 for MSC_READCTRL */
|
||||
#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_READCTRL */
|
||||
#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 0) /**< Shifted mode WS1 for MSC_READCTRL */
|
||||
#define MSC_READCTRL_MODE_WS0SCBTP (_MSC_READCTRL_MODE_WS0SCBTP << 0) /**< Shifted mode WS0SCBTP for MSC_READCTRL */
|
||||
#define MSC_READCTRL_MODE_WS1SCBTP (_MSC_READCTRL_MODE_WS1SCBTP << 0) /**< Shifted mode WS1SCBTP for MSC_READCTRL */
|
||||
|
||||
/* Bit fields for MSC WRITECTRL */
|
||||
#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */
|
||||
#define _MSC_WRITECTRL_MASK 0x00000003UL /**< Mask for MSC_WRITECTRL */
|
||||
#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */
|
||||
#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */
|
||||
#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */
|
||||
#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
|
||||
#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
|
||||
#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */
|
||||
#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */
|
||||
#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */
|
||||
#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
|
||||
#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
|
||||
|
||||
/* Bit fields for MSC WRITECMD */
|
||||
#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */
|
||||
#define _MSC_WRITECMD_MASK 0x0000001FUL /**< Mask for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB into ADDR */
|
||||
#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */
|
||||
#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */
|
||||
#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */
|
||||
#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */
|
||||
#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */
|
||||
#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */
|
||||
#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */
|
||||
#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */
|
||||
#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */
|
||||
#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */
|
||||
#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */
|
||||
#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */
|
||||
#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */
|
||||
#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */
|
||||
#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */
|
||||
|
||||
/* Bit fields for MSC ADDRB */
|
||||
#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */
|
||||
#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */
|
||||
#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */
|
||||
#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */
|
||||
#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */
|
||||
#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */
|
||||
|
||||
/* Bit fields for MSC WDATA */
|
||||
#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */
|
||||
#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */
|
||||
#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */
|
||||
#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */
|
||||
#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */
|
||||
#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */
|
||||
|
||||
/* Bit fields for MSC STATUS */
|
||||
#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */
|
||||
#define _MSC_STATUS_MASK 0x0000003FUL /**< Mask for MSC_STATUS */
|
||||
#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */
|
||||
#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */
|
||||
#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */
|
||||
#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
|
||||
#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */
|
||||
#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */
|
||||
#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */
|
||||
#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */
|
||||
#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
|
||||
#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */
|
||||
#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */
|
||||
#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */
|
||||
#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */
|
||||
#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
|
||||
#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */
|
||||
#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */
|
||||
#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */
|
||||
#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */
|
||||
#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */
|
||||
#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */
|
||||
#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */
|
||||
#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */
|
||||
#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */
|
||||
#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
|
||||
#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */
|
||||
#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */
|
||||
#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */
|
||||
#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */
|
||||
#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
|
||||
#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */
|
||||
|
||||
/* Bit fields for MSC IF */
|
||||
#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */
|
||||
#define _MSC_IF_MASK 0x00000003UL /**< Mask for MSC_IF */
|
||||
#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */
|
||||
#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
|
||||
#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
|
||||
#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
|
||||
#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */
|
||||
#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */
|
||||
#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
|
||||
#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
|
||||
#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
|
||||
#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */
|
||||
|
||||
/* Bit fields for MSC IFS */
|
||||
#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */
|
||||
#define _MSC_IFS_MASK 0x00000003UL /**< Mask for MSC_IFS */
|
||||
#define MSC_IFS_ERASE (0x1UL << 0) /**< Erase Done Interrupt Set */
|
||||
#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
|
||||
#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
|
||||
#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
|
||||
#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */
|
||||
#define MSC_IFS_WRITE (0x1UL << 1) /**< Write Done Interrupt Set */
|
||||
#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
|
||||
#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
|
||||
#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
|
||||
#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */
|
||||
|
||||
/* Bit fields for MSC IFC */
|
||||
#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */
|
||||
#define _MSC_IFC_MASK 0x00000003UL /**< Mask for MSC_IFC */
|
||||
#define MSC_IFC_ERASE (0x1UL << 0) /**< Erase Done Interrupt Clear */
|
||||
#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
|
||||
#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
|
||||
#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
|
||||
#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */
|
||||
#define MSC_IFC_WRITE (0x1UL << 1) /**< Write Done Interrupt Clear */
|
||||
#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
|
||||
#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
|
||||
#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
|
||||
#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */
|
||||
|
||||
/* Bit fields for MSC IEN */
|
||||
#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */
|
||||
#define _MSC_IEN_MASK 0x00000003UL /**< Mask for MSC_IEN */
|
||||
#define MSC_IEN_ERASE (0x1UL << 0) /**< Erase Done Interrupt Enable */
|
||||
#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
|
||||
#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
|
||||
#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
|
||||
#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */
|
||||
#define MSC_IEN_WRITE (0x1UL << 1) /**< Write Done Interrupt Enable */
|
||||
#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
|
||||
#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
|
||||
#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
|
||||
#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */
|
||||
|
||||
/* Bit fields for MSC LOCK */
|
||||
#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */
|
||||
#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */
|
||||
#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
|
||||
#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
|
||||
#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */
|
||||
#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */
|
||||
#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */
|
||||
#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */
|
||||
#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */
|
||||
#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */
|
||||
#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */
|
||||
#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */
|
||||
#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */
|
||||
#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */
|
||||
|
||||
/** @} End of group EFM32G_MSC */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,280 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief efm32g_pcnt Register and Bit Field definitions
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_PCNT
|
||||
* @{
|
||||
* @brief EFM32G_PCNT Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__IO uint32_t CMD; /**< Command Register */
|
||||
__I uint32_t STATUS; /**< Status Register */
|
||||
__I uint32_t CNT; /**< Counter Value Register */
|
||||
__I uint32_t TOP; /**< Top Value Register */
|
||||
__IO uint32_t TOPB; /**< Top Value Buffer Register */
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IO uint32_t ROUTE; /**< I/O Routing Register */
|
||||
|
||||
__IO uint32_t FREEZE; /**< Freeze Register */
|
||||
__I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
} PCNT_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_PCNT_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/* Bit fields for PCNT CTRL */
|
||||
#define _PCNT_CTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_MASK 0x0000003FUL /**< Mask for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_MODE_SHIFT 0 /**< Shift value for PCNT_MODE */
|
||||
#define _PCNT_CTRL_MODE_MASK 0x3UL /**< Bit mask for PCNT_MODE */
|
||||
#define _PCNT_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_MODE_DISABLE 0x00000000UL /**< Mode DISABLE for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_MODE_OVSSINGLE 0x00000001UL /**< Mode OVSSINGLE for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_MODE_EXTCLKSINGLE 0x00000002UL /**< Mode EXTCLKSINGLE for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_MODE_EXTCLKQUAD 0x00000003UL /**< Mode EXTCLKQUAD for PCNT_CTRL */
|
||||
#define PCNT_CTRL_MODE_DEFAULT (_PCNT_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_MODE_DISABLE (_PCNT_CTRL_MODE_DISABLE << 0) /**< Shifted mode DISABLE for PCNT_CTRL */
|
||||
#define PCNT_CTRL_MODE_OVSSINGLE (_PCNT_CTRL_MODE_OVSSINGLE << 0) /**< Shifted mode OVSSINGLE for PCNT_CTRL */
|
||||
#define PCNT_CTRL_MODE_EXTCLKSINGLE (_PCNT_CTRL_MODE_EXTCLKSINGLE << 0) /**< Shifted mode EXTCLKSINGLE for PCNT_CTRL */
|
||||
#define PCNT_CTRL_MODE_EXTCLKQUAD (_PCNT_CTRL_MODE_EXTCLKQUAD << 0) /**< Shifted mode EXTCLKQUAD for PCNT_CTRL */
|
||||
#define PCNT_CTRL_CNTDIR (0x1UL << 2) /**< Non-Quadrature Mode Counter Direction Control */
|
||||
#define _PCNT_CTRL_CNTDIR_SHIFT 2 /**< Shift value for PCNT_CNTDIR */
|
||||
#define _PCNT_CTRL_CNTDIR_MASK 0x4UL /**< Bit mask for PCNT_CNTDIR */
|
||||
#define _PCNT_CTRL_CNTDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_CNTDIR_UP 0x00000000UL /**< Mode UP for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_CNTDIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_CTRL */
|
||||
#define PCNT_CTRL_CNTDIR_DEFAULT (_PCNT_CTRL_CNTDIR_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_CNTDIR_UP (_PCNT_CTRL_CNTDIR_UP << 2) /**< Shifted mode UP for PCNT_CTRL */
|
||||
#define PCNT_CTRL_CNTDIR_DOWN (_PCNT_CTRL_CNTDIR_DOWN << 2) /**< Shifted mode DOWN for PCNT_CTRL */
|
||||
#define PCNT_CTRL_EDGE (0x1UL << 3) /**< Edge Select */
|
||||
#define _PCNT_CTRL_EDGE_SHIFT 3 /**< Shift value for PCNT_EDGE */
|
||||
#define _PCNT_CTRL_EDGE_MASK 0x8UL /**< Bit mask for PCNT_EDGE */
|
||||
#define _PCNT_CTRL_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_EDGE_POS 0x00000000UL /**< Mode POS for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_EDGE_NEG 0x00000001UL /**< Mode NEG for PCNT_CTRL */
|
||||
#define PCNT_CTRL_EDGE_DEFAULT (_PCNT_CTRL_EDGE_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_EDGE_POS (_PCNT_CTRL_EDGE_POS << 3) /**< Shifted mode POS for PCNT_CTRL */
|
||||
#define PCNT_CTRL_EDGE_NEG (_PCNT_CTRL_EDGE_NEG << 3) /**< Shifted mode NEG for PCNT_CTRL */
|
||||
#define PCNT_CTRL_FILT (0x1UL << 4) /**< Enable Digital Pulse Width Filter */
|
||||
#define _PCNT_CTRL_FILT_SHIFT 4 /**< Shift value for PCNT_FILT */
|
||||
#define _PCNT_CTRL_FILT_MASK 0x10UL /**< Bit mask for PCNT_FILT */
|
||||
#define _PCNT_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_FILT_DEFAULT (_PCNT_CTRL_FILT_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_RSTEN (0x1UL << 5) /**< Enable PCNT Clock Domain Reset */
|
||||
#define _PCNT_CTRL_RSTEN_SHIFT 5 /**< Shift value for PCNT_RSTEN */
|
||||
#define _PCNT_CTRL_RSTEN_MASK 0x20UL /**< Bit mask for PCNT_RSTEN */
|
||||
#define _PCNT_CTRL_RSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_RSTEN_DEFAULT (_PCNT_CTRL_RSTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_CTRL */
|
||||
|
||||
/* Bit fields for PCNT CMD */
|
||||
#define _PCNT_CMD_RESETVALUE 0x00000000UL /**< Default value for PCNT_CMD */
|
||||
#define _PCNT_CMD_MASK 0x00000003UL /**< Mask for PCNT_CMD */
|
||||
#define PCNT_CMD_LCNTIM (0x1UL << 0) /**< Load CNT Immediately */
|
||||
#define _PCNT_CMD_LCNTIM_SHIFT 0 /**< Shift value for PCNT_LCNTIM */
|
||||
#define _PCNT_CMD_LCNTIM_MASK 0x1UL /**< Bit mask for PCNT_LCNTIM */
|
||||
#define _PCNT_CMD_LCNTIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */
|
||||
#define PCNT_CMD_LCNTIM_DEFAULT (_PCNT_CMD_LCNTIM_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CMD */
|
||||
#define PCNT_CMD_LTOPBIM (0x1UL << 1) /**< Load TOPB Immediately */
|
||||
#define _PCNT_CMD_LTOPBIM_SHIFT 1 /**< Shift value for PCNT_LTOPBIM */
|
||||
#define _PCNT_CMD_LTOPBIM_MASK 0x2UL /**< Bit mask for PCNT_LTOPBIM */
|
||||
#define _PCNT_CMD_LTOPBIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */
|
||||
#define PCNT_CMD_LTOPBIM_DEFAULT (_PCNT_CMD_LTOPBIM_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_CMD */
|
||||
|
||||
/* Bit fields for PCNT STATUS */
|
||||
#define _PCNT_STATUS_RESETVALUE 0x00000000UL /**< Default value for PCNT_STATUS */
|
||||
#define _PCNT_STATUS_MASK 0x00000001UL /**< Mask for PCNT_STATUS */
|
||||
#define PCNT_STATUS_DIR (0x1UL << 0) /**< Current Counter Direction */
|
||||
#define _PCNT_STATUS_DIR_SHIFT 0 /**< Shift value for PCNT_DIR */
|
||||
#define _PCNT_STATUS_DIR_MASK 0x1UL /**< Bit mask for PCNT_DIR */
|
||||
#define _PCNT_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */
|
||||
#define _PCNT_STATUS_DIR_UP 0x00000000UL /**< Mode UP for PCNT_STATUS */
|
||||
#define _PCNT_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_STATUS */
|
||||
#define PCNT_STATUS_DIR_DEFAULT (_PCNT_STATUS_DIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_STATUS */
|
||||
#define PCNT_STATUS_DIR_UP (_PCNT_STATUS_DIR_UP << 0) /**< Shifted mode UP for PCNT_STATUS */
|
||||
#define PCNT_STATUS_DIR_DOWN (_PCNT_STATUS_DIR_DOWN << 0) /**< Shifted mode DOWN for PCNT_STATUS */
|
||||
|
||||
/* Bit fields for PCNT CNT */
|
||||
#define _PCNT_CNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_CNT */
|
||||
#define _PCNT_CNT_MASK 0x000000FFUL /**< Mask for PCNT_CNT */
|
||||
#define _PCNT_CNT_CNT_SHIFT 0 /**< Shift value for PCNT_CNT */
|
||||
#define _PCNT_CNT_CNT_MASK 0xFFUL /**< Bit mask for PCNT_CNT */
|
||||
#define _PCNT_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CNT */
|
||||
#define PCNT_CNT_CNT_DEFAULT (_PCNT_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CNT */
|
||||
|
||||
/* Bit fields for PCNT TOP */
|
||||
#define _PCNT_TOP_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOP */
|
||||
#define _PCNT_TOP_MASK 0x000000FFUL /**< Mask for PCNT_TOP */
|
||||
#define _PCNT_TOP_TOP_SHIFT 0 /**< Shift value for PCNT_TOP */
|
||||
#define _PCNT_TOP_TOP_MASK 0xFFUL /**< Bit mask for PCNT_TOP */
|
||||
#define _PCNT_TOP_TOP_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOP */
|
||||
#define PCNT_TOP_TOP_DEFAULT (_PCNT_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOP */
|
||||
|
||||
/* Bit fields for PCNT TOPB */
|
||||
#define _PCNT_TOPB_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOPB */
|
||||
#define _PCNT_TOPB_MASK 0x000000FFUL /**< Mask for PCNT_TOPB */
|
||||
#define _PCNT_TOPB_TOPB_SHIFT 0 /**< Shift value for PCNT_TOPB */
|
||||
#define _PCNT_TOPB_TOPB_MASK 0xFFUL /**< Bit mask for PCNT_TOPB */
|
||||
#define _PCNT_TOPB_TOPB_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOPB */
|
||||
#define PCNT_TOPB_TOPB_DEFAULT (_PCNT_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOPB */
|
||||
|
||||
/* Bit fields for PCNT IF */
|
||||
#define _PCNT_IF_RESETVALUE 0x00000000UL /**< Default value for PCNT_IF */
|
||||
#define _PCNT_IF_MASK 0x00000007UL /**< Mask for PCNT_IF */
|
||||
#define PCNT_IF_UF (0x1UL << 0) /**< Underflow Interrupt Read Flag */
|
||||
#define _PCNT_IF_UF_SHIFT 0 /**< Shift value for PCNT_UF */
|
||||
#define _PCNT_IF_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */
|
||||
#define _PCNT_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
|
||||
#define PCNT_IF_UF_DEFAULT (_PCNT_IF_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IF */
|
||||
#define PCNT_IF_OF (0x1UL << 1) /**< Overflow Interrupt Read Flag */
|
||||
#define _PCNT_IF_OF_SHIFT 1 /**< Shift value for PCNT_OF */
|
||||
#define _PCNT_IF_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */
|
||||
#define _PCNT_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
|
||||
#define PCNT_IF_OF_DEFAULT (_PCNT_IF_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IF */
|
||||
#define PCNT_IF_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */
|
||||
#define _PCNT_IF_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */
|
||||
#define _PCNT_IF_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */
|
||||
#define _PCNT_IF_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
|
||||
#define PCNT_IF_DIRCNG_DEFAULT (_PCNT_IF_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IF */
|
||||
|
||||
/* Bit fields for PCNT IFS */
|
||||
#define _PCNT_IFS_RESETVALUE 0x00000000UL /**< Default value for PCNT_IFS */
|
||||
#define _PCNT_IFS_MASK 0x00000007UL /**< Mask for PCNT_IFS */
|
||||
#define PCNT_IFS_UF (0x1UL << 0) /**< Underflow interrupt set */
|
||||
#define _PCNT_IFS_UF_SHIFT 0 /**< Shift value for PCNT_UF */
|
||||
#define _PCNT_IFS_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */
|
||||
#define _PCNT_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */
|
||||
#define PCNT_IFS_UF_DEFAULT (_PCNT_IFS_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IFS */
|
||||
#define PCNT_IFS_OF (0x1UL << 1) /**< Overflow Interrupt Set */
|
||||
#define _PCNT_IFS_OF_SHIFT 1 /**< Shift value for PCNT_OF */
|
||||
#define _PCNT_IFS_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */
|
||||
#define _PCNT_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */
|
||||
#define PCNT_IFS_OF_DEFAULT (_PCNT_IFS_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IFS */
|
||||
#define PCNT_IFS_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Set */
|
||||
#define _PCNT_IFS_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */
|
||||
#define _PCNT_IFS_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */
|
||||
#define _PCNT_IFS_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */
|
||||
#define PCNT_IFS_DIRCNG_DEFAULT (_PCNT_IFS_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IFS */
|
||||
|
||||
/* Bit fields for PCNT IFC */
|
||||
#define _PCNT_IFC_RESETVALUE 0x00000000UL /**< Default value for PCNT_IFC */
|
||||
#define _PCNT_IFC_MASK 0x00000007UL /**< Mask for PCNT_IFC */
|
||||
#define PCNT_IFC_UF (0x1UL << 0) /**< Underflow Interrupt Clear */
|
||||
#define _PCNT_IFC_UF_SHIFT 0 /**< Shift value for PCNT_UF */
|
||||
#define _PCNT_IFC_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */
|
||||
#define _PCNT_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */
|
||||
#define PCNT_IFC_UF_DEFAULT (_PCNT_IFC_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IFC */
|
||||
#define PCNT_IFC_OF (0x1UL << 1) /**< Overflow Interrupt Clear */
|
||||
#define _PCNT_IFC_OF_SHIFT 1 /**< Shift value for PCNT_OF */
|
||||
#define _PCNT_IFC_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */
|
||||
#define _PCNT_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */
|
||||
#define PCNT_IFC_OF_DEFAULT (_PCNT_IFC_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IFC */
|
||||
#define PCNT_IFC_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Clear */
|
||||
#define _PCNT_IFC_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */
|
||||
#define _PCNT_IFC_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */
|
||||
#define _PCNT_IFC_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */
|
||||
#define PCNT_IFC_DIRCNG_DEFAULT (_PCNT_IFC_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IFC */
|
||||
|
||||
/* Bit fields for PCNT IEN */
|
||||
#define _PCNT_IEN_RESETVALUE 0x00000000UL /**< Default value for PCNT_IEN */
|
||||
#define _PCNT_IEN_MASK 0x00000007UL /**< Mask for PCNT_IEN */
|
||||
#define PCNT_IEN_UF (0x1UL << 0) /**< Underflow Interrupt Enable */
|
||||
#define _PCNT_IEN_UF_SHIFT 0 /**< Shift value for PCNT_UF */
|
||||
#define _PCNT_IEN_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */
|
||||
#define _PCNT_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
|
||||
#define PCNT_IEN_UF_DEFAULT (_PCNT_IEN_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IEN */
|
||||
#define PCNT_IEN_OF (0x1UL << 1) /**< Overflow Interrupt Enable */
|
||||
#define _PCNT_IEN_OF_SHIFT 1 /**< Shift value for PCNT_OF */
|
||||
#define _PCNT_IEN_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */
|
||||
#define _PCNT_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
|
||||
#define PCNT_IEN_OF_DEFAULT (_PCNT_IEN_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IEN */
|
||||
#define PCNT_IEN_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Enable */
|
||||
#define _PCNT_IEN_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */
|
||||
#define _PCNT_IEN_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */
|
||||
#define _PCNT_IEN_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
|
||||
#define PCNT_IEN_DIRCNG_DEFAULT (_PCNT_IEN_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IEN */
|
||||
|
||||
/* Bit fields for PCNT ROUTE */
|
||||
#define _PCNT_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PCNT_ROUTE */
|
||||
#define _PCNT_ROUTE_MASK 0x00000300UL /**< Mask for PCNT_ROUTE */
|
||||
#define _PCNT_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PCNT_LOCATION */
|
||||
#define _PCNT_ROUTE_LOCATION_MASK 0x300UL /**< Bit mask for PCNT_LOCATION */
|
||||
#define _PCNT_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_ROUTE */
|
||||
#define _PCNT_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PCNT_ROUTE */
|
||||
#define _PCNT_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PCNT_ROUTE */
|
||||
#define _PCNT_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for PCNT_ROUTE */
|
||||
#define PCNT_ROUTE_LOCATION_DEFAULT (_PCNT_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_ROUTE */
|
||||
#define PCNT_ROUTE_LOCATION_LOC0 (_PCNT_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PCNT_ROUTE */
|
||||
#define PCNT_ROUTE_LOCATION_LOC1 (_PCNT_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PCNT_ROUTE */
|
||||
#define PCNT_ROUTE_LOCATION_LOC2 (_PCNT_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for PCNT_ROUTE */
|
||||
|
||||
/* Bit fields for PCNT FREEZE */
|
||||
#define _PCNT_FREEZE_RESETVALUE 0x00000000UL /**< Default value for PCNT_FREEZE */
|
||||
#define _PCNT_FREEZE_MASK 0x00000001UL /**< Mask for PCNT_FREEZE */
|
||||
#define PCNT_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
|
||||
#define _PCNT_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for PCNT_REGFREEZE */
|
||||
#define _PCNT_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for PCNT_REGFREEZE */
|
||||
#define _PCNT_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_FREEZE */
|
||||
#define _PCNT_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for PCNT_FREEZE */
|
||||
#define _PCNT_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for PCNT_FREEZE */
|
||||
#define PCNT_FREEZE_REGFREEZE_DEFAULT (_PCNT_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_FREEZE */
|
||||
#define PCNT_FREEZE_REGFREEZE_UPDATE (_PCNT_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for PCNT_FREEZE */
|
||||
#define PCNT_FREEZE_REGFREEZE_FREEZE (_PCNT_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for PCNT_FREEZE */
|
||||
|
||||
/* Bit fields for PCNT SYNCBUSY */
|
||||
#define _PCNT_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for PCNT_SYNCBUSY */
|
||||
#define _PCNT_SYNCBUSY_MASK 0x00000007UL /**< Mask for PCNT_SYNCBUSY */
|
||||
#define PCNT_SYNCBUSY_CTRL (0x1UL << 0) /**< PCNTn_CTRL Register Busy */
|
||||
#define _PCNT_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for PCNT_CTRL */
|
||||
#define _PCNT_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for PCNT_CTRL */
|
||||
#define _PCNT_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */
|
||||
#define PCNT_SYNCBUSY_CTRL_DEFAULT (_PCNT_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
|
||||
#define PCNT_SYNCBUSY_CMD (0x1UL << 1) /**< PCNTn_CMD Register Busy */
|
||||
#define _PCNT_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for PCNT_CMD */
|
||||
#define _PCNT_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for PCNT_CMD */
|
||||
#define _PCNT_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */
|
||||
#define PCNT_SYNCBUSY_CMD_DEFAULT (_PCNT_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
|
||||
#define PCNT_SYNCBUSY_TOPB (0x1UL << 2) /**< PCNTn_TOPB Register Busy */
|
||||
#define _PCNT_SYNCBUSY_TOPB_SHIFT 2 /**< Shift value for PCNT_TOPB */
|
||||
#define _PCNT_SYNCBUSY_TOPB_MASK 0x4UL /**< Bit mask for PCNT_TOPB */
|
||||
#define _PCNT_SYNCBUSY_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */
|
||||
#define PCNT_SYNCBUSY_TOPB_DEFAULT (_PCNT_SYNCBUSY_TOPB_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
|
||||
|
||||
/** @} End of group EFM32G_PCNT */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,295 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief efm32g_prs Register and Bit Field definitions
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_PRS
|
||||
* @{
|
||||
* @brief EFM32G_PRS Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t SWPULSE; /**< Software Pulse Register */
|
||||
__IO uint32_t SWLEVEL; /**< Software Level Register */
|
||||
|
||||
uint32_t RESERVED0[2]; /**< Reserved registers */
|
||||
|
||||
PRS_CH_TypeDef CH[8]; /**< Channel registers */
|
||||
} PRS_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_PRS_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/* Bit fields for PRS SWPULSE */
|
||||
#define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */
|
||||
#define _PRS_SWPULSE_MASK 0x000000FFUL /**< Mask for PRS_SWPULSE */
|
||||
#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */
|
||||
#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */
|
||||
#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */
|
||||
#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
|
||||
#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */
|
||||
#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */
|
||||
#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */
|
||||
#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */
|
||||
#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
|
||||
#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */
|
||||
#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */
|
||||
#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */
|
||||
#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */
|
||||
#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
|
||||
#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */
|
||||
#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */
|
||||
#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */
|
||||
#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */
|
||||
#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
|
||||
#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */
|
||||
#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */
|
||||
#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */
|
||||
#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */
|
||||
#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
|
||||
#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */
|
||||
#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */
|
||||
#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */
|
||||
#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */
|
||||
#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
|
||||
#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */
|
||||
#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */
|
||||
#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */
|
||||
#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */
|
||||
#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
|
||||
#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */
|
||||
#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */
|
||||
#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */
|
||||
#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */
|
||||
#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
|
||||
#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */
|
||||
|
||||
/* Bit fields for PRS SWLEVEL */
|
||||
#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */
|
||||
#define _PRS_SWLEVEL_MASK 0x000000FFUL /**< Mask for PRS_SWLEVEL */
|
||||
#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */
|
||||
#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */
|
||||
#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */
|
||||
#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
|
||||
#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
|
||||
#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */
|
||||
#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */
|
||||
#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */
|
||||
#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
|
||||
#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
|
||||
#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */
|
||||
#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */
|
||||
#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */
|
||||
#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
|
||||
#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
|
||||
#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */
|
||||
#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */
|
||||
#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */
|
||||
#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
|
||||
#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
|
||||
#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */
|
||||
#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */
|
||||
#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */
|
||||
#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
|
||||
#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
|
||||
#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */
|
||||
#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */
|
||||
#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */
|
||||
#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
|
||||
#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
|
||||
#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */
|
||||
#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */
|
||||
#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */
|
||||
#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
|
||||
#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
|
||||
#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */
|
||||
#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */
|
||||
#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */
|
||||
#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
|
||||
#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
|
||||
|
||||
/* Bit fields for PRS CH_CTRL */
|
||||
#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_MASK 0x033F0007UL /**< Mask for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL /**< Mode UART0TXC for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL /**< Mode UART0RXDATAV for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) /**< Shifted mode UART0TXC for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */
|
||||
#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */
|
||||
#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SOURCESEL_UART0 0x00000029UL /**< Mode UART0 for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 16) /**< Shifted mode UART0 for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */
|
||||
#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */
|
||||
#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */
|
||||
#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */
|
||||
#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */
|
||||
|
||||
/** @} End of group EFM32G_PRS */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief efm32g_prs_.h Register and Bit Field definitions
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @brief PRS_CH EFM32G PRS CH
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Channel Control Register */
|
||||
} PRS_CH_TypeDef;
|
||||
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief efm32g_prs_signals Register and Bit Field definitions
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @addtogroup EFM32G_PRS_Signals
|
||||
* @{
|
||||
* @brief PRS Signal names
|
||||
*****************************************************************************/
|
||||
|
||||
#define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */
|
||||
#define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */
|
||||
#define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */
|
||||
#define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */
|
||||
#define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */
|
||||
#define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */
|
||||
#define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */
|
||||
#define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */
|
||||
#define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */
|
||||
#define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */
|
||||
#define PRS_USART1_IRTX ((17 << 16) + 0) /**< PRS USART 1 IRDA out */
|
||||
#define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */
|
||||
#define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */
|
||||
#define PRS_USART2_IRTX ((18 << 16) + 0) /**< PRS USART 2 IRDA out */
|
||||
#define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */
|
||||
#define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */
|
||||
#define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */
|
||||
#define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */
|
||||
#define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */
|
||||
#define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */
|
||||
#define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */
|
||||
#define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */
|
||||
#define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */
|
||||
#define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */
|
||||
#define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */
|
||||
#define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */
|
||||
#define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */
|
||||
#define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */
|
||||
#define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */
|
||||
#define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */
|
||||
#define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */
|
||||
#define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */
|
||||
#define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */
|
||||
#define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */
|
||||
#define PRS_UART0_IRTX ((41 << 16) + 0) /**< PRS USART 0 IRDA out */
|
||||
#define PRS_UART0_TXC ((41 << 16) + 1) /**< PRS USART 0 TX complete */
|
||||
#define PRS_UART0_RXDATAV ((41 << 16) + 2) /**< PRS USART 0 RX Data Valid */
|
||||
#define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */
|
||||
#define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */
|
||||
#define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */
|
||||
#define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */
|
||||
#define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */
|
||||
#define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */
|
||||
#define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */
|
||||
#define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */
|
||||
#define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */
|
||||
#define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */
|
||||
#define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */
|
||||
#define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */
|
||||
#define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */
|
||||
#define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */
|
||||
#define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */
|
||||
#define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */
|
||||
|
||||
/** @} End of group EFM32G_PRS */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,109 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief efm32g_rmu Register and Bit Field definitions
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_RMU
|
||||
* @{
|
||||
* @brief EFM32G_RMU Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__I uint32_t RSTCAUSE; /**< Reset Cause Register */
|
||||
__O uint32_t CMD; /**< Command Register */
|
||||
} RMU_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_RMU_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/* Bit fields for RMU CTRL */
|
||||
#define _RMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for RMU_CTRL */
|
||||
#define _RMU_CTRL_MASK 0x00000001UL /**< Mask for RMU_CTRL */
|
||||
#define RMU_CTRL_LOCKUPRDIS (0x1UL << 0) /**< Lockup Reset Disable */
|
||||
#define _RMU_CTRL_LOCKUPRDIS_SHIFT 0 /**< Shift value for RMU_LOCKUPRDIS */
|
||||
#define _RMU_CTRL_LOCKUPRDIS_MASK 0x1UL /**< Bit mask for RMU_LOCKUPRDIS */
|
||||
#define _RMU_CTRL_LOCKUPRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CTRL */
|
||||
#define RMU_CTRL_LOCKUPRDIS_DEFAULT (_RMU_CTRL_LOCKUPRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CTRL */
|
||||
|
||||
/* Bit fields for RMU RSTCAUSE */
|
||||
#define _RMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for RMU_RSTCAUSE */
|
||||
#define _RMU_RSTCAUSE_MASK 0x0000007FUL /**< Mask for RMU_RSTCAUSE */
|
||||
#define RMU_RSTCAUSE_PORST (0x1UL << 0) /**< Power On Reset */
|
||||
#define _RMU_RSTCAUSE_PORST_SHIFT 0 /**< Shift value for RMU_PORST */
|
||||
#define _RMU_RSTCAUSE_PORST_MASK 0x1UL /**< Bit mask for RMU_PORST */
|
||||
#define _RMU_RSTCAUSE_PORST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
|
||||
#define RMU_RSTCAUSE_PORST_DEFAULT (_RMU_RSTCAUSE_PORST_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
|
||||
#define RMU_RSTCAUSE_BODUNREGRST (0x1UL << 1) /**< Brown Out Detector Unregulated Domain Reset */
|
||||
#define _RMU_RSTCAUSE_BODUNREGRST_SHIFT 1 /**< Shift value for RMU_BODUNREGRST */
|
||||
#define _RMU_RSTCAUSE_BODUNREGRST_MASK 0x2UL /**< Bit mask for RMU_BODUNREGRST */
|
||||
#define _RMU_RSTCAUSE_BODUNREGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
|
||||
#define RMU_RSTCAUSE_BODUNREGRST_DEFAULT (_RMU_RSTCAUSE_BODUNREGRST_DEFAULT << 1) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
|
||||
#define RMU_RSTCAUSE_BODREGRST (0x1UL << 2) /**< Brown Out Detector Regulated Domain Reset */
|
||||
#define _RMU_RSTCAUSE_BODREGRST_SHIFT 2 /**< Shift value for RMU_BODREGRST */
|
||||
#define _RMU_RSTCAUSE_BODREGRST_MASK 0x4UL /**< Bit mask for RMU_BODREGRST */
|
||||
#define _RMU_RSTCAUSE_BODREGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
|
||||
#define RMU_RSTCAUSE_BODREGRST_DEFAULT (_RMU_RSTCAUSE_BODREGRST_DEFAULT << 2) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
|
||||
#define RMU_RSTCAUSE_EXTRST (0x1UL << 3) /**< External Pin Reset */
|
||||
#define _RMU_RSTCAUSE_EXTRST_SHIFT 3 /**< Shift value for RMU_EXTRST */
|
||||
#define _RMU_RSTCAUSE_EXTRST_MASK 0x8UL /**< Bit mask for RMU_EXTRST */
|
||||
#define _RMU_RSTCAUSE_EXTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
|
||||
#define RMU_RSTCAUSE_EXTRST_DEFAULT (_RMU_RSTCAUSE_EXTRST_DEFAULT << 3) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
|
||||
#define RMU_RSTCAUSE_WDOGRST (0x1UL << 4) /**< Watchdog Reset */
|
||||
#define _RMU_RSTCAUSE_WDOGRST_SHIFT 4 /**< Shift value for RMU_WDOGRST */
|
||||
#define _RMU_RSTCAUSE_WDOGRST_MASK 0x10UL /**< Bit mask for RMU_WDOGRST */
|
||||
#define _RMU_RSTCAUSE_WDOGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
|
||||
#define RMU_RSTCAUSE_WDOGRST_DEFAULT (_RMU_RSTCAUSE_WDOGRST_DEFAULT << 4) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
|
||||
#define RMU_RSTCAUSE_LOCKUPRST (0x1UL << 5) /**< LOCKUP Reset */
|
||||
#define _RMU_RSTCAUSE_LOCKUPRST_SHIFT 5 /**< Shift value for RMU_LOCKUPRST */
|
||||
#define _RMU_RSTCAUSE_LOCKUPRST_MASK 0x20UL /**< Bit mask for RMU_LOCKUPRST */
|
||||
#define _RMU_RSTCAUSE_LOCKUPRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
|
||||
#define RMU_RSTCAUSE_LOCKUPRST_DEFAULT (_RMU_RSTCAUSE_LOCKUPRST_DEFAULT << 5) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
|
||||
#define RMU_RSTCAUSE_SYSREQRST (0x1UL << 6) /**< System Request Reset */
|
||||
#define _RMU_RSTCAUSE_SYSREQRST_SHIFT 6 /**< Shift value for RMU_SYSREQRST */
|
||||
#define _RMU_RSTCAUSE_SYSREQRST_MASK 0x40UL /**< Bit mask for RMU_SYSREQRST */
|
||||
#define _RMU_RSTCAUSE_SYSREQRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
|
||||
#define RMU_RSTCAUSE_SYSREQRST_DEFAULT (_RMU_RSTCAUSE_SYSREQRST_DEFAULT << 6) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
|
||||
|
||||
/* Bit fields for RMU CMD */
|
||||
#define _RMU_CMD_RESETVALUE 0x00000000UL /**< Default value for RMU_CMD */
|
||||
#define _RMU_CMD_MASK 0x00000001UL /**< Mask for RMU_CMD */
|
||||
#define RMU_CMD_RCCLR (0x1UL << 0) /**< Reset Cause Clear */
|
||||
#define _RMU_CMD_RCCLR_SHIFT 0 /**< Shift value for RMU_RCCLR */
|
||||
#define _RMU_CMD_RCCLR_MASK 0x1UL /**< Bit mask for RMU_RCCLR */
|
||||
#define _RMU_CMD_RCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CMD */
|
||||
#define RMU_CMD_RCCLR_DEFAULT (_RMU_CMD_RCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CMD */
|
||||
|
||||
/** @} End of group EFM32G_RMU */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief efm32g_romtable Register and Bit Field definitions
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_ROMTABLE
|
||||
* @{
|
||||
* @brief Chip Information, Revision numbers
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__I uint32_t PID4; /**< JEP_106_BANK */
|
||||
__I uint32_t PID5; /**< Unused */
|
||||
__I uint32_t PID6; /**< Unused */
|
||||
__I uint32_t PID7; /**< Unused */
|
||||
__I uint32_t PID0; /**< Chip family LSB, chip major revision */
|
||||
__I uint32_t PID1; /**< JEP_106_NO, Chip family MSB */
|
||||
__I uint32_t PID2; /**< Chip minor rev MSB, JEP_106_PRESENT, JEP_106_NO */
|
||||
__I uint32_t PID3; /**< Chip minor rev LSB */
|
||||
__I uint32_t CID0; /**< Unused */
|
||||
} ROMTABLE_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_ROMTABLE_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
/* Bit fields for EFM32G_ROMTABLE */
|
||||
#define _ROMTABLE_PID0_FAMILYLSB_MASK 0x000000C0UL /**< Least Significant Bits [1:0] of CHIP FAMILY, mask */
|
||||
#define _ROMTABLE_PID0_FAMILYLSB_SHIFT 6 /**< Least Significant Bits [1:0] of CHIP FAMILY, shift */
|
||||
#define _ROMTABLE_PID0_REVMAJOR_MASK 0x0000003FUL /**< CHIP MAJOR Revison, mask */
|
||||
#define _ROMTABLE_PID0_REVMAJOR_SHIFT 0 /**< CHIP MAJOR Revison, shift */
|
||||
#define _ROMTABLE_PID1_FAMILYMSB_MASK 0x0000000FUL /**< Most Significant Bits [5:2] of CHIP FAMILY, mask */
|
||||
#define _ROMTABLE_PID1_FAMILYMSB_SHIFT 0 /**< Most Significant Bits [5:2] of CHIP FAMILY, shift */
|
||||
#define _ROMTABLE_PID2_REVMINORMSB_MASK 0x000000F0UL /**< Most Significant Bits [7:4] of CHIP MINOR revision, mask */
|
||||
#define _ROMTABLE_PID2_REVMINORMSB_SHIFT 4 /**< Most Significant Bits [7:4] of CHIP MINOR revision, mask */
|
||||
#define _ROMTABLE_PID3_REVMINORLSB_MASK 0x000000F0UL /**< Least Significant Bits [3:0] of CHIP MINOR revision, mask */
|
||||
#define _ROMTABLE_PID3_REVMINORLSB_SHIFT 4 /**< Least Significant Bits [3:0] of CHIP MINOR revision, shift */
|
||||
|
||||
/** @} End of group EFM32G_ROMTABLE */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,215 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief efm32g_rtc Register and Bit Field definitions
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_RTC
|
||||
* @{
|
||||
* @brief EFM32G_RTC Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__I uint32_t CNT; /**< Counter Value Register */
|
||||
__IO uint32_t COMP0; /**< Compare Value Register 0 */
|
||||
__IO uint32_t COMP1; /**< Compare Value Register 1 */
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
|
||||
__IO uint32_t FREEZE; /**< Freeze Register */
|
||||
__I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
} RTC_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_RTC_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/* Bit fields for RTC CTRL */
|
||||
#define _RTC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTC_CTRL */
|
||||
#define _RTC_CTRL_MASK 0x00000007UL /**< Mask for RTC_CTRL */
|
||||
#define RTC_CTRL_EN (0x1UL << 0) /**< RTC Enable */
|
||||
#define _RTC_CTRL_EN_SHIFT 0 /**< Shift value for RTC_EN */
|
||||
#define _RTC_CTRL_EN_MASK 0x1UL /**< Bit mask for RTC_EN */
|
||||
#define _RTC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */
|
||||
#define RTC_CTRL_EN_DEFAULT (_RTC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_CTRL */
|
||||
#define RTC_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */
|
||||
#define _RTC_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for RTC_DEBUGRUN */
|
||||
#define _RTC_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for RTC_DEBUGRUN */
|
||||
#define _RTC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */
|
||||
#define RTC_CTRL_DEBUGRUN_DEFAULT (_RTC_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_CTRL */
|
||||
#define RTC_CTRL_COMP0TOP (0x1UL << 2) /**< Compare Channel 0 is Top Value */
|
||||
#define _RTC_CTRL_COMP0TOP_SHIFT 2 /**< Shift value for RTC_COMP0TOP */
|
||||
#define _RTC_CTRL_COMP0TOP_MASK 0x4UL /**< Bit mask for RTC_COMP0TOP */
|
||||
#define _RTC_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */
|
||||
#define _RTC_CTRL_COMP0TOP_DISABLE 0x00000000UL /**< Mode DISABLE for RTC_CTRL */
|
||||
#define _RTC_CTRL_COMP0TOP_ENABLE 0x00000001UL /**< Mode ENABLE for RTC_CTRL */
|
||||
#define RTC_CTRL_COMP0TOP_DEFAULT (_RTC_CTRL_COMP0TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_CTRL */
|
||||
#define RTC_CTRL_COMP0TOP_DISABLE (_RTC_CTRL_COMP0TOP_DISABLE << 2) /**< Shifted mode DISABLE for RTC_CTRL */
|
||||
#define RTC_CTRL_COMP0TOP_ENABLE (_RTC_CTRL_COMP0TOP_ENABLE << 2) /**< Shifted mode ENABLE for RTC_CTRL */
|
||||
|
||||
/* Bit fields for RTC CNT */
|
||||
#define _RTC_CNT_RESETVALUE 0x00000000UL /**< Default value for RTC_CNT */
|
||||
#define _RTC_CNT_MASK 0x00FFFFFFUL /**< Mask for RTC_CNT */
|
||||
#define _RTC_CNT_CNT_SHIFT 0 /**< Shift value for RTC_CNT */
|
||||
#define _RTC_CNT_CNT_MASK 0xFFFFFFUL /**< Bit mask for RTC_CNT */
|
||||
#define _RTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CNT */
|
||||
#define RTC_CNT_CNT_DEFAULT (_RTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_CNT */
|
||||
|
||||
/* Bit fields for RTC COMP0 */
|
||||
#define _RTC_COMP0_RESETVALUE 0x00000000UL /**< Default value for RTC_COMP0 */
|
||||
#define _RTC_COMP0_MASK 0x00FFFFFFUL /**< Mask for RTC_COMP0 */
|
||||
#define _RTC_COMP0_COMP0_SHIFT 0 /**< Shift value for RTC_COMP0 */
|
||||
#define _RTC_COMP0_COMP0_MASK 0xFFFFFFUL /**< Bit mask for RTC_COMP0 */
|
||||
#define _RTC_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_COMP0 */
|
||||
#define RTC_COMP0_COMP0_DEFAULT (_RTC_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_COMP0 */
|
||||
|
||||
/* Bit fields for RTC COMP1 */
|
||||
#define _RTC_COMP1_RESETVALUE 0x00000000UL /**< Default value for RTC_COMP1 */
|
||||
#define _RTC_COMP1_MASK 0x00FFFFFFUL /**< Mask for RTC_COMP1 */
|
||||
#define _RTC_COMP1_COMP1_SHIFT 0 /**< Shift value for RTC_COMP1 */
|
||||
#define _RTC_COMP1_COMP1_MASK 0xFFFFFFUL /**< Bit mask for RTC_COMP1 */
|
||||
#define _RTC_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_COMP1 */
|
||||
#define RTC_COMP1_COMP1_DEFAULT (_RTC_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_COMP1 */
|
||||
|
||||
/* Bit fields for RTC IF */
|
||||
#define _RTC_IF_RESETVALUE 0x00000000UL /**< Default value for RTC_IF */
|
||||
#define _RTC_IF_MASK 0x00000007UL /**< Mask for RTC_IF */
|
||||
#define RTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */
|
||||
#define _RTC_IF_OF_SHIFT 0 /**< Shift value for RTC_OF */
|
||||
#define _RTC_IF_OF_MASK 0x1UL /**< Bit mask for RTC_OF */
|
||||
#define _RTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */
|
||||
#define RTC_IF_OF_DEFAULT (_RTC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IF */
|
||||
#define RTC_IF_COMP0 (0x1UL << 1) /**< Compare Match 0 Interrupt Flag */
|
||||
#define _RTC_IF_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */
|
||||
#define _RTC_IF_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */
|
||||
#define _RTC_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */
|
||||
#define RTC_IF_COMP0_DEFAULT (_RTC_IF_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IF */
|
||||
#define RTC_IF_COMP1 (0x1UL << 2) /**< Compare Match 1 Interrupt Flag */
|
||||
#define _RTC_IF_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */
|
||||
#define _RTC_IF_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */
|
||||
#define _RTC_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */
|
||||
#define RTC_IF_COMP1_DEFAULT (_RTC_IF_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IF */
|
||||
|
||||
/* Bit fields for RTC IFS */
|
||||
#define _RTC_IFS_RESETVALUE 0x00000000UL /**< Default value for RTC_IFS */
|
||||
#define _RTC_IFS_MASK 0x00000007UL /**< Mask for RTC_IFS */
|
||||
#define RTC_IFS_OF (0x1UL << 0) /**< Set Overflow Interrupt Flag */
|
||||
#define _RTC_IFS_OF_SHIFT 0 /**< Shift value for RTC_OF */
|
||||
#define _RTC_IFS_OF_MASK 0x1UL /**< Bit mask for RTC_OF */
|
||||
#define _RTC_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */
|
||||
#define RTC_IFS_OF_DEFAULT (_RTC_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IFS */
|
||||
#define RTC_IFS_COMP0 (0x1UL << 1) /**< Set Compare match 0 Interrupt Flag */
|
||||
#define _RTC_IFS_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */
|
||||
#define _RTC_IFS_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */
|
||||
#define _RTC_IFS_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */
|
||||
#define RTC_IFS_COMP0_DEFAULT (_RTC_IFS_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IFS */
|
||||
#define RTC_IFS_COMP1 (0x1UL << 2) /**< Set Compare match 1 Interrupt Flag */
|
||||
#define _RTC_IFS_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */
|
||||
#define _RTC_IFS_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */
|
||||
#define _RTC_IFS_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */
|
||||
#define RTC_IFS_COMP1_DEFAULT (_RTC_IFS_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IFS */
|
||||
|
||||
/* Bit fields for RTC IFC */
|
||||
#define _RTC_IFC_RESETVALUE 0x00000000UL /**< Default value for RTC_IFC */
|
||||
#define _RTC_IFC_MASK 0x00000007UL /**< Mask for RTC_IFC */
|
||||
#define RTC_IFC_OF (0x1UL << 0) /**< Clear Overflow Interrupt Flag */
|
||||
#define _RTC_IFC_OF_SHIFT 0 /**< Shift value for RTC_OF */
|
||||
#define _RTC_IFC_OF_MASK 0x1UL /**< Bit mask for RTC_OF */
|
||||
#define _RTC_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */
|
||||
#define RTC_IFC_OF_DEFAULT (_RTC_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IFC */
|
||||
#define RTC_IFC_COMP0 (0x1UL << 1) /**< Clear Compare match 0 Interrupt Flag */
|
||||
#define _RTC_IFC_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */
|
||||
#define _RTC_IFC_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */
|
||||
#define _RTC_IFC_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */
|
||||
#define RTC_IFC_COMP0_DEFAULT (_RTC_IFC_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IFC */
|
||||
#define RTC_IFC_COMP1 (0x1UL << 2) /**< Clear Compare match 1 Interrupt Flag */
|
||||
#define _RTC_IFC_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */
|
||||
#define _RTC_IFC_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */
|
||||
#define _RTC_IFC_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */
|
||||
#define RTC_IFC_COMP1_DEFAULT (_RTC_IFC_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IFC */
|
||||
|
||||
/* Bit fields for RTC IEN */
|
||||
#define _RTC_IEN_RESETVALUE 0x00000000UL /**< Default value for RTC_IEN */
|
||||
#define _RTC_IEN_MASK 0x00000007UL /**< Mask for RTC_IEN */
|
||||
#define RTC_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Enable */
|
||||
#define _RTC_IEN_OF_SHIFT 0 /**< Shift value for RTC_OF */
|
||||
#define _RTC_IEN_OF_MASK 0x1UL /**< Bit mask for RTC_OF */
|
||||
#define _RTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */
|
||||
#define RTC_IEN_OF_DEFAULT (_RTC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IEN */
|
||||
#define RTC_IEN_COMP0 (0x1UL << 1) /**< Compare Match 0 Interrupt Enable */
|
||||
#define _RTC_IEN_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */
|
||||
#define _RTC_IEN_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */
|
||||
#define _RTC_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */
|
||||
#define RTC_IEN_COMP0_DEFAULT (_RTC_IEN_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IEN */
|
||||
#define RTC_IEN_COMP1 (0x1UL << 2) /**< Compare Match 1 Interrupt Enable */
|
||||
#define _RTC_IEN_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */
|
||||
#define _RTC_IEN_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */
|
||||
#define _RTC_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */
|
||||
#define RTC_IEN_COMP1_DEFAULT (_RTC_IEN_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IEN */
|
||||
|
||||
/* Bit fields for RTC FREEZE */
|
||||
#define _RTC_FREEZE_RESETVALUE 0x00000000UL /**< Default value for RTC_FREEZE */
|
||||
#define _RTC_FREEZE_MASK 0x00000001UL /**< Mask for RTC_FREEZE */
|
||||
#define RTC_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
|
||||
#define _RTC_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for RTC_REGFREEZE */
|
||||
#define _RTC_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for RTC_REGFREEZE */
|
||||
#define _RTC_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_FREEZE */
|
||||
#define _RTC_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for RTC_FREEZE */
|
||||
#define _RTC_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for RTC_FREEZE */
|
||||
#define RTC_FREEZE_REGFREEZE_DEFAULT (_RTC_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_FREEZE */
|
||||
#define RTC_FREEZE_REGFREEZE_UPDATE (_RTC_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for RTC_FREEZE */
|
||||
#define RTC_FREEZE_REGFREEZE_FREEZE (_RTC_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for RTC_FREEZE */
|
||||
|
||||
/* Bit fields for RTC SYNCBUSY */
|
||||
#define _RTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for RTC_SYNCBUSY */
|
||||
#define _RTC_SYNCBUSY_MASK 0x00000007UL /**< Mask for RTC_SYNCBUSY */
|
||||
#define RTC_SYNCBUSY_CTRL (0x1UL << 0) /**< RTC_CTRL Register Busy */
|
||||
#define _RTC_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for RTC_CTRL */
|
||||
#define _RTC_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for RTC_CTRL */
|
||||
#define _RTC_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */
|
||||
#define RTC_SYNCBUSY_CTRL_DEFAULT (_RTC_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */
|
||||
#define RTC_SYNCBUSY_COMP0 (0x1UL << 1) /**< RTC_COMP0 Register Busy */
|
||||
#define _RTC_SYNCBUSY_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */
|
||||
#define _RTC_SYNCBUSY_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */
|
||||
#define _RTC_SYNCBUSY_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */
|
||||
#define RTC_SYNCBUSY_COMP0_DEFAULT (_RTC_SYNCBUSY_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */
|
||||
#define RTC_SYNCBUSY_COMP1 (0x1UL << 2) /**< RTC_COMP1 Register Busy */
|
||||
#define _RTC_SYNCBUSY_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */
|
||||
#define _RTC_SYNCBUSY_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */
|
||||
#define _RTC_SYNCBUSY_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */
|
||||
#define RTC_SYNCBUSY_COMP1_DEFAULT (_RTC_SYNCBUSY_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */
|
||||
|
||||
/** @} End of group EFM32G_RTC */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,931 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief efm32g_timer Register and Bit Field definitions
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_TIMER
|
||||
* @{
|
||||
* @brief EFM32G_TIMER Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__IO uint32_t CMD; /**< Command Register */
|
||||
__I uint32_t STATUS; /**< Status Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IO uint32_t TOP; /**< Counter Top Value Register */
|
||||
__IO uint32_t TOPB; /**< Counter Top Value Buffer Register */
|
||||
__IO uint32_t CNT; /**< Counter Value Register */
|
||||
__IO uint32_t ROUTE; /**< I/O Routing Register */
|
||||
|
||||
uint32_t RESERVED0[1]; /**< Reserved registers */
|
||||
|
||||
TIMER_CC_TypeDef CC[3]; /**< Compare/Capture Channel */
|
||||
|
||||
uint32_t RESERVED1[4]; /**< Reserved for future use **/
|
||||
__IO uint32_t DTCTRL; /**< DTI Control Register */
|
||||
__IO uint32_t DTTIME; /**< DTI Time Control Register */
|
||||
__IO uint32_t DTFC; /**< DTI Fault Configuration Register */
|
||||
__IO uint32_t DTOGEN; /**< DTI Output Generation Enable Register */
|
||||
__I uint32_t DTFAULT; /**< DTI Fault Register */
|
||||
__O uint32_t DTFAULTC; /**< DTI Fault Clear Register */
|
||||
__IO uint32_t DTLOCK; /**< DTI Configuration Lock Register */
|
||||
} TIMER_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_TIMER_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/* Bit fields for TIMER CTRL */
|
||||
#define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_MASK 0x0F030FFBUL /**< Mask for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */
|
||||
#define _TIMER_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */
|
||||
#define _TIMER_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_MODE_UP 0x00000000UL /**< Mode UP for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_MODE_DOWN 0x00000001UL /**< Mode DOWN for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_MODE_QDEC 0x00000003UL /**< Mode QDEC for TIMER_CTRL */
|
||||
#define TIMER_CTRL_MODE_DEFAULT (_TIMER_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CTRL */
|
||||
#define TIMER_CTRL_MODE_UP (_TIMER_CTRL_MODE_UP << 0) /**< Shifted mode UP for TIMER_CTRL */
|
||||
#define TIMER_CTRL_MODE_DOWN (_TIMER_CTRL_MODE_DOWN << 0) /**< Shifted mode DOWN for TIMER_CTRL */
|
||||
#define TIMER_CTRL_MODE_UPDOWN (_TIMER_CTRL_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for TIMER_CTRL */
|
||||
#define TIMER_CTRL_MODE_QDEC (_TIMER_CTRL_MODE_QDEC << 0) /**< Shifted mode QDEC for TIMER_CTRL */
|
||||
#define TIMER_CTRL_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */
|
||||
#define _TIMER_CTRL_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */
|
||||
#define _TIMER_CTRL_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */
|
||||
#define _TIMER_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
|
||||
#define TIMER_CTRL_SYNC_DEFAULT (_TIMER_CTRL_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_CTRL */
|
||||
#define TIMER_CTRL_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */
|
||||
#define _TIMER_CTRL_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */
|
||||
#define _TIMER_CTRL_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */
|
||||
#define _TIMER_CTRL_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
|
||||
#define TIMER_CTRL_OSMEN_DEFAULT (_TIMER_CTRL_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CTRL */
|
||||
#define TIMER_CTRL_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */
|
||||
#define _TIMER_CTRL_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */
|
||||
#define _TIMER_CTRL_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */
|
||||
#define _TIMER_CTRL_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_QDM_X2 0x00000000UL /**< Mode X2 for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_QDM_X4 0x00000001UL /**< Mode X4 for TIMER_CTRL */
|
||||
#define TIMER_CTRL_QDM_DEFAULT (_TIMER_CTRL_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_CTRL */
|
||||
#define TIMER_CTRL_QDM_X2 (_TIMER_CTRL_QDM_X2 << 5) /**< Shifted mode X2 for TIMER_CTRL */
|
||||
#define TIMER_CTRL_QDM_X4 (_TIMER_CTRL_QDM_X4 << 5) /**< Shifted mode X4 for TIMER_CTRL */
|
||||
#define TIMER_CTRL_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */
|
||||
#define _TIMER_CTRL_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */
|
||||
#define _TIMER_CTRL_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */
|
||||
#define _TIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
|
||||
#define TIMER_CTRL_DEBUGRUN_DEFAULT (_TIMER_CTRL_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_CTRL */
|
||||
#define TIMER_CTRL_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */
|
||||
#define _TIMER_CTRL_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */
|
||||
#define _TIMER_CTRL_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */
|
||||
#define _TIMER_CTRL_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
|
||||
#define TIMER_CTRL_DMACLRACT_DEFAULT (_TIMER_CTRL_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_RISEA_SHIFT 8 /**< Shift value for TIMER_RISEA */
|
||||
#define _TIMER_CTRL_RISEA_MASK 0x300UL /**< Bit mask for TIMER_RISEA */
|
||||
#define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */
|
||||
#define TIMER_CTRL_RISEA_DEFAULT (_TIMER_CTRL_RISEA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CTRL */
|
||||
#define TIMER_CTRL_RISEA_NONE (_TIMER_CTRL_RISEA_NONE << 8) /**< Shifted mode NONE for TIMER_CTRL */
|
||||
#define TIMER_CTRL_RISEA_START (_TIMER_CTRL_RISEA_START << 8) /**< Shifted mode START for TIMER_CTRL */
|
||||
#define TIMER_CTRL_RISEA_STOP (_TIMER_CTRL_RISEA_STOP << 8) /**< Shifted mode STOP for TIMER_CTRL */
|
||||
#define TIMER_CTRL_RISEA_RELOADSTART (_TIMER_CTRL_RISEA_RELOADSTART << 8) /**< Shifted mode RELOADSTART for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_FALLA_SHIFT 10 /**< Shift value for TIMER_FALLA */
|
||||
#define _TIMER_CTRL_FALLA_MASK 0xC00UL /**< Bit mask for TIMER_FALLA */
|
||||
#define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */
|
||||
#define TIMER_CTRL_FALLA_DEFAULT (_TIMER_CTRL_FALLA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CTRL */
|
||||
#define TIMER_CTRL_FALLA_NONE (_TIMER_CTRL_FALLA_NONE << 10) /**< Shifted mode NONE for TIMER_CTRL */
|
||||
#define TIMER_CTRL_FALLA_START (_TIMER_CTRL_FALLA_START << 10) /**< Shifted mode START for TIMER_CTRL */
|
||||
#define TIMER_CTRL_FALLA_STOP (_TIMER_CTRL_FALLA_STOP << 10) /**< Shifted mode STOP for TIMER_CTRL */
|
||||
#define TIMER_CTRL_FALLA_RELOADSTART (_TIMER_CTRL_FALLA_RELOADSTART << 10) /**< Shifted mode RELOADSTART for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_CLKSEL_SHIFT 16 /**< Shift value for TIMER_CLKSEL */
|
||||
#define _TIMER_CTRL_CLKSEL_MASK 0x30000UL /**< Bit mask for TIMER_CLKSEL */
|
||||
#define _TIMER_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_CLKSEL_PRESCHFPERCLK 0x00000000UL /**< Mode PRESCHFPERCLK for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for TIMER_CTRL */
|
||||
#define TIMER_CTRL_CLKSEL_DEFAULT (_TIMER_CTRL_CLKSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CTRL */
|
||||
#define TIMER_CTRL_CLKSEL_PRESCHFPERCLK (_TIMER_CTRL_CLKSEL_PRESCHFPERCLK << 16) /**< Shifted mode PRESCHFPERCLK for TIMER_CTRL */
|
||||
#define TIMER_CTRL_CLKSEL_CC1 (_TIMER_CTRL_CLKSEL_CC1 << 16) /**< Shifted mode CC1 for TIMER_CTRL */
|
||||
#define TIMER_CTRL_CLKSEL_TIMEROUF (_TIMER_CTRL_CLKSEL_TIMEROUF << 16) /**< Shifted mode TIMEROUF for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_PRESC_SHIFT 24 /**< Shift value for TIMER_PRESC */
|
||||
#define _TIMER_CTRL_PRESC_MASK 0xF000000UL /**< Bit mask for TIMER_PRESC */
|
||||
#define _TIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_PRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_PRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_CTRL */
|
||||
#define _TIMER_CTRL_PRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_CTRL */
|
||||
#define TIMER_CTRL_PRESC_DEFAULT (_TIMER_CTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CTRL */
|
||||
#define TIMER_CTRL_PRESC_DIV1 (_TIMER_CTRL_PRESC_DIV1 << 24) /**< Shifted mode DIV1 for TIMER_CTRL */
|
||||
#define TIMER_CTRL_PRESC_DIV2 (_TIMER_CTRL_PRESC_DIV2 << 24) /**< Shifted mode DIV2 for TIMER_CTRL */
|
||||
#define TIMER_CTRL_PRESC_DIV4 (_TIMER_CTRL_PRESC_DIV4 << 24) /**< Shifted mode DIV4 for TIMER_CTRL */
|
||||
#define TIMER_CTRL_PRESC_DIV8 (_TIMER_CTRL_PRESC_DIV8 << 24) /**< Shifted mode DIV8 for TIMER_CTRL */
|
||||
#define TIMER_CTRL_PRESC_DIV16 (_TIMER_CTRL_PRESC_DIV16 << 24) /**< Shifted mode DIV16 for TIMER_CTRL */
|
||||
#define TIMER_CTRL_PRESC_DIV32 (_TIMER_CTRL_PRESC_DIV32 << 24) /**< Shifted mode DIV32 for TIMER_CTRL */
|
||||
#define TIMER_CTRL_PRESC_DIV64 (_TIMER_CTRL_PRESC_DIV64 << 24) /**< Shifted mode DIV64 for TIMER_CTRL */
|
||||
#define TIMER_CTRL_PRESC_DIV128 (_TIMER_CTRL_PRESC_DIV128 << 24) /**< Shifted mode DIV128 for TIMER_CTRL */
|
||||
#define TIMER_CTRL_PRESC_DIV256 (_TIMER_CTRL_PRESC_DIV256 << 24) /**< Shifted mode DIV256 for TIMER_CTRL */
|
||||
#define TIMER_CTRL_PRESC_DIV512 (_TIMER_CTRL_PRESC_DIV512 << 24) /**< Shifted mode DIV512 for TIMER_CTRL */
|
||||
#define TIMER_CTRL_PRESC_DIV1024 (_TIMER_CTRL_PRESC_DIV1024 << 24) /**< Shifted mode DIV1024 for TIMER_CTRL */
|
||||
|
||||
/* Bit fields for TIMER CMD */
|
||||
#define _TIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for TIMER_CMD */
|
||||
#define _TIMER_CMD_MASK 0x00000003UL /**< Mask for TIMER_CMD */
|
||||
#define TIMER_CMD_START (0x1UL << 0) /**< Start Timer */
|
||||
#define _TIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */
|
||||
#define _TIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */
|
||||
#define _TIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */
|
||||
#define TIMER_CMD_START_DEFAULT (_TIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CMD */
|
||||
#define TIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */
|
||||
#define _TIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */
|
||||
#define _TIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */
|
||||
#define _TIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */
|
||||
#define TIMER_CMD_STOP_DEFAULT (_TIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_CMD */
|
||||
|
||||
/* Bit fields for TIMER STATUS */
|
||||
#define _TIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for TIMER_STATUS */
|
||||
#define _TIMER_STATUS_MASK 0x07070707UL /**< Mask for TIMER_STATUS */
|
||||
#define TIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */
|
||||
#define _TIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */
|
||||
#define _TIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */
|
||||
#define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
|
||||
#define TIMER_STATUS_RUNNING_DEFAULT (_TIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_STATUS */
|
||||
#define TIMER_STATUS_DIR (0x1UL << 1) /**< Direction */
|
||||
#define _TIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */
|
||||
#define _TIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */
|
||||
#define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
|
||||
#define _TIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for TIMER_STATUS */
|
||||
#define _TIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for TIMER_STATUS */
|
||||
#define TIMER_STATUS_DIR_DEFAULT (_TIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_STATUS */
|
||||
#define TIMER_STATUS_DIR_UP (_TIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for TIMER_STATUS */
|
||||
#define TIMER_STATUS_DIR_DOWN (_TIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for TIMER_STATUS */
|
||||
#define TIMER_STATUS_TOPBV (0x1UL << 2) /**< TOPB Valid */
|
||||
#define _TIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */
|
||||
#define _TIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */
|
||||
#define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
|
||||
#define TIMER_STATUS_TOPBV_DEFAULT (_TIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_STATUS */
|
||||
#define TIMER_STATUS_CCVBV0 (0x1UL << 8) /**< CC0 CCVB Valid */
|
||||
#define _TIMER_STATUS_CCVBV0_SHIFT 8 /**< Shift value for TIMER_CCVBV0 */
|
||||
#define _TIMER_STATUS_CCVBV0_MASK 0x100UL /**< Bit mask for TIMER_CCVBV0 */
|
||||
#define _TIMER_STATUS_CCVBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
|
||||
#define TIMER_STATUS_CCVBV0_DEFAULT (_TIMER_STATUS_CCVBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_STATUS */
|
||||
#define TIMER_STATUS_CCVBV1 (0x1UL << 9) /**< CC1 CCVB Valid */
|
||||
#define _TIMER_STATUS_CCVBV1_SHIFT 9 /**< Shift value for TIMER_CCVBV1 */
|
||||
#define _TIMER_STATUS_CCVBV1_MASK 0x200UL /**< Bit mask for TIMER_CCVBV1 */
|
||||
#define _TIMER_STATUS_CCVBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
|
||||
#define TIMER_STATUS_CCVBV1_DEFAULT (_TIMER_STATUS_CCVBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_STATUS */
|
||||
#define TIMER_STATUS_CCVBV2 (0x1UL << 10) /**< CC2 CCVB Valid */
|
||||
#define _TIMER_STATUS_CCVBV2_SHIFT 10 /**< Shift value for TIMER_CCVBV2 */
|
||||
#define _TIMER_STATUS_CCVBV2_MASK 0x400UL /**< Bit mask for TIMER_CCVBV2 */
|
||||
#define _TIMER_STATUS_CCVBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
|
||||
#define TIMER_STATUS_CCVBV2_DEFAULT (_TIMER_STATUS_CCVBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_STATUS */
|
||||
#define TIMER_STATUS_ICV0 (0x1UL << 16) /**< CC0 Input Capture Valid */
|
||||
#define _TIMER_STATUS_ICV0_SHIFT 16 /**< Shift value for TIMER_ICV0 */
|
||||
#define _TIMER_STATUS_ICV0_MASK 0x10000UL /**< Bit mask for TIMER_ICV0 */
|
||||
#define _TIMER_STATUS_ICV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
|
||||
#define TIMER_STATUS_ICV0_DEFAULT (_TIMER_STATUS_ICV0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_STATUS */
|
||||
#define TIMER_STATUS_ICV1 (0x1UL << 17) /**< CC1 Input Capture Valid */
|
||||
#define _TIMER_STATUS_ICV1_SHIFT 17 /**< Shift value for TIMER_ICV1 */
|
||||
#define _TIMER_STATUS_ICV1_MASK 0x20000UL /**< Bit mask for TIMER_ICV1 */
|
||||
#define _TIMER_STATUS_ICV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
|
||||
#define TIMER_STATUS_ICV1_DEFAULT (_TIMER_STATUS_ICV1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_STATUS */
|
||||
#define TIMER_STATUS_ICV2 (0x1UL << 18) /**< CC2 Input Capture Valid */
|
||||
#define _TIMER_STATUS_ICV2_SHIFT 18 /**< Shift value for TIMER_ICV2 */
|
||||
#define _TIMER_STATUS_ICV2_MASK 0x40000UL /**< Bit mask for TIMER_ICV2 */
|
||||
#define _TIMER_STATUS_ICV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
|
||||
#define TIMER_STATUS_ICV2_DEFAULT (_TIMER_STATUS_ICV2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_STATUS */
|
||||
#define TIMER_STATUS_CCPOL0 (0x1UL << 24) /**< CC0 Polarity */
|
||||
#define _TIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */
|
||||
#define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */
|
||||
#define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
|
||||
#define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */
|
||||
#define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */
|
||||
#define TIMER_STATUS_CCPOL0_DEFAULT (_TIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_STATUS */
|
||||
#define TIMER_STATUS_CCPOL0_LOWRISE (_TIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for TIMER_STATUS */
|
||||
#define TIMER_STATUS_CCPOL0_HIGHFALL (_TIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */
|
||||
#define TIMER_STATUS_CCPOL1 (0x1UL << 25) /**< CC1 Polarity */
|
||||
#define _TIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */
|
||||
#define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */
|
||||
#define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
|
||||
#define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */
|
||||
#define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */
|
||||
#define TIMER_STATUS_CCPOL1_DEFAULT (_TIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_STATUS */
|
||||
#define TIMER_STATUS_CCPOL1_LOWRISE (_TIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for TIMER_STATUS */
|
||||
#define TIMER_STATUS_CCPOL1_HIGHFALL (_TIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */
|
||||
#define TIMER_STATUS_CCPOL2 (0x1UL << 26) /**< CC2 Polarity */
|
||||
#define _TIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */
|
||||
#define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */
|
||||
#define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */
|
||||
#define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */
|
||||
#define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */
|
||||
#define TIMER_STATUS_CCPOL2_DEFAULT (_TIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_STATUS */
|
||||
#define TIMER_STATUS_CCPOL2_LOWRISE (_TIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for TIMER_STATUS */
|
||||
#define TIMER_STATUS_CCPOL2_HIGHFALL (_TIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */
|
||||
|
||||
/* Bit fields for TIMER IEN */
|
||||
#define _TIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_IEN */
|
||||
#define _TIMER_IEN_MASK 0x00000773UL /**< Mask for TIMER_IEN */
|
||||
#define TIMER_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Enable */
|
||||
#define _TIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */
|
||||
#define _TIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
|
||||
#define _TIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
|
||||
#define TIMER_IEN_OF_DEFAULT (_TIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IEN */
|
||||
#define TIMER_IEN_UF (0x1UL << 1) /**< Underflow Interrupt Enable */
|
||||
#define _TIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */
|
||||
#define _TIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
|
||||
#define _TIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
|
||||
#define TIMER_IEN_UF_DEFAULT (_TIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IEN */
|
||||
#define TIMER_IEN_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Enable */
|
||||
#define _TIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
|
||||
#define _TIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
|
||||
#define _TIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
|
||||
#define TIMER_IEN_CC0_DEFAULT (_TIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IEN */
|
||||
#define TIMER_IEN_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Enable */
|
||||
#define _TIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
|
||||
#define _TIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
|
||||
#define _TIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
|
||||
#define TIMER_IEN_CC1_DEFAULT (_TIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IEN */
|
||||
#define TIMER_IEN_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Enable */
|
||||
#define _TIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
|
||||
#define _TIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
|
||||
#define _TIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
|
||||
#define TIMER_IEN_CC2_DEFAULT (_TIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IEN */
|
||||
#define TIMER_IEN_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Enable */
|
||||
#define _TIMER_IEN_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
|
||||
#define _TIMER_IEN_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
|
||||
#define _TIMER_IEN_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
|
||||
#define TIMER_IEN_ICBOF0_DEFAULT (_TIMER_IEN_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IEN */
|
||||
#define TIMER_IEN_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Enable */
|
||||
#define _TIMER_IEN_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
|
||||
#define _TIMER_IEN_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
|
||||
#define _TIMER_IEN_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
|
||||
#define TIMER_IEN_ICBOF1_DEFAULT (_TIMER_IEN_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IEN */
|
||||
#define TIMER_IEN_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Enable */
|
||||
#define _TIMER_IEN_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
|
||||
#define _TIMER_IEN_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
|
||||
#define _TIMER_IEN_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */
|
||||
#define TIMER_IEN_ICBOF2_DEFAULT (_TIMER_IEN_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IEN */
|
||||
|
||||
/* Bit fields for TIMER IF */
|
||||
#define _TIMER_IF_RESETVALUE 0x00000000UL /**< Default value for TIMER_IF */
|
||||
#define _TIMER_IF_MASK 0x00000773UL /**< Mask for TIMER_IF */
|
||||
#define TIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */
|
||||
#define _TIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */
|
||||
#define _TIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
|
||||
#define _TIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
|
||||
#define TIMER_IF_OF_DEFAULT (_TIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IF */
|
||||
#define TIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */
|
||||
#define _TIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */
|
||||
#define _TIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
|
||||
#define _TIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
|
||||
#define TIMER_IF_UF_DEFAULT (_TIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IF */
|
||||
#define TIMER_IF_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag */
|
||||
#define _TIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
|
||||
#define _TIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
|
||||
#define _TIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
|
||||
#define TIMER_IF_CC0_DEFAULT (_TIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IF */
|
||||
#define TIMER_IF_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag */
|
||||
#define _TIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
|
||||
#define _TIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
|
||||
#define _TIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
|
||||
#define TIMER_IF_CC1_DEFAULT (_TIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IF */
|
||||
#define TIMER_IF_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag */
|
||||
#define _TIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
|
||||
#define _TIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
|
||||
#define _TIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
|
||||
#define TIMER_IF_CC2_DEFAULT (_TIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IF */
|
||||
#define TIMER_IF_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag */
|
||||
#define _TIMER_IF_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
|
||||
#define _TIMER_IF_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
|
||||
#define _TIMER_IF_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
|
||||
#define TIMER_IF_ICBOF0_DEFAULT (_TIMER_IF_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IF */
|
||||
#define TIMER_IF_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag */
|
||||
#define _TIMER_IF_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
|
||||
#define _TIMER_IF_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
|
||||
#define _TIMER_IF_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
|
||||
#define TIMER_IF_ICBOF1_DEFAULT (_TIMER_IF_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IF */
|
||||
#define TIMER_IF_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag */
|
||||
#define _TIMER_IF_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
|
||||
#define _TIMER_IF_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
|
||||
#define _TIMER_IF_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */
|
||||
#define TIMER_IF_ICBOF2_DEFAULT (_TIMER_IF_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IF */
|
||||
|
||||
/* Bit fields for TIMER IFS */
|
||||
#define _TIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFS */
|
||||
#define _TIMER_IFS_MASK 0x00000773UL /**< Mask for TIMER_IFS */
|
||||
#define TIMER_IFS_OF (0x1UL << 0) /**< Overflow Interrupt Flag Set */
|
||||
#define _TIMER_IFS_OF_SHIFT 0 /**< Shift value for TIMER_OF */
|
||||
#define _TIMER_IFS_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
|
||||
#define _TIMER_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
|
||||
#define TIMER_IFS_OF_DEFAULT (_TIMER_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IFS */
|
||||
#define TIMER_IFS_UF (0x1UL << 1) /**< Underflow Interrupt Flag Set */
|
||||
#define _TIMER_IFS_UF_SHIFT 1 /**< Shift value for TIMER_UF */
|
||||
#define _TIMER_IFS_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
|
||||
#define _TIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
|
||||
#define TIMER_IFS_UF_DEFAULT (_TIMER_IFS_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IFS */
|
||||
#define TIMER_IFS_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag Set */
|
||||
#define _TIMER_IFS_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
|
||||
#define _TIMER_IFS_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
|
||||
#define _TIMER_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
|
||||
#define TIMER_IFS_CC0_DEFAULT (_TIMER_IFS_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IFS */
|
||||
#define TIMER_IFS_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag Set */
|
||||
#define _TIMER_IFS_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
|
||||
#define _TIMER_IFS_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
|
||||
#define _TIMER_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
|
||||
#define TIMER_IFS_CC1_DEFAULT (_TIMER_IFS_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IFS */
|
||||
#define TIMER_IFS_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag Set */
|
||||
#define _TIMER_IFS_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
|
||||
#define _TIMER_IFS_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
|
||||
#define _TIMER_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
|
||||
#define TIMER_IFS_CC2_DEFAULT (_TIMER_IFS_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IFS */
|
||||
#define TIMER_IFS_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag Set */
|
||||
#define _TIMER_IFS_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
|
||||
#define _TIMER_IFS_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
|
||||
#define _TIMER_IFS_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
|
||||
#define TIMER_IFS_ICBOF0_DEFAULT (_TIMER_IFS_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IFS */
|
||||
#define TIMER_IFS_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Set */
|
||||
#define _TIMER_IFS_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
|
||||
#define _TIMER_IFS_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
|
||||
#define _TIMER_IFS_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
|
||||
#define TIMER_IFS_ICBOF1_DEFAULT (_TIMER_IFS_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IFS */
|
||||
#define TIMER_IFS_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag Set */
|
||||
#define _TIMER_IFS_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
|
||||
#define _TIMER_IFS_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
|
||||
#define _TIMER_IFS_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFS */
|
||||
#define TIMER_IFS_ICBOF2_DEFAULT (_TIMER_IFS_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IFS */
|
||||
|
||||
/* Bit fields for TIMER IFC */
|
||||
#define _TIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_IFC */
|
||||
#define _TIMER_IFC_MASK 0x00000773UL /**< Mask for TIMER_IFC */
|
||||
#define TIMER_IFC_OF (0x1UL << 0) /**< Overflow Interrupt Flag Clear */
|
||||
#define _TIMER_IFC_OF_SHIFT 0 /**< Shift value for TIMER_OF */
|
||||
#define _TIMER_IFC_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */
|
||||
#define _TIMER_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
|
||||
#define TIMER_IFC_OF_DEFAULT (_TIMER_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IFC */
|
||||
#define TIMER_IFC_UF (0x1UL << 1) /**< Underflow Interrupt Flag Clear */
|
||||
#define _TIMER_IFC_UF_SHIFT 1 /**< Shift value for TIMER_UF */
|
||||
#define _TIMER_IFC_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */
|
||||
#define _TIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
|
||||
#define TIMER_IFC_UF_DEFAULT (_TIMER_IFC_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IFC */
|
||||
#define TIMER_IFC_CC0 (0x1UL << 4) /**< CC Channel 0 Interrupt Flag Clear */
|
||||
#define _TIMER_IFC_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */
|
||||
#define _TIMER_IFC_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */
|
||||
#define _TIMER_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
|
||||
#define TIMER_IFC_CC0_DEFAULT (_TIMER_IFC_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IFC */
|
||||
#define TIMER_IFC_CC1 (0x1UL << 5) /**< CC Channel 1 Interrupt Flag Clear */
|
||||
#define _TIMER_IFC_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */
|
||||
#define _TIMER_IFC_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */
|
||||
#define _TIMER_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
|
||||
#define TIMER_IFC_CC1_DEFAULT (_TIMER_IFC_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IFC */
|
||||
#define TIMER_IFC_CC2 (0x1UL << 6) /**< CC Channel 2 Interrupt Flag Clear */
|
||||
#define _TIMER_IFC_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */
|
||||
#define _TIMER_IFC_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */
|
||||
#define _TIMER_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
|
||||
#define TIMER_IFC_CC2_DEFAULT (_TIMER_IFC_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IFC */
|
||||
#define TIMER_IFC_ICBOF0 (0x1UL << 8) /**< CC Channel 0 Input Capture Buffer Overflow Interrupt Flag Clear */
|
||||
#define _TIMER_IFC_ICBOF0_SHIFT 8 /**< Shift value for TIMER_ICBOF0 */
|
||||
#define _TIMER_IFC_ICBOF0_MASK 0x100UL /**< Bit mask for TIMER_ICBOF0 */
|
||||
#define _TIMER_IFC_ICBOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
|
||||
#define TIMER_IFC_ICBOF0_DEFAULT (_TIMER_IFC_ICBOF0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_IFC */
|
||||
#define TIMER_IFC_ICBOF1 (0x1UL << 9) /**< CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Clear */
|
||||
#define _TIMER_IFC_ICBOF1_SHIFT 9 /**< Shift value for TIMER_ICBOF1 */
|
||||
#define _TIMER_IFC_ICBOF1_MASK 0x200UL /**< Bit mask for TIMER_ICBOF1 */
|
||||
#define _TIMER_IFC_ICBOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
|
||||
#define TIMER_IFC_ICBOF1_DEFAULT (_TIMER_IFC_ICBOF1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_IFC */
|
||||
#define TIMER_IFC_ICBOF2 (0x1UL << 10) /**< CC Channel 2 Input Capture Buffer Overflow Interrupt Flag Clear */
|
||||
#define _TIMER_IFC_ICBOF2_SHIFT 10 /**< Shift value for TIMER_ICBOF2 */
|
||||
#define _TIMER_IFC_ICBOF2_MASK 0x400UL /**< Bit mask for TIMER_ICBOF2 */
|
||||
#define _TIMER_IFC_ICBOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IFC */
|
||||
#define TIMER_IFC_ICBOF2_DEFAULT (_TIMER_IFC_ICBOF2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_IFC */
|
||||
|
||||
/* Bit fields for TIMER TOP */
|
||||
#define _TIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for TIMER_TOP */
|
||||
#define _TIMER_TOP_MASK 0x0000FFFFUL /**< Mask for TIMER_TOP */
|
||||
#define _TIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */
|
||||
#define _TIMER_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for TIMER_TOP */
|
||||
#define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for TIMER_TOP */
|
||||
#define TIMER_TOP_TOP_DEFAULT (_TIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOP */
|
||||
|
||||
/* Bit fields for TIMER TOPB */
|
||||
#define _TIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for TIMER_TOPB */
|
||||
#define _TIMER_TOPB_MASK 0x0000FFFFUL /**< Mask for TIMER_TOPB */
|
||||
#define _TIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */
|
||||
#define _TIMER_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for TIMER_TOPB */
|
||||
#define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_TOPB */
|
||||
#define TIMER_TOPB_TOPB_DEFAULT (_TIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */
|
||||
|
||||
/* Bit fields for TIMER CNT */
|
||||
#define _TIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for TIMER_CNT */
|
||||
#define _TIMER_CNT_MASK 0x0000FFFFUL /**< Mask for TIMER_CNT */
|
||||
#define _TIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */
|
||||
#define _TIMER_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for TIMER_CNT */
|
||||
#define _TIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CNT */
|
||||
#define TIMER_CNT_CNT_DEFAULT (_TIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CNT */
|
||||
|
||||
/* Bit fields for TIMER ROUTE */
|
||||
#define _TIMER_ROUTE_RESETVALUE 0x00000000UL /**< Default value for TIMER_ROUTE */
|
||||
#define _TIMER_ROUTE_MASK 0x00030707UL /**< Mask for TIMER_ROUTE */
|
||||
#define TIMER_ROUTE_CC0PEN (0x1UL << 0) /**< CC Channel 0 Pin Enable */
|
||||
#define _TIMER_ROUTE_CC0PEN_SHIFT 0 /**< Shift value for TIMER_CC0PEN */
|
||||
#define _TIMER_ROUTE_CC0PEN_MASK 0x1UL /**< Bit mask for TIMER_CC0PEN */
|
||||
#define _TIMER_ROUTE_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */
|
||||
#define TIMER_ROUTE_CC0PEN_DEFAULT (_TIMER_ROUTE_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_ROUTE */
|
||||
#define TIMER_ROUTE_CC1PEN (0x1UL << 1) /**< CC Channel 1 Pin Enable */
|
||||
#define _TIMER_ROUTE_CC1PEN_SHIFT 1 /**< Shift value for TIMER_CC1PEN */
|
||||
#define _TIMER_ROUTE_CC1PEN_MASK 0x2UL /**< Bit mask for TIMER_CC1PEN */
|
||||
#define _TIMER_ROUTE_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */
|
||||
#define TIMER_ROUTE_CC1PEN_DEFAULT (_TIMER_ROUTE_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_ROUTE */
|
||||
#define TIMER_ROUTE_CC2PEN (0x1UL << 2) /**< CC Channel 2 Pin Enable */
|
||||
#define _TIMER_ROUTE_CC2PEN_SHIFT 2 /**< Shift value for TIMER_CC2PEN */
|
||||
#define _TIMER_ROUTE_CC2PEN_MASK 0x4UL /**< Bit mask for TIMER_CC2PEN */
|
||||
#define _TIMER_ROUTE_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */
|
||||
#define TIMER_ROUTE_CC2PEN_DEFAULT (_TIMER_ROUTE_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_ROUTE */
|
||||
#define TIMER_ROUTE_CDTI0PEN (0x1UL << 8) /**< CC Channel 0 Complementary Dead-Time Insertion Pin Enable */
|
||||
#define _TIMER_ROUTE_CDTI0PEN_SHIFT 8 /**< Shift value for TIMER_CDTI0PEN */
|
||||
#define _TIMER_ROUTE_CDTI0PEN_MASK 0x100UL /**< Bit mask for TIMER_CDTI0PEN */
|
||||
#define _TIMER_ROUTE_CDTI0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */
|
||||
#define TIMER_ROUTE_CDTI0PEN_DEFAULT (_TIMER_ROUTE_CDTI0PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_ROUTE */
|
||||
#define TIMER_ROUTE_CDTI1PEN (0x1UL << 9) /**< CC Channel 1 Complementary Dead-Time Insertion Pin Enable */
|
||||
#define _TIMER_ROUTE_CDTI1PEN_SHIFT 9 /**< Shift value for TIMER_CDTI1PEN */
|
||||
#define _TIMER_ROUTE_CDTI1PEN_MASK 0x200UL /**< Bit mask for TIMER_CDTI1PEN */
|
||||
#define _TIMER_ROUTE_CDTI1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */
|
||||
#define TIMER_ROUTE_CDTI1PEN_DEFAULT (_TIMER_ROUTE_CDTI1PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_ROUTE */
|
||||
#define TIMER_ROUTE_CDTI2PEN (0x1UL << 10) /**< CC Channel 2 Complementary Dead-Time Insertion Pin Enable */
|
||||
#define _TIMER_ROUTE_CDTI2PEN_SHIFT 10 /**< Shift value for TIMER_CDTI2PEN */
|
||||
#define _TIMER_ROUTE_CDTI2PEN_MASK 0x400UL /**< Bit mask for TIMER_CDTI2PEN */
|
||||
#define _TIMER_ROUTE_CDTI2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */
|
||||
#define TIMER_ROUTE_CDTI2PEN_DEFAULT (_TIMER_ROUTE_CDTI2PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_ROUTE */
|
||||
#define _TIMER_ROUTE_LOCATION_SHIFT 16 /**< Shift value for TIMER_LOCATION */
|
||||
#define _TIMER_ROUTE_LOCATION_MASK 0x30000UL /**< Bit mask for TIMER_LOCATION */
|
||||
#define _TIMER_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_ROUTE */
|
||||
#define _TIMER_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for TIMER_ROUTE */
|
||||
#define _TIMER_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for TIMER_ROUTE */
|
||||
#define _TIMER_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for TIMER_ROUTE */
|
||||
#define _TIMER_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for TIMER_ROUTE */
|
||||
#define TIMER_ROUTE_LOCATION_DEFAULT (_TIMER_ROUTE_LOCATION_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_ROUTE */
|
||||
#define TIMER_ROUTE_LOCATION_LOC0 (_TIMER_ROUTE_LOCATION_LOC0 << 16) /**< Shifted mode LOC0 for TIMER_ROUTE */
|
||||
#define TIMER_ROUTE_LOCATION_LOC1 (_TIMER_ROUTE_LOCATION_LOC1 << 16) /**< Shifted mode LOC1 for TIMER_ROUTE */
|
||||
#define TIMER_ROUTE_LOCATION_LOC2 (_TIMER_ROUTE_LOCATION_LOC2 << 16) /**< Shifted mode LOC2 for TIMER_ROUTE */
|
||||
#define TIMER_ROUTE_LOCATION_LOC3 (_TIMER_ROUTE_LOCATION_LOC3 << 16) /**< Shifted mode LOC3 for TIMER_ROUTE */
|
||||
|
||||
/* Bit fields for TIMER CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_MASK 0x0F373F17UL /**< Mask for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */
|
||||
#define _TIMER_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */
|
||||
#define _TIMER_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_MODE_PWM 0x00000003UL /**< Mode PWM for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_MODE_DEFAULT (_TIMER_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_MODE_OFF (_TIMER_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_MODE_INPUTCAPTURE (_TIMER_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_MODE_OUTPUTCOMPARE (_TIMER_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_MODE_PWM (_TIMER_CC_CTRL_MODE_PWM << 0) /**< Shifted mode PWM for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */
|
||||
#define _TIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */
|
||||
#define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */
|
||||
#define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_OUTINV_DEFAULT (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_COIST (0x1UL << 4) /**< Compare Output Initial State */
|
||||
#define _TIMER_CC_CTRL_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */
|
||||
#define _TIMER_CC_CTRL_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */
|
||||
#define _TIMER_CC_CTRL_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_COIST_DEFAULT (_TIMER_CC_CTRL_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */
|
||||
#define _TIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */
|
||||
#define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_CMOA_DEFAULT (_TIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_CMOA_NONE (_TIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_CMOA_TOGGLE (_TIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_CMOA_CLEAR (_TIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_CMOA_SET (_TIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */
|
||||
#define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */
|
||||
#define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_COFOA_DEFAULT (_TIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_COFOA_NONE (_TIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_COFOA_TOGGLE (_TIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_COFOA_CLEAR (_TIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_COFOA_SET (_TIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */
|
||||
#define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */
|
||||
#define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_CUFOA_DEFAULT (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_CUFOA_NONE (_TIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_CUFOA_TOGGLE (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_CUFOA_CLEAR (_TIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_CUFOA_SET (_TIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_PRSSEL_SHIFT 16 /**< Shift value for TIMER_PRSSEL */
|
||||
#define _TIMER_CC_CTRL_PRSSEL_MASK 0x70000UL /**< Bit mask for TIMER_PRSSEL */
|
||||
#define _TIMER_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_PRSSEL_DEFAULT (_TIMER_CC_CTRL_PRSSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_PRSSEL_PRSCH0 (_TIMER_CC_CTRL_PRSSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_PRSSEL_PRSCH1 (_TIMER_CC_CTRL_PRSSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_PRSSEL_PRSCH2 (_TIMER_CC_CTRL_PRSSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_PRSSEL_PRSCH3 (_TIMER_CC_CTRL_PRSSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_PRSSEL_PRSCH4 (_TIMER_CC_CTRL_PRSSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_PRSSEL_PRSCH5 (_TIMER_CC_CTRL_PRSSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_PRSSEL_PRSCH6 (_TIMER_CC_CTRL_PRSSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_PRSSEL_PRSCH7 (_TIMER_CC_CTRL_PRSSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_INSEL (0x1UL << 20) /**< Input Selection */
|
||||
#define _TIMER_CC_CTRL_INSEL_SHIFT 20 /**< Shift value for TIMER_INSEL */
|
||||
#define _TIMER_CC_CTRL_INSEL_MASK 0x100000UL /**< Bit mask for TIMER_INSEL */
|
||||
#define _TIMER_CC_CTRL_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_INSEL_PIN 0x00000000UL /**< Mode PIN for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_INSEL_PRS 0x00000001UL /**< Mode PRS for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_INSEL_DEFAULT (_TIMER_CC_CTRL_INSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_INSEL_PIN (_TIMER_CC_CTRL_INSEL_PIN << 20) /**< Shifted mode PIN for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_INSEL_PRS (_TIMER_CC_CTRL_INSEL_PRS << 20) /**< Shifted mode PRS for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_FILT (0x1UL << 21) /**< Digital Filter */
|
||||
#define _TIMER_CC_CTRL_FILT_SHIFT 21 /**< Shift value for TIMER_FILT */
|
||||
#define _TIMER_CC_CTRL_FILT_MASK 0x200000UL /**< Bit mask for TIMER_FILT */
|
||||
#define _TIMER_CC_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_FILT_DEFAULT (_TIMER_CC_CTRL_FILT_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_FILT_DISABLE (_TIMER_CC_CTRL_FILT_DISABLE << 21) /**< Shifted mode DISABLE for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_FILT_ENABLE (_TIMER_CC_CTRL_FILT_ENABLE << 21) /**< Shifted mode ENABLE for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */
|
||||
#define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */
|
||||
#define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_ICEDGE_DEFAULT (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_ICEDGE_RISING (_TIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_ICEDGE_FALLING (_TIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_ICEDGE_BOTH (_TIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_ICEDGE_NONE (_TIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */
|
||||
#define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */
|
||||
#define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for TIMER_CC_CTRL */
|
||||
#define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_ICEVCTRL_RISING (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for TIMER_CC_CTRL */
|
||||
#define TIMER_CC_CTRL_ICEVCTRL_FALLING (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for TIMER_CC_CTRL */
|
||||
|
||||
/* Bit fields for TIMER CC_CCV */
|
||||
#define _TIMER_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCV */
|
||||
#define _TIMER_CC_CCV_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCV */
|
||||
#define _TIMER_CC_CCV_CCV_SHIFT 0 /**< Shift value for TIMER_CCV */
|
||||
#define _TIMER_CC_CCV_CCV_MASK 0xFFFFUL /**< Bit mask for TIMER_CCV */
|
||||
#define _TIMER_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCV */
|
||||
#define TIMER_CC_CCV_CCV_DEFAULT (_TIMER_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCV */
|
||||
|
||||
/* Bit fields for TIMER CC_CCVP */
|
||||
#define _TIMER_CC_CCVP_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVP */
|
||||
#define _TIMER_CC_CCVP_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVP */
|
||||
#define _TIMER_CC_CCVP_CCVP_SHIFT 0 /**< Shift value for TIMER_CCVP */
|
||||
#define _TIMER_CC_CCVP_CCVP_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVP */
|
||||
#define _TIMER_CC_CCVP_CCVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVP */
|
||||
#define TIMER_CC_CCVP_CCVP_DEFAULT (_TIMER_CC_CCVP_CCVP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVP */
|
||||
|
||||
/* Bit fields for TIMER CC_CCVB */
|
||||
#define _TIMER_CC_CCVB_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CCVB */
|
||||
#define _TIMER_CC_CCVB_MASK 0x0000FFFFUL /**< Mask for TIMER_CC_CCVB */
|
||||
#define _TIMER_CC_CCVB_CCVB_SHIFT 0 /**< Shift value for TIMER_CCVB */
|
||||
#define _TIMER_CC_CCVB_CCVB_MASK 0xFFFFUL /**< Bit mask for TIMER_CCVB */
|
||||
#define _TIMER_CC_CCVB_CCVB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CCVB */
|
||||
#define TIMER_CC_CCVB_CCVB_DEFAULT (_TIMER_CC_CCVB_CCVB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CCVB */
|
||||
|
||||
/* Bit fields for TIMER DTCTRL */
|
||||
#define _TIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCTRL */
|
||||
#define _TIMER_DTCTRL_MASK 0x0100007FUL /**< Mask for TIMER_DTCTRL */
|
||||
#define TIMER_DTCTRL_DTEN (0x1UL << 0) /**< DTI Enable */
|
||||
#define _TIMER_DTCTRL_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */
|
||||
#define _TIMER_DTCTRL_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */
|
||||
#define _TIMER_DTCTRL_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
|
||||
#define TIMER_DTCTRL_DTEN_DEFAULT (_TIMER_DTCTRL_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
|
||||
#define TIMER_DTCTRL_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */
|
||||
#define _TIMER_DTCTRL_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */
|
||||
#define _TIMER_DTCTRL_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */
|
||||
#define _TIMER_DTCTRL_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
|
||||
#define _TIMER_DTCTRL_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for TIMER_DTCTRL */
|
||||
#define _TIMER_DTCTRL_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for TIMER_DTCTRL */
|
||||
#define TIMER_DTCTRL_DTDAS_DEFAULT (_TIMER_DTCTRL_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
|
||||
#define TIMER_DTCTRL_DTDAS_NORESTART (_TIMER_DTCTRL_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for TIMER_DTCTRL */
|
||||
#define TIMER_DTCTRL_DTDAS_RESTART (_TIMER_DTCTRL_DTDAS_RESTART << 1) /**< Shifted mode RESTART for TIMER_DTCTRL */
|
||||
#define TIMER_DTCTRL_DTIPOL (0x1UL << 2) /**< DTI Inactive Polarity */
|
||||
#define _TIMER_DTCTRL_DTIPOL_SHIFT 2 /**< Shift value for TIMER_DTIPOL */
|
||||
#define _TIMER_DTCTRL_DTIPOL_MASK 0x4UL /**< Bit mask for TIMER_DTIPOL */
|
||||
#define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
|
||||
#define TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
|
||||
#define TIMER_DTCTRL_DTCINV (0x1UL << 3) /**< DTI Complementary Output Invert. */
|
||||
#define _TIMER_DTCTRL_DTCINV_SHIFT 3 /**< Shift value for TIMER_DTCINV */
|
||||
#define _TIMER_DTCTRL_DTCINV_MASK 0x8UL /**< Bit mask for TIMER_DTCINV */
|
||||
#define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
|
||||
#define TIMER_DTCTRL_DTCINV_DEFAULT (_TIMER_DTCTRL_DTCINV_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
|
||||
#define _TIMER_DTCTRL_DTPRSSEL_SHIFT 4 /**< Shift value for TIMER_DTPRSSEL */
|
||||
#define _TIMER_DTCTRL_DTPRSSEL_MASK 0x70UL /**< Bit mask for TIMER_DTPRSSEL */
|
||||
#define _TIMER_DTCTRL_DTPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
|
||||
#define _TIMER_DTCTRL_DTPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTCTRL */
|
||||
#define _TIMER_DTCTRL_DTPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTCTRL */
|
||||
#define _TIMER_DTCTRL_DTPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTCTRL */
|
||||
#define _TIMER_DTCTRL_DTPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTCTRL */
|
||||
#define _TIMER_DTCTRL_DTPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTCTRL */
|
||||
#define _TIMER_DTCTRL_DTPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTCTRL */
|
||||
#define _TIMER_DTCTRL_DTPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTCTRL */
|
||||
#define _TIMER_DTCTRL_DTPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTCTRL */
|
||||
#define TIMER_DTCTRL_DTPRSSEL_DEFAULT (_TIMER_DTCTRL_DTPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
|
||||
#define TIMER_DTCTRL_DTPRSSEL_PRSCH0 (_TIMER_DTCTRL_DTPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for TIMER_DTCTRL */
|
||||
#define TIMER_DTCTRL_DTPRSSEL_PRSCH1 (_TIMER_DTCTRL_DTPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for TIMER_DTCTRL */
|
||||
#define TIMER_DTCTRL_DTPRSSEL_PRSCH2 (_TIMER_DTCTRL_DTPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for TIMER_DTCTRL */
|
||||
#define TIMER_DTCTRL_DTPRSSEL_PRSCH3 (_TIMER_DTCTRL_DTPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for TIMER_DTCTRL */
|
||||
#define TIMER_DTCTRL_DTPRSSEL_PRSCH4 (_TIMER_DTCTRL_DTPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for TIMER_DTCTRL */
|
||||
#define TIMER_DTCTRL_DTPRSSEL_PRSCH5 (_TIMER_DTCTRL_DTPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for TIMER_DTCTRL */
|
||||
#define TIMER_DTCTRL_DTPRSSEL_PRSCH6 (_TIMER_DTCTRL_DTPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for TIMER_DTCTRL */
|
||||
#define TIMER_DTCTRL_DTPRSSEL_PRSCH7 (_TIMER_DTCTRL_DTPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for TIMER_DTCTRL */
|
||||
#define TIMER_DTCTRL_DTPRSEN (0x1UL << 24) /**< DTI PRS Source Enable */
|
||||
#define _TIMER_DTCTRL_DTPRSEN_SHIFT 24 /**< Shift value for TIMER_DTPRSEN */
|
||||
#define _TIMER_DTCTRL_DTPRSEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRSEN */
|
||||
#define _TIMER_DTCTRL_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */
|
||||
#define TIMER_DTCTRL_DTPRSEN_DEFAULT (_TIMER_DTCTRL_DTPRSEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTCTRL */
|
||||
|
||||
/* Bit fields for TIMER DTTIME */
|
||||
#define _TIMER_DTTIME_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTTIME */
|
||||
#define _TIMER_DTTIME_MASK 0x003F3F0FUL /**< Mask for TIMER_DTTIME */
|
||||
#define _TIMER_DTTIME_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */
|
||||
#define _TIMER_DTTIME_DTPRESC_MASK 0xFUL /**< Bit mask for TIMER_DTPRESC */
|
||||
#define _TIMER_DTTIME_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */
|
||||
#define _TIMER_DTTIME_DTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_DTTIME */
|
||||
#define _TIMER_DTTIME_DTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_DTTIME */
|
||||
#define _TIMER_DTTIME_DTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for TIMER_DTTIME */
|
||||
#define _TIMER_DTTIME_DTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for TIMER_DTTIME */
|
||||
#define _TIMER_DTTIME_DTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for TIMER_DTTIME */
|
||||
#define _TIMER_DTTIME_DTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for TIMER_DTTIME */
|
||||
#define _TIMER_DTTIME_DTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for TIMER_DTTIME */
|
||||
#define _TIMER_DTTIME_DTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for TIMER_DTTIME */
|
||||
#define _TIMER_DTTIME_DTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for TIMER_DTTIME */
|
||||
#define _TIMER_DTTIME_DTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for TIMER_DTTIME */
|
||||
#define _TIMER_DTTIME_DTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for TIMER_DTTIME */
|
||||
#define TIMER_DTTIME_DTPRESC_DEFAULT (_TIMER_DTTIME_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTTIME */
|
||||
#define TIMER_DTTIME_DTPRESC_DIV1 (_TIMER_DTTIME_DTPRESC_DIV1 << 0) /**< Shifted mode DIV1 for TIMER_DTTIME */
|
||||
#define TIMER_DTTIME_DTPRESC_DIV2 (_TIMER_DTTIME_DTPRESC_DIV2 << 0) /**< Shifted mode DIV2 for TIMER_DTTIME */
|
||||
#define TIMER_DTTIME_DTPRESC_DIV4 (_TIMER_DTTIME_DTPRESC_DIV4 << 0) /**< Shifted mode DIV4 for TIMER_DTTIME */
|
||||
#define TIMER_DTTIME_DTPRESC_DIV8 (_TIMER_DTTIME_DTPRESC_DIV8 << 0) /**< Shifted mode DIV8 for TIMER_DTTIME */
|
||||
#define TIMER_DTTIME_DTPRESC_DIV16 (_TIMER_DTTIME_DTPRESC_DIV16 << 0) /**< Shifted mode DIV16 for TIMER_DTTIME */
|
||||
#define TIMER_DTTIME_DTPRESC_DIV32 (_TIMER_DTTIME_DTPRESC_DIV32 << 0) /**< Shifted mode DIV32 for TIMER_DTTIME */
|
||||
#define TIMER_DTTIME_DTPRESC_DIV64 (_TIMER_DTTIME_DTPRESC_DIV64 << 0) /**< Shifted mode DIV64 for TIMER_DTTIME */
|
||||
#define TIMER_DTTIME_DTPRESC_DIV128 (_TIMER_DTTIME_DTPRESC_DIV128 << 0) /**< Shifted mode DIV128 for TIMER_DTTIME */
|
||||
#define TIMER_DTTIME_DTPRESC_DIV256 (_TIMER_DTTIME_DTPRESC_DIV256 << 0) /**< Shifted mode DIV256 for TIMER_DTTIME */
|
||||
#define TIMER_DTTIME_DTPRESC_DIV512 (_TIMER_DTTIME_DTPRESC_DIV512 << 0) /**< Shifted mode DIV512 for TIMER_DTTIME */
|
||||
#define TIMER_DTTIME_DTPRESC_DIV1024 (_TIMER_DTTIME_DTPRESC_DIV1024 << 0) /**< Shifted mode DIV1024 for TIMER_DTTIME */
|
||||
#define _TIMER_DTTIME_DTRISET_SHIFT 8 /**< Shift value for TIMER_DTRISET */
|
||||
#define _TIMER_DTTIME_DTRISET_MASK 0x3F00UL /**< Bit mask for TIMER_DTRISET */
|
||||
#define _TIMER_DTTIME_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */
|
||||
#define TIMER_DTTIME_DTRISET_DEFAULT (_TIMER_DTTIME_DTRISET_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_DTTIME */
|
||||
#define _TIMER_DTTIME_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */
|
||||
#define _TIMER_DTTIME_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */
|
||||
#define _TIMER_DTTIME_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIME */
|
||||
#define TIMER_DTTIME_DTFALLT_DEFAULT (_TIMER_DTTIME_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTTIME */
|
||||
|
||||
/* Bit fields for TIMER DTFC */
|
||||
#define _TIMER_DTFC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFC */
|
||||
#define _TIMER_DTFC_MASK 0x0F030707UL /**< Mask for TIMER_DTFC */
|
||||
#define _TIMER_DTFC_DTPRS0FSEL_SHIFT 0 /**< Shift value for TIMER_DTPRS0FSEL */
|
||||
#define _TIMER_DTFC_DTPRS0FSEL_MASK 0x7UL /**< Bit mask for TIMER_DTPRS0FSEL */
|
||||
#define _TIMER_DTFC_DTPRS0FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
|
||||
#define _TIMER_DTFC_DTPRS0FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */
|
||||
#define _TIMER_DTFC_DTPRS0FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */
|
||||
#define _TIMER_DTFC_DTPRS0FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */
|
||||
#define _TIMER_DTFC_DTPRS0FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */
|
||||
#define _TIMER_DTFC_DTPRS0FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */
|
||||
#define _TIMER_DTFC_DTPRS0FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */
|
||||
#define _TIMER_DTFC_DTPRS0FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */
|
||||
#define _TIMER_DTFC_DTPRS0FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */
|
||||
#define TIMER_DTFC_DTPRS0FSEL_DEFAULT (_TIMER_DTFC_DTPRS0FSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFC */
|
||||
#define TIMER_DTFC_DTPRS0FSEL_PRSCH0 (_TIMER_DTFC_DTPRS0FSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for TIMER_DTFC */
|
||||
#define TIMER_DTFC_DTPRS0FSEL_PRSCH1 (_TIMER_DTFC_DTPRS0FSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for TIMER_DTFC */
|
||||
#define TIMER_DTFC_DTPRS0FSEL_PRSCH2 (_TIMER_DTFC_DTPRS0FSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for TIMER_DTFC */
|
||||
#define TIMER_DTFC_DTPRS0FSEL_PRSCH3 (_TIMER_DTFC_DTPRS0FSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for TIMER_DTFC */
|
||||
#define TIMER_DTFC_DTPRS0FSEL_PRSCH4 (_TIMER_DTFC_DTPRS0FSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for TIMER_DTFC */
|
||||
#define TIMER_DTFC_DTPRS0FSEL_PRSCH5 (_TIMER_DTFC_DTPRS0FSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for TIMER_DTFC */
|
||||
#define TIMER_DTFC_DTPRS0FSEL_PRSCH6 (_TIMER_DTFC_DTPRS0FSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for TIMER_DTFC */
|
||||
#define TIMER_DTFC_DTPRS0FSEL_PRSCH7 (_TIMER_DTFC_DTPRS0FSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for TIMER_DTFC */
|
||||
#define _TIMER_DTFC_DTPRS1FSEL_SHIFT 8 /**< Shift value for TIMER_DTPRS1FSEL */
|
||||
#define _TIMER_DTFC_DTPRS1FSEL_MASK 0x700UL /**< Bit mask for TIMER_DTPRS1FSEL */
|
||||
#define _TIMER_DTFC_DTPRS1FSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
|
||||
#define _TIMER_DTFC_DTPRS1FSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for TIMER_DTFC */
|
||||
#define _TIMER_DTFC_DTPRS1FSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for TIMER_DTFC */
|
||||
#define _TIMER_DTFC_DTPRS1FSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for TIMER_DTFC */
|
||||
#define _TIMER_DTFC_DTPRS1FSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for TIMER_DTFC */
|
||||
#define _TIMER_DTFC_DTPRS1FSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for TIMER_DTFC */
|
||||
#define _TIMER_DTFC_DTPRS1FSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for TIMER_DTFC */
|
||||
#define _TIMER_DTFC_DTPRS1FSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for TIMER_DTFC */
|
||||
#define _TIMER_DTFC_DTPRS1FSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for TIMER_DTFC */
|
||||
#define TIMER_DTFC_DTPRS1FSEL_DEFAULT (_TIMER_DTFC_DTPRS1FSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_DTFC */
|
||||
#define TIMER_DTFC_DTPRS1FSEL_PRSCH0 (_TIMER_DTFC_DTPRS1FSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for TIMER_DTFC */
|
||||
#define TIMER_DTFC_DTPRS1FSEL_PRSCH1 (_TIMER_DTFC_DTPRS1FSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for TIMER_DTFC */
|
||||
#define TIMER_DTFC_DTPRS1FSEL_PRSCH2 (_TIMER_DTFC_DTPRS1FSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for TIMER_DTFC */
|
||||
#define TIMER_DTFC_DTPRS1FSEL_PRSCH3 (_TIMER_DTFC_DTPRS1FSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for TIMER_DTFC */
|
||||
#define TIMER_DTFC_DTPRS1FSEL_PRSCH4 (_TIMER_DTFC_DTPRS1FSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for TIMER_DTFC */
|
||||
#define TIMER_DTFC_DTPRS1FSEL_PRSCH5 (_TIMER_DTFC_DTPRS1FSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for TIMER_DTFC */
|
||||
#define TIMER_DTFC_DTPRS1FSEL_PRSCH6 (_TIMER_DTFC_DTPRS1FSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for TIMER_DTFC */
|
||||
#define TIMER_DTFC_DTPRS1FSEL_PRSCH7 (_TIMER_DTFC_DTPRS1FSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for TIMER_DTFC */
|
||||
#define _TIMER_DTFC_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */
|
||||
#define _TIMER_DTFC_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */
|
||||
#define _TIMER_DTFC_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
|
||||
#define _TIMER_DTFC_DTFA_NONE 0x00000000UL /**< Mode NONE for TIMER_DTFC */
|
||||
#define _TIMER_DTFC_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for TIMER_DTFC */
|
||||
#define _TIMER_DTFC_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_DTFC */
|
||||
#define _TIMER_DTFC_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for TIMER_DTFC */
|
||||
#define TIMER_DTFC_DTFA_DEFAULT (_TIMER_DTFC_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTFC */
|
||||
#define TIMER_DTFC_DTFA_NONE (_TIMER_DTFC_DTFA_NONE << 16) /**< Shifted mode NONE for TIMER_DTFC */
|
||||
#define TIMER_DTFC_DTFA_INACTIVE (_TIMER_DTFC_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for TIMER_DTFC */
|
||||
#define TIMER_DTFC_DTFA_CLEAR (_TIMER_DTFC_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for TIMER_DTFC */
|
||||
#define TIMER_DTFC_DTFA_TRISTATE (_TIMER_DTFC_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for TIMER_DTFC */
|
||||
#define TIMER_DTFC_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */
|
||||
#define _TIMER_DTFC_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */
|
||||
#define _TIMER_DTFC_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */
|
||||
#define _TIMER_DTFC_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
|
||||
#define TIMER_DTFC_DTPRS0FEN_DEFAULT (_TIMER_DTFC_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTFC */
|
||||
#define TIMER_DTFC_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */
|
||||
#define _TIMER_DTFC_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */
|
||||
#define _TIMER_DTFC_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */
|
||||
#define _TIMER_DTFC_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
|
||||
#define TIMER_DTFC_DTPRS1FEN_DEFAULT (_TIMER_DTFC_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_DTFC */
|
||||
#define TIMER_DTFC_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */
|
||||
#define _TIMER_DTFC_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */
|
||||
#define _TIMER_DTFC_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */
|
||||
#define _TIMER_DTFC_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
|
||||
#define TIMER_DTFC_DTDBGFEN_DEFAULT (_TIMER_DTFC_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_DTFC */
|
||||
#define TIMER_DTFC_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */
|
||||
#define _TIMER_DTFC_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */
|
||||
#define _TIMER_DTFC_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */
|
||||
#define _TIMER_DTFC_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFC */
|
||||
#define TIMER_DTFC_DTLOCKUPFEN_DEFAULT (_TIMER_DTFC_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_DTFC */
|
||||
|
||||
/* Bit fields for TIMER DTOGEN */
|
||||
#define _TIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTOGEN */
|
||||
#define _TIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for TIMER_DTOGEN */
|
||||
#define TIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CC0 Output Generation Enable */
|
||||
#define _TIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */
|
||||
#define _TIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */
|
||||
#define _TIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
|
||||
#define TIMER_DTOGEN_DTOGCC0EN_DEFAULT (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
|
||||
#define TIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CC1 Output Generation Enable */
|
||||
#define _TIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */
|
||||
#define _TIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */
|
||||
#define _TIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
|
||||
#define TIMER_DTOGEN_DTOGCC1EN_DEFAULT (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
|
||||
#define TIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CC2 Output Generation Enable */
|
||||
#define _TIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */
|
||||
#define _TIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */
|
||||
#define _TIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
|
||||
#define TIMER_DTOGEN_DTOGCC2EN_DEFAULT (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
|
||||
#define TIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTI0 Output Generation Enable */
|
||||
#define _TIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */
|
||||
#define _TIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */
|
||||
#define _TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
|
||||
#define TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
|
||||
#define TIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTI1 Output Generation Enable */
|
||||
#define _TIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */
|
||||
#define _TIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */
|
||||
#define _TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
|
||||
#define TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
|
||||
#define TIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTI2 Output Generation Enable */
|
||||
#define _TIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */
|
||||
#define _TIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */
|
||||
#define _TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */
|
||||
#define TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_DTOGEN */
|
||||
|
||||
/* Bit fields for TIMER DTFAULT */
|
||||
#define _TIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULT */
|
||||
#define _TIMER_DTFAULT_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULT */
|
||||
#define TIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */
|
||||
#define _TIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */
|
||||
#define _TIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */
|
||||
#define _TIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */
|
||||
#define TIMER_DTFAULT_DTPRS0F_DEFAULT (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULT */
|
||||
#define TIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */
|
||||
#define _TIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */
|
||||
#define _TIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */
|
||||
#define _TIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */
|
||||
#define TIMER_DTFAULT_DTPRS1F_DEFAULT (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULT */
|
||||
#define TIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */
|
||||
#define _TIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */
|
||||
#define _TIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */
|
||||
#define _TIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */
|
||||
#define TIMER_DTFAULT_DTDBGF_DEFAULT (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULT */
|
||||
#define TIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */
|
||||
#define _TIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */
|
||||
#define _TIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */
|
||||
#define _TIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */
|
||||
#define TIMER_DTFAULT_DTLOCKUPF_DEFAULT (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULT */
|
||||
|
||||
/* Bit fields for TIMER DTFAULTC */
|
||||
#define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULTC */
|
||||
#define _TIMER_DTFAULTC_MASK 0x0000000FUL /**< Mask for TIMER_DTFAULTC */
|
||||
#define TIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */
|
||||
#define _TIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */
|
||||
#define _TIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */
|
||||
#define _TIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */
|
||||
#define TIMER_DTFAULTC_DTPRS0FC_DEFAULT (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
|
||||
#define TIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */
|
||||
#define _TIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */
|
||||
#define _TIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */
|
||||
#define _TIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */
|
||||
#define TIMER_DTFAULTC_DTPRS1FC_DEFAULT (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
|
||||
#define TIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */
|
||||
#define _TIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */
|
||||
#define _TIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */
|
||||
#define _TIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */
|
||||
#define TIMER_DTFAULTC_DTDBGFC_DEFAULT (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
|
||||
#define TIMER_DTFAULTC_TLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */
|
||||
#define _TIMER_DTFAULTC_TLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_TLOCKUPFC */
|
||||
#define _TIMER_DTFAULTC_TLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_TLOCKUPFC */
|
||||
#define _TIMER_DTFAULTC_TLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */
|
||||
#define TIMER_DTFAULTC_TLOCKUPFC_DEFAULT (_TIMER_DTFAULTC_TLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */
|
||||
|
||||
/* Bit fields for TIMER DTLOCK */
|
||||
#define _TIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTLOCK */
|
||||
#define _TIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_DTLOCK */
|
||||
#define _TIMER_DTLOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */
|
||||
#define _TIMER_DTLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */
|
||||
#define _TIMER_DTLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */
|
||||
#define _TIMER_DTLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for TIMER_DTLOCK */
|
||||
#define _TIMER_DTLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_DTLOCK */
|
||||
#define _TIMER_DTLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_DTLOCK */
|
||||
#define _TIMER_DTLOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */
|
||||
#define TIMER_DTLOCK_LOCKKEY_DEFAULT (_TIMER_DTLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */
|
||||
#define TIMER_DTLOCK_LOCKKEY_LOCK (_TIMER_DTLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for TIMER_DTLOCK */
|
||||
#define TIMER_DTLOCK_LOCKKEY_UNLOCKED (_TIMER_DTLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for TIMER_DTLOCK */
|
||||
#define TIMER_DTLOCK_LOCKKEY_LOCKED (_TIMER_DTLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for TIMER_DTLOCK */
|
||||
#define TIMER_DTLOCK_LOCKKEY_UNLOCK (_TIMER_DTLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */
|
||||
|
||||
/** @} End of group EFM32G_TIMER */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief efm32g_timer_cc Register and Bit Field definitions
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @brief TIMER_CC EFM32G TIMER CC
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< CC Channel Control Register */
|
||||
__IO uint32_t CCV; /**< CC Channel Value Register */
|
||||
__I uint32_t CCVP; /**< CC Channel Value Peek Register */
|
||||
__IO uint32_t CCVB; /**< CC Channel Buffer Register */
|
||||
} TIMER_CC_TypeDef;
|
||||
|
||||
|
|
@ -0,0 +1,989 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief efm32g_uart Register and Bit Field definitions
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_UART_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/* Bit fields for UART CTRL */
|
||||
#define _UART_CTRL_RESETVALUE 0x00000000UL /**< Default value for UART_CTRL */
|
||||
#define _UART_CTRL_MASK 0x1DFFFF7FUL /**< Mask for UART_CTRL */
|
||||
#define UART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */
|
||||
#define _UART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */
|
||||
#define _UART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */
|
||||
#define _UART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_SYNC_DEFAULT (_UART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */
|
||||
#define _UART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */
|
||||
#define _UART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */
|
||||
#define _UART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_LOOPBK_DEFAULT (_UART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */
|
||||
#define _UART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */
|
||||
#define _UART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */
|
||||
#define _UART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_CCEN_DEFAULT (_UART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */
|
||||
#define _UART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */
|
||||
#define _UART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */
|
||||
#define _UART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_MPM_DEFAULT (_UART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */
|
||||
#define _UART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */
|
||||
#define _UART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */
|
||||
#define _UART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_MPAB_DEFAULT (_UART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_CTRL */
|
||||
#define _UART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */
|
||||
#define _UART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */
|
||||
#define _UART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
|
||||
#define _UART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for UART_CTRL */
|
||||
#define _UART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for UART_CTRL */
|
||||
#define _UART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for UART_CTRL */
|
||||
#define _UART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for UART_CTRL */
|
||||
#define UART_CTRL_OVS_DEFAULT (_UART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_OVS_X16 (_UART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for UART_CTRL */
|
||||
#define UART_CTRL_OVS_X8 (_UART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for UART_CTRL */
|
||||
#define UART_CTRL_OVS_X6 (_UART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for UART_CTRL */
|
||||
#define UART_CTRL_OVS_X4 (_UART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for UART_CTRL */
|
||||
#define UART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */
|
||||
#define _UART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */
|
||||
#define _UART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */
|
||||
#define _UART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
|
||||
#define _UART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for UART_CTRL */
|
||||
#define _UART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for UART_CTRL */
|
||||
#define UART_CTRL_CLKPOL_DEFAULT (_UART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_CLKPOL_IDLELOW (_UART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for UART_CTRL */
|
||||
#define UART_CTRL_CLKPOL_IDLEHIGH (_UART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for UART_CTRL */
|
||||
#define UART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge For Setup/Sample */
|
||||
#define _UART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */
|
||||
#define _UART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */
|
||||
#define _UART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
|
||||
#define _UART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for UART_CTRL */
|
||||
#define _UART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for UART_CTRL */
|
||||
#define UART_CTRL_CLKPHA_DEFAULT (_UART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_CLKPHA_SAMPLELEADING (_UART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for UART_CTRL */
|
||||
#define UART_CTRL_CLKPHA_SAMPLETRAILING (_UART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for UART_CTRL */
|
||||
#define UART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */
|
||||
#define _UART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */
|
||||
#define _UART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */
|
||||
#define _UART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_MSBF_DEFAULT (_UART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_CSMA (0x1UL << 11) /**< Action On Slave-Select In Master Mode */
|
||||
#define _UART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */
|
||||
#define _UART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */
|
||||
#define _UART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
|
||||
#define _UART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for UART_CTRL */
|
||||
#define _UART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for UART_CTRL */
|
||||
#define UART_CTRL_CSMA_DEFAULT (_UART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_CSMA_NOACTION (_UART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for UART_CTRL */
|
||||
#define UART_CTRL_CSMA_GOTOSLAVEMODE (_UART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for UART_CTRL */
|
||||
#define UART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */
|
||||
#define _UART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */
|
||||
#define _UART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */
|
||||
#define _UART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
|
||||
#define _UART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for UART_CTRL */
|
||||
#define _UART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for UART_CTRL */
|
||||
#define UART_CTRL_TXBIL_DEFAULT (_UART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_TXBIL_EMPTY (_UART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for UART_CTRL */
|
||||
#define UART_CTRL_TXBIL_HALFFULL (_UART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for UART_CTRL */
|
||||
#define UART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */
|
||||
#define _UART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */
|
||||
#define _UART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */
|
||||
#define _UART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_RXINV_DEFAULT (_UART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_TXINV (0x1UL << 14) /**< Transmitter output Invert */
|
||||
#define _UART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */
|
||||
#define _UART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */
|
||||
#define _UART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_TXINV_DEFAULT (_UART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */
|
||||
#define _UART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */
|
||||
#define _UART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */
|
||||
#define _UART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_CSINV_DEFAULT (_UART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */
|
||||
#define _UART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */
|
||||
#define _UART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */
|
||||
#define _UART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_AUTOCS_DEFAULT (_UART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */
|
||||
#define _UART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */
|
||||
#define _UART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */
|
||||
#define _UART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_AUTOTRI_DEFAULT (_UART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */
|
||||
#define _UART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */
|
||||
#define _UART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */
|
||||
#define _UART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_SCMODE_DEFAULT (_UART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */
|
||||
#define _UART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */
|
||||
#define _UART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */
|
||||
#define _UART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_SCRETRANS_DEFAULT (_UART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */
|
||||
#define _UART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */
|
||||
#define _UART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */
|
||||
#define _UART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_SKIPPERRF_DEFAULT (_UART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */
|
||||
#define _UART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */
|
||||
#define _UART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */
|
||||
#define _UART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_BIT8DV_DEFAULT (_UART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA On Error */
|
||||
#define _UART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */
|
||||
#define _UART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */
|
||||
#define _UART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_ERRSDMA_DEFAULT (_UART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX On Error */
|
||||
#define _UART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */
|
||||
#define _UART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */
|
||||
#define _UART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_ERRSRX_DEFAULT (_UART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX On Error */
|
||||
#define _UART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */
|
||||
#define _UART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */
|
||||
#define _UART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_ERRSTX_DEFAULT (_UART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for UART_CTRL */
|
||||
#define _UART_CTRL_TXDELAY_SHIFT 26 /**< Shift value for USART_TXDELAY */
|
||||
#define _UART_CTRL_TXDELAY_MASK 0xC000000UL /**< Bit mask for USART_TXDELAY */
|
||||
#define _UART_CTRL_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
|
||||
#define _UART_CTRL_TXDELAY_NONE 0x00000000UL /**< Mode NONE for UART_CTRL */
|
||||
#define _UART_CTRL_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for UART_CTRL */
|
||||
#define _UART_CTRL_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for UART_CTRL */
|
||||
#define _UART_CTRL_TXDELAY_TRIPLE 0x00000003UL /**< Mode TRIPLE for UART_CTRL */
|
||||
#define UART_CTRL_TXDELAY_DEFAULT (_UART_CTRL_TXDELAY_DEFAULT << 26) /**< Shifted mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_TXDELAY_NONE (_UART_CTRL_TXDELAY_NONE << 26) /**< Shifted mode NONE for UART_CTRL */
|
||||
#define UART_CTRL_TXDELAY_SINGLE (_UART_CTRL_TXDELAY_SINGLE << 26) /**< Shifted mode SINGLE for UART_CTRL */
|
||||
#define UART_CTRL_TXDELAY_DOUBLE (_UART_CTRL_TXDELAY_DOUBLE << 26) /**< Shifted mode DOUBLE for UART_CTRL */
|
||||
#define UART_CTRL_TXDELAY_TRIPLE (_UART_CTRL_TXDELAY_TRIPLE << 26) /**< Shifted mode TRIPLE for UART_CTRL */
|
||||
#define UART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap In Double Accesses */
|
||||
#define _UART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */
|
||||
#define _UART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */
|
||||
#define _UART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CTRL */
|
||||
#define UART_CTRL_BYTESWAP_DEFAULT (_UART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for UART_CTRL */
|
||||
|
||||
/* Bit fields for UART FRAME */
|
||||
#define _UART_FRAME_RESETVALUE 0x00001005UL /**< Default value for UART_FRAME */
|
||||
#define _UART_FRAME_MASK 0x0000330FUL /**< Mask for UART_FRAME */
|
||||
#define _UART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */
|
||||
#define _UART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */
|
||||
#define _UART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for UART_FRAME */
|
||||
#define _UART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for UART_FRAME */
|
||||
#define _UART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for UART_FRAME */
|
||||
#define _UART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for UART_FRAME */
|
||||
#define _UART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for UART_FRAME */
|
||||
#define _UART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for UART_FRAME */
|
||||
#define _UART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for UART_FRAME */
|
||||
#define _UART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for UART_FRAME */
|
||||
#define _UART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for UART_FRAME */
|
||||
#define _UART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for UART_FRAME */
|
||||
#define _UART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for UART_FRAME */
|
||||
#define _UART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for UART_FRAME */
|
||||
#define _UART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for UART_FRAME */
|
||||
#define _UART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for UART_FRAME */
|
||||
#define UART_FRAME_DATABITS_FOUR (_UART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for UART_FRAME */
|
||||
#define UART_FRAME_DATABITS_FIVE (_UART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for UART_FRAME */
|
||||
#define UART_FRAME_DATABITS_SIX (_UART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for UART_FRAME */
|
||||
#define UART_FRAME_DATABITS_SEVEN (_UART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for UART_FRAME */
|
||||
#define UART_FRAME_DATABITS_DEFAULT (_UART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_FRAME */
|
||||
#define UART_FRAME_DATABITS_EIGHT (_UART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for UART_FRAME */
|
||||
#define UART_FRAME_DATABITS_NINE (_UART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for UART_FRAME */
|
||||
#define UART_FRAME_DATABITS_TEN (_UART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for UART_FRAME */
|
||||
#define UART_FRAME_DATABITS_ELEVEN (_UART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for UART_FRAME */
|
||||
#define UART_FRAME_DATABITS_TWELVE (_UART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for UART_FRAME */
|
||||
#define UART_FRAME_DATABITS_THIRTEEN (_UART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for UART_FRAME */
|
||||
#define UART_FRAME_DATABITS_FOURTEEN (_UART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for UART_FRAME */
|
||||
#define UART_FRAME_DATABITS_FIFTEEN (_UART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for UART_FRAME */
|
||||
#define UART_FRAME_DATABITS_SIXTEEN (_UART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for UART_FRAME */
|
||||
#define _UART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */
|
||||
#define _UART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */
|
||||
#define _UART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_FRAME */
|
||||
#define _UART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for UART_FRAME */
|
||||
#define _UART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for UART_FRAME */
|
||||
#define _UART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for UART_FRAME */
|
||||
#define UART_FRAME_PARITY_DEFAULT (_UART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_FRAME */
|
||||
#define UART_FRAME_PARITY_NONE (_UART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for UART_FRAME */
|
||||
#define UART_FRAME_PARITY_EVEN (_UART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for UART_FRAME */
|
||||
#define UART_FRAME_PARITY_ODD (_UART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for UART_FRAME */
|
||||
#define _UART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */
|
||||
#define _UART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */
|
||||
#define _UART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for UART_FRAME */
|
||||
#define _UART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for UART_FRAME */
|
||||
#define _UART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for UART_FRAME */
|
||||
#define _UART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for UART_FRAME */
|
||||
#define _UART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for UART_FRAME */
|
||||
#define UART_FRAME_STOPBITS_HALF (_UART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for UART_FRAME */
|
||||
#define UART_FRAME_STOPBITS_DEFAULT (_UART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_FRAME */
|
||||
#define UART_FRAME_STOPBITS_ONE (_UART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for UART_FRAME */
|
||||
#define UART_FRAME_STOPBITS_ONEANDAHALF (_UART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for UART_FRAME */
|
||||
#define UART_FRAME_STOPBITS_TWO (_UART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for UART_FRAME */
|
||||
|
||||
/* Bit fields for UART TRIGCTRL */
|
||||
#define _UART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for UART_TRIGCTRL */
|
||||
#define _UART_TRIGCTRL_MASK 0x00000037UL /**< Mask for UART_TRIGCTRL */
|
||||
#define _UART_TRIGCTRL_TSEL_SHIFT 0 /**< Shift value for USART_TSEL */
|
||||
#define _UART_TRIGCTRL_TSEL_MASK 0x7UL /**< Bit mask for USART_TSEL */
|
||||
#define _UART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */
|
||||
#define _UART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for UART_TRIGCTRL */
|
||||
#define _UART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for UART_TRIGCTRL */
|
||||
#define _UART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for UART_TRIGCTRL */
|
||||
#define _UART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for UART_TRIGCTRL */
|
||||
#define _UART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for UART_TRIGCTRL */
|
||||
#define _UART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for UART_TRIGCTRL */
|
||||
#define _UART_TRIGCTRL_TSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for UART_TRIGCTRL */
|
||||
#define _UART_TRIGCTRL_TSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for UART_TRIGCTRL */
|
||||
#define UART_TRIGCTRL_TSEL_DEFAULT (_UART_TRIGCTRL_TSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TRIGCTRL */
|
||||
#define UART_TRIGCTRL_TSEL_PRSCH0 (_UART_TRIGCTRL_TSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for UART_TRIGCTRL */
|
||||
#define UART_TRIGCTRL_TSEL_PRSCH1 (_UART_TRIGCTRL_TSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for UART_TRIGCTRL */
|
||||
#define UART_TRIGCTRL_TSEL_PRSCH2 (_UART_TRIGCTRL_TSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for UART_TRIGCTRL */
|
||||
#define UART_TRIGCTRL_TSEL_PRSCH3 (_UART_TRIGCTRL_TSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for UART_TRIGCTRL */
|
||||
#define UART_TRIGCTRL_TSEL_PRSCH4 (_UART_TRIGCTRL_TSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for UART_TRIGCTRL */
|
||||
#define UART_TRIGCTRL_TSEL_PRSCH5 (_UART_TRIGCTRL_TSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for UART_TRIGCTRL */
|
||||
#define UART_TRIGCTRL_TSEL_PRSCH6 (_UART_TRIGCTRL_TSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for UART_TRIGCTRL */
|
||||
#define UART_TRIGCTRL_TSEL_PRSCH7 (_UART_TRIGCTRL_TSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for UART_TRIGCTRL */
|
||||
#define UART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */
|
||||
#define _UART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */
|
||||
#define _UART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */
|
||||
#define _UART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */
|
||||
#define UART_TRIGCTRL_RXTEN_DEFAULT (_UART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_TRIGCTRL */
|
||||
#define UART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */
|
||||
#define _UART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */
|
||||
#define _UART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */
|
||||
#define _UART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TRIGCTRL */
|
||||
#define UART_TRIGCTRL_TXTEN_DEFAULT (_UART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_TRIGCTRL */
|
||||
|
||||
/* Bit fields for UART CMD */
|
||||
#define _UART_CMD_RESETVALUE 0x00000000UL /**< Default value for UART_CMD */
|
||||
#define _UART_CMD_MASK 0x00000FFFUL /**< Mask for UART_CMD */
|
||||
#define UART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */
|
||||
#define _UART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */
|
||||
#define _UART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */
|
||||
#define _UART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
|
||||
#define UART_CMD_RXEN_DEFAULT (_UART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_CMD */
|
||||
#define UART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */
|
||||
#define _UART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */
|
||||
#define _UART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */
|
||||
#define _UART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
|
||||
#define UART_CMD_RXDIS_DEFAULT (_UART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_CMD */
|
||||
#define UART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */
|
||||
#define _UART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */
|
||||
#define _UART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */
|
||||
#define _UART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
|
||||
#define UART_CMD_TXEN_DEFAULT (_UART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_CMD */
|
||||
#define UART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */
|
||||
#define _UART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */
|
||||
#define _UART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */
|
||||
#define _UART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
|
||||
#define UART_CMD_TXDIS_DEFAULT (_UART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_CMD */
|
||||
#define UART_CMD_MASTEREN (0x1UL << 4) /**< Master Enable */
|
||||
#define _UART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */
|
||||
#define _UART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */
|
||||
#define _UART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
|
||||
#define UART_CMD_MASTEREN_DEFAULT (_UART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_CMD */
|
||||
#define UART_CMD_MASTERDIS (0x1UL << 5) /**< Master Disable */
|
||||
#define _UART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */
|
||||
#define _UART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */
|
||||
#define _UART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
|
||||
#define UART_CMD_MASTERDIS_DEFAULT (_UART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_CMD */
|
||||
#define UART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */
|
||||
#define _UART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */
|
||||
#define _UART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */
|
||||
#define _UART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
|
||||
#define UART_CMD_RXBLOCKEN_DEFAULT (_UART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_CMD */
|
||||
#define UART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */
|
||||
#define _UART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */
|
||||
#define _UART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */
|
||||
#define _UART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
|
||||
#define UART_CMD_RXBLOCKDIS_DEFAULT (_UART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_CMD */
|
||||
#define UART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */
|
||||
#define _UART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */
|
||||
#define _UART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */
|
||||
#define _UART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
|
||||
#define UART_CMD_TXTRIEN_DEFAULT (_UART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_CMD */
|
||||
#define UART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */
|
||||
#define _UART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */
|
||||
#define _UART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */
|
||||
#define _UART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
|
||||
#define UART_CMD_TXTRIDIS_DEFAULT (_UART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_CMD */
|
||||
#define UART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */
|
||||
#define _UART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */
|
||||
#define _UART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */
|
||||
#define _UART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
|
||||
#define UART_CMD_CLEARTX_DEFAULT (_UART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_CMD */
|
||||
#define UART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */
|
||||
#define _UART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */
|
||||
#define _UART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */
|
||||
#define _UART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CMD */
|
||||
#define UART_CMD_CLEARRX_DEFAULT (_UART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_CMD */
|
||||
|
||||
/* Bit fields for UART STATUS */
|
||||
#define _UART_STATUS_RESETVALUE 0x00000040UL /**< Default value for UART_STATUS */
|
||||
#define _UART_STATUS_MASK 0x000001FFUL /**< Mask for UART_STATUS */
|
||||
#define UART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */
|
||||
#define _UART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */
|
||||
#define _UART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */
|
||||
#define _UART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
|
||||
#define UART_STATUS_RXENS_DEFAULT (_UART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_STATUS */
|
||||
#define UART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */
|
||||
#define _UART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */
|
||||
#define _UART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */
|
||||
#define _UART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
|
||||
#define UART_STATUS_TXENS_DEFAULT (_UART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_STATUS */
|
||||
#define UART_STATUS_MASTER (0x1UL << 2) /**< SPI Master Mode */
|
||||
#define _UART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */
|
||||
#define _UART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */
|
||||
#define _UART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
|
||||
#define UART_STATUS_MASTER_DEFAULT (_UART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_STATUS */
|
||||
#define UART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */
|
||||
#define _UART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */
|
||||
#define _UART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */
|
||||
#define _UART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
|
||||
#define UART_STATUS_RXBLOCK_DEFAULT (_UART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_STATUS */
|
||||
#define UART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */
|
||||
#define _UART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */
|
||||
#define _UART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */
|
||||
#define _UART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
|
||||
#define UART_STATUS_TXTRI_DEFAULT (_UART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_STATUS */
|
||||
#define UART_STATUS_TXC (0x1UL << 5) /**< TX Complete */
|
||||
#define _UART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */
|
||||
#define _UART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */
|
||||
#define _UART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
|
||||
#define UART_STATUS_TXC_DEFAULT (_UART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_STATUS */
|
||||
#define UART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */
|
||||
#define _UART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */
|
||||
#define _UART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */
|
||||
#define _UART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for UART_STATUS */
|
||||
#define UART_STATUS_TXBL_DEFAULT (_UART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_STATUS */
|
||||
#define UART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */
|
||||
#define _UART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */
|
||||
#define _UART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */
|
||||
#define _UART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
|
||||
#define UART_STATUS_RXDATAV_DEFAULT (_UART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_STATUS */
|
||||
#define UART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */
|
||||
#define _UART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */
|
||||
#define _UART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */
|
||||
#define _UART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_STATUS */
|
||||
#define UART_STATUS_RXFULL_DEFAULT (_UART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_STATUS */
|
||||
|
||||
/* Bit fields for UART CLKDIV */
|
||||
#define _UART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for UART_CLKDIV */
|
||||
#define _UART_CLKDIV_MASK 0x001FFFC0UL /**< Mask for UART_CLKDIV */
|
||||
#define _UART_CLKDIV_DIV_SHIFT 6 /**< Shift value for USART_DIV */
|
||||
#define _UART_CLKDIV_DIV_MASK 0x1FFFC0UL /**< Bit mask for USART_DIV */
|
||||
#define _UART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_CLKDIV */
|
||||
#define UART_CLKDIV_DIV_DEFAULT (_UART_CLKDIV_DIV_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_CLKDIV */
|
||||
|
||||
/* Bit fields for UART RXDATAX */
|
||||
#define _UART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for UART_RXDATAX */
|
||||
#define _UART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for UART_RXDATAX */
|
||||
#define _UART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */
|
||||
#define _UART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */
|
||||
#define _UART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAX */
|
||||
#define UART_RXDATAX_RXDATA_DEFAULT (_UART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDATAX */
|
||||
#define UART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */
|
||||
#define _UART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */
|
||||
#define _UART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */
|
||||
#define _UART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAX */
|
||||
#define UART_RXDATAX_PERR_DEFAULT (_UART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_RXDATAX */
|
||||
#define UART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */
|
||||
#define _UART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */
|
||||
#define _UART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */
|
||||
#define _UART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAX */
|
||||
#define UART_RXDATAX_FERR_DEFAULT (_UART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_RXDATAX */
|
||||
|
||||
/* Bit fields for UART RXDATA */
|
||||
#define _UART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for UART_RXDATA */
|
||||
#define _UART_RXDATA_MASK 0x000000FFUL /**< Mask for UART_RXDATA */
|
||||
#define _UART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */
|
||||
#define _UART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */
|
||||
#define _UART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATA */
|
||||
#define UART_RXDATA_RXDATA_DEFAULT (_UART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDATA */
|
||||
|
||||
/* Bit fields for UART RXDOUBLEX */
|
||||
#define _UART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for UART_RXDOUBLEX */
|
||||
#define _UART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for UART_RXDOUBLEX */
|
||||
#define _UART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */
|
||||
#define _UART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */
|
||||
#define _UART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */
|
||||
#define UART_RXDOUBLEX_RXDATA0_DEFAULT (_UART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */
|
||||
#define UART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */
|
||||
#define _UART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */
|
||||
#define _UART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */
|
||||
#define _UART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */
|
||||
#define UART_RXDOUBLEX_PERR0_DEFAULT (_UART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */
|
||||
#define UART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */
|
||||
#define _UART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */
|
||||
#define _UART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */
|
||||
#define _UART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */
|
||||
#define UART_RXDOUBLEX_FERR0_DEFAULT (_UART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */
|
||||
#define _UART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */
|
||||
#define _UART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */
|
||||
#define _UART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */
|
||||
#define UART_RXDOUBLEX_RXDATA1_DEFAULT (_UART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */
|
||||
#define UART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */
|
||||
#define _UART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */
|
||||
#define _UART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */
|
||||
#define _UART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */
|
||||
#define UART_RXDOUBLEX_PERR1_DEFAULT (_UART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */
|
||||
#define UART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */
|
||||
#define _UART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */
|
||||
#define _UART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */
|
||||
#define _UART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEX */
|
||||
#define UART_RXDOUBLEX_FERR1_DEFAULT (_UART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for UART_RXDOUBLEX */
|
||||
|
||||
/* Bit fields for UART RXDOUBLE */
|
||||
#define _UART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for UART_RXDOUBLE */
|
||||
#define _UART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for UART_RXDOUBLE */
|
||||
#define _UART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */
|
||||
#define _UART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */
|
||||
#define _UART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLE */
|
||||
#define UART_RXDOUBLE_RXDATA0_DEFAULT (_UART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDOUBLE */
|
||||
#define _UART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */
|
||||
#define _UART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */
|
||||
#define _UART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLE */
|
||||
#define UART_RXDOUBLE_RXDATA1_DEFAULT (_UART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_RXDOUBLE */
|
||||
|
||||
/* Bit fields for UART RXDATAXP */
|
||||
#define _UART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for UART_RXDATAXP */
|
||||
#define _UART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for UART_RXDATAXP */
|
||||
#define _UART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */
|
||||
#define _UART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */
|
||||
#define _UART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAXP */
|
||||
#define UART_RXDATAXP_RXDATAP_DEFAULT (_UART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDATAXP */
|
||||
#define UART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */
|
||||
#define _UART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */
|
||||
#define _UART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */
|
||||
#define _UART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAXP */
|
||||
#define UART_RXDATAXP_PERRP_DEFAULT (_UART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_RXDATAXP */
|
||||
#define UART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */
|
||||
#define _UART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */
|
||||
#define _UART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */
|
||||
#define _UART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDATAXP */
|
||||
#define UART_RXDATAXP_FERRP_DEFAULT (_UART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_RXDATAXP */
|
||||
|
||||
/* Bit fields for UART RXDOUBLEXP */
|
||||
#define _UART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for UART_RXDOUBLEXP */
|
||||
#define _UART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for UART_RXDOUBLEXP */
|
||||
#define _UART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */
|
||||
#define _UART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */
|
||||
#define _UART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */
|
||||
#define UART_RXDOUBLEXP_RXDATAP0_DEFAULT (_UART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */
|
||||
#define UART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */
|
||||
#define _UART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */
|
||||
#define _UART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */
|
||||
#define _UART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */
|
||||
#define UART_RXDOUBLEXP_PERRP0_DEFAULT (_UART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */
|
||||
#define UART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */
|
||||
#define _UART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */
|
||||
#define _UART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */
|
||||
#define _UART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */
|
||||
#define UART_RXDOUBLEXP_FERRP0_DEFAULT (_UART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */
|
||||
#define _UART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */
|
||||
#define _UART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */
|
||||
#define _UART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */
|
||||
#define UART_RXDOUBLEXP_RXDATAP1_DEFAULT (_UART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */
|
||||
#define UART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */
|
||||
#define _UART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */
|
||||
#define _UART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */
|
||||
#define _UART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */
|
||||
#define UART_RXDOUBLEXP_PERRP1_DEFAULT (_UART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */
|
||||
#define UART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */
|
||||
#define _UART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */
|
||||
#define _UART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */
|
||||
#define _UART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_RXDOUBLEXP */
|
||||
#define UART_RXDOUBLEXP_FERRP1_DEFAULT (_UART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for UART_RXDOUBLEXP */
|
||||
|
||||
/* Bit fields for UART TXDATAX */
|
||||
#define _UART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for UART_TXDATAX */
|
||||
#define _UART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for UART_TXDATAX */
|
||||
#define _UART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */
|
||||
#define _UART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */
|
||||
#define _UART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */
|
||||
#define UART_TXDATAX_TXDATAX_DEFAULT (_UART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TXDATAX */
|
||||
#define UART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */
|
||||
#define _UART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */
|
||||
#define _UART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */
|
||||
#define _UART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */
|
||||
#define UART_TXDATAX_UBRXAT_DEFAULT (_UART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_TXDATAX */
|
||||
#define UART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */
|
||||
#define _UART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */
|
||||
#define _UART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */
|
||||
#define _UART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */
|
||||
#define UART_TXDATAX_TXTRIAT_DEFAULT (_UART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_TXDATAX */
|
||||
#define UART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */
|
||||
#define _UART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */
|
||||
#define _UART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */
|
||||
#define _UART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */
|
||||
#define UART_TXDATAX_TXBREAK_DEFAULT (_UART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for UART_TXDATAX */
|
||||
#define UART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */
|
||||
#define _UART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */
|
||||
#define _UART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */
|
||||
#define _UART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */
|
||||
#define UART_TXDATAX_TXDISAT_DEFAULT (_UART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_TXDATAX */
|
||||
#define UART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */
|
||||
#define _UART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */
|
||||
#define _UART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */
|
||||
#define _UART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATAX */
|
||||
#define UART_TXDATAX_RXENAT_DEFAULT (_UART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_TXDATAX */
|
||||
|
||||
/* Bit fields for UART TXDATA */
|
||||
#define _UART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for UART_TXDATA */
|
||||
#define _UART_TXDATA_MASK 0x000000FFUL /**< Mask for UART_TXDATA */
|
||||
#define _UART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */
|
||||
#define _UART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */
|
||||
#define _UART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDATA */
|
||||
#define UART_TXDATA_TXDATA_DEFAULT (_UART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TXDATA */
|
||||
|
||||
/* Bit fields for UART TXDOUBLEX */
|
||||
#define _UART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for UART_TXDOUBLEX */
|
||||
#define _UART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for UART_TXDOUBLEX */
|
||||
#define _UART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */
|
||||
#define _UART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */
|
||||
#define _UART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
|
||||
#define UART_TXDOUBLEX_TXDATA0_DEFAULT (_UART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
|
||||
#define UART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */
|
||||
#define _UART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */
|
||||
#define _UART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */
|
||||
#define _UART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
|
||||
#define UART_TXDOUBLEX_UBRXAT0_DEFAULT (_UART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
|
||||
#define UART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */
|
||||
#define _UART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */
|
||||
#define _UART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */
|
||||
#define _UART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
|
||||
#define UART_TXDOUBLEX_TXTRIAT0_DEFAULT (_UART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
|
||||
#define UART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data As Break */
|
||||
#define _UART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */
|
||||
#define _UART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */
|
||||
#define _UART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
|
||||
#define UART_TXDOUBLEX_TXBREAK0_DEFAULT (_UART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
|
||||
#define UART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */
|
||||
#define _UART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */
|
||||
#define _UART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */
|
||||
#define _UART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
|
||||
#define UART_TXDOUBLEX_TXDISAT0_DEFAULT (_UART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
|
||||
#define UART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */
|
||||
#define _UART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */
|
||||
#define _UART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */
|
||||
#define _UART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
|
||||
#define UART_TXDOUBLEX_RXENAT0_DEFAULT (_UART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
|
||||
#define _UART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */
|
||||
#define _UART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */
|
||||
#define _UART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
|
||||
#define UART_TXDOUBLEX_TXDATA1_DEFAULT (_UART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
|
||||
#define UART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */
|
||||
#define _UART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */
|
||||
#define _UART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */
|
||||
#define _UART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
|
||||
#define UART_TXDOUBLEX_UBRXAT1_DEFAULT (_UART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
|
||||
#define UART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */
|
||||
#define _UART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */
|
||||
#define _UART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */
|
||||
#define _UART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
|
||||
#define UART_TXDOUBLEX_TXTRIAT1_DEFAULT (_UART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
|
||||
#define UART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data As Break */
|
||||
#define _UART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */
|
||||
#define _UART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */
|
||||
#define _UART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
|
||||
#define UART_TXDOUBLEX_TXBREAK1_DEFAULT (_UART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
|
||||
#define UART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */
|
||||
#define _UART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */
|
||||
#define _UART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */
|
||||
#define _UART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
|
||||
#define UART_TXDOUBLEX_TXDISAT1_DEFAULT (_UART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
|
||||
#define UART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */
|
||||
#define _UART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */
|
||||
#define _UART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */
|
||||
#define _UART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLEX */
|
||||
#define UART_TXDOUBLEX_RXENAT1_DEFAULT (_UART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for UART_TXDOUBLEX */
|
||||
|
||||
/* Bit fields for UART TXDOUBLE */
|
||||
#define _UART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for UART_TXDOUBLE */
|
||||
#define _UART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for UART_TXDOUBLE */
|
||||
#define _UART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */
|
||||
#define _UART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */
|
||||
#define _UART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLE */
|
||||
#define UART_TXDOUBLE_TXDATA0_DEFAULT (_UART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_TXDOUBLE */
|
||||
#define _UART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */
|
||||
#define _UART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */
|
||||
#define _UART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_TXDOUBLE */
|
||||
#define UART_TXDOUBLE_TXDATA1_DEFAULT (_UART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_TXDOUBLE */
|
||||
|
||||
/* Bit fields for UART IF */
|
||||
#define _UART_IF_RESETVALUE 0x00000002UL /**< Default value for UART_IF */
|
||||
#define _UART_IF_MASK 0x00001FFFUL /**< Mask for UART_IF */
|
||||
#define UART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */
|
||||
#define _UART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */
|
||||
#define _UART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
|
||||
#define _UART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
|
||||
#define UART_IF_TXC_DEFAULT (_UART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_IF */
|
||||
#define UART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */
|
||||
#define _UART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */
|
||||
#define _UART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */
|
||||
#define _UART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for UART_IF */
|
||||
#define UART_IF_TXBL_DEFAULT (_UART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_IF */
|
||||
#define UART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */
|
||||
#define _UART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */
|
||||
#define _UART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */
|
||||
#define _UART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
|
||||
#define UART_IF_RXDATAV_DEFAULT (_UART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_IF */
|
||||
#define UART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */
|
||||
#define _UART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
|
||||
#define _UART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
|
||||
#define _UART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
|
||||
#define UART_IF_RXFULL_DEFAULT (_UART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_IF */
|
||||
#define UART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */
|
||||
#define _UART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
|
||||
#define _UART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
|
||||
#define _UART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
|
||||
#define UART_IF_RXOF_DEFAULT (_UART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_IF */
|
||||
#define UART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */
|
||||
#define _UART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
|
||||
#define _UART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
|
||||
#define _UART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
|
||||
#define UART_IF_RXUF_DEFAULT (_UART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_IF */
|
||||
#define UART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */
|
||||
#define _UART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
|
||||
#define _UART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
|
||||
#define _UART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
|
||||
#define UART_IF_TXOF_DEFAULT (_UART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_IF */
|
||||
#define UART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */
|
||||
#define _UART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
|
||||
#define _UART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
|
||||
#define _UART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
|
||||
#define UART_IF_TXUF_DEFAULT (_UART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_IF */
|
||||
#define UART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */
|
||||
#define _UART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */
|
||||
#define _UART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
|
||||
#define _UART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
|
||||
#define UART_IF_PERR_DEFAULT (_UART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_IF */
|
||||
#define UART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */
|
||||
#define _UART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */
|
||||
#define _UART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
|
||||
#define _UART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
|
||||
#define UART_IF_FERR_DEFAULT (_UART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_IF */
|
||||
#define UART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt Flag */
|
||||
#define _UART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
|
||||
#define _UART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
|
||||
#define _UART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
|
||||
#define UART_IF_MPAF_DEFAULT (_UART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_IF */
|
||||
#define UART_IF_SSM (0x1UL << 11) /**< Slave-Select In Master Mode Interrupt Flag */
|
||||
#define _UART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */
|
||||
#define _UART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
|
||||
#define _UART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
|
||||
#define UART_IF_SSM_DEFAULT (_UART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_IF */
|
||||
#define UART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */
|
||||
#define _UART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */
|
||||
#define _UART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
|
||||
#define _UART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IF */
|
||||
#define UART_IF_CCF_DEFAULT (_UART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_IF */
|
||||
|
||||
/* Bit fields for UART IFS */
|
||||
#define _UART_IFS_RESETVALUE 0x00000000UL /**< Default value for UART_IFS */
|
||||
#define _UART_IFS_MASK 0x00001FF9UL /**< Mask for UART_IFS */
|
||||
#define UART_IFS_TXC (0x1UL << 0) /**< Set TX Complete Interrupt Flag */
|
||||
#define _UART_IFS_TXC_SHIFT 0 /**< Shift value for USART_TXC */
|
||||
#define _UART_IFS_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
|
||||
#define _UART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
|
||||
#define UART_IFS_TXC_DEFAULT (_UART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_IFS */
|
||||
#define UART_IFS_RXFULL (0x1UL << 3) /**< Set RX Buffer Full Interrupt Flag */
|
||||
#define _UART_IFS_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
|
||||
#define _UART_IFS_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
|
||||
#define _UART_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
|
||||
#define UART_IFS_RXFULL_DEFAULT (_UART_IFS_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_IFS */
|
||||
#define UART_IFS_RXOF (0x1UL << 4) /**< Set RX Overflow Interrupt Flag */
|
||||
#define _UART_IFS_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
|
||||
#define _UART_IFS_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
|
||||
#define _UART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
|
||||
#define UART_IFS_RXOF_DEFAULT (_UART_IFS_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_IFS */
|
||||
#define UART_IFS_RXUF (0x1UL << 5) /**< Set RX Underflow Interrupt Flag */
|
||||
#define _UART_IFS_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
|
||||
#define _UART_IFS_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
|
||||
#define _UART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
|
||||
#define UART_IFS_RXUF_DEFAULT (_UART_IFS_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_IFS */
|
||||
#define UART_IFS_TXOF (0x1UL << 6) /**< Set TX Overflow Interrupt Flag */
|
||||
#define _UART_IFS_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
|
||||
#define _UART_IFS_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
|
||||
#define _UART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
|
||||
#define UART_IFS_TXOF_DEFAULT (_UART_IFS_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_IFS */
|
||||
#define UART_IFS_TXUF (0x1UL << 7) /**< Set TX Underflow Interrupt Flag */
|
||||
#define _UART_IFS_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
|
||||
#define _UART_IFS_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
|
||||
#define _UART_IFS_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
|
||||
#define UART_IFS_TXUF_DEFAULT (_UART_IFS_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_IFS */
|
||||
#define UART_IFS_PERR (0x1UL << 8) /**< Set Parity Error Interrupt Flag */
|
||||
#define _UART_IFS_PERR_SHIFT 8 /**< Shift value for USART_PERR */
|
||||
#define _UART_IFS_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
|
||||
#define _UART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
|
||||
#define UART_IFS_PERR_DEFAULT (_UART_IFS_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_IFS */
|
||||
#define UART_IFS_FERR (0x1UL << 9) /**< Set Framing Error Interrupt Flag */
|
||||
#define _UART_IFS_FERR_SHIFT 9 /**< Shift value for USART_FERR */
|
||||
#define _UART_IFS_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
|
||||
#define _UART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
|
||||
#define UART_IFS_FERR_DEFAULT (_UART_IFS_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_IFS */
|
||||
#define UART_IFS_MPAF (0x1UL << 10) /**< Set Multi-Processor Address Frame Interrupt Flag */
|
||||
#define _UART_IFS_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
|
||||
#define _UART_IFS_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
|
||||
#define _UART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
|
||||
#define UART_IFS_MPAF_DEFAULT (_UART_IFS_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_IFS */
|
||||
#define UART_IFS_SSM (0x1UL << 11) /**< Set Slave-Select in Master mode Interrupt Flag */
|
||||
#define _UART_IFS_SSM_SHIFT 11 /**< Shift value for USART_SSM */
|
||||
#define _UART_IFS_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
|
||||
#define _UART_IFS_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
|
||||
#define UART_IFS_SSM_DEFAULT (_UART_IFS_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_IFS */
|
||||
#define UART_IFS_CCF (0x1UL << 12) /**< Set Collision Check Fail Interrupt Flag */
|
||||
#define _UART_IFS_CCF_SHIFT 12 /**< Shift value for USART_CCF */
|
||||
#define _UART_IFS_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
|
||||
#define _UART_IFS_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFS */
|
||||
#define UART_IFS_CCF_DEFAULT (_UART_IFS_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_IFS */
|
||||
|
||||
/* Bit fields for UART IFC */
|
||||
#define _UART_IFC_RESETVALUE 0x00000000UL /**< Default value for UART_IFC */
|
||||
#define _UART_IFC_MASK 0x00001FF9UL /**< Mask for UART_IFC */
|
||||
#define UART_IFC_TXC (0x1UL << 0) /**< Clear TX Complete Interrupt Flag */
|
||||
#define _UART_IFC_TXC_SHIFT 0 /**< Shift value for USART_TXC */
|
||||
#define _UART_IFC_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
|
||||
#define _UART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
|
||||
#define UART_IFC_TXC_DEFAULT (_UART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_IFC */
|
||||
#define UART_IFC_RXFULL (0x1UL << 3) /**< Clear RX Buffer Full Interrupt Flag */
|
||||
#define _UART_IFC_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
|
||||
#define _UART_IFC_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
|
||||
#define _UART_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
|
||||
#define UART_IFC_RXFULL_DEFAULT (_UART_IFC_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_IFC */
|
||||
#define UART_IFC_RXOF (0x1UL << 4) /**< Clear RX Overflow Interrupt Flag */
|
||||
#define _UART_IFC_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
|
||||
#define _UART_IFC_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
|
||||
#define _UART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
|
||||
#define UART_IFC_RXOF_DEFAULT (_UART_IFC_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_IFC */
|
||||
#define UART_IFC_RXUF (0x1UL << 5) /**< Clear RX Underflow Interrupt Flag */
|
||||
#define _UART_IFC_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
|
||||
#define _UART_IFC_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
|
||||
#define _UART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
|
||||
#define UART_IFC_RXUF_DEFAULT (_UART_IFC_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_IFC */
|
||||
#define UART_IFC_TXOF (0x1UL << 6) /**< Clear TX Overflow Interrupt Flag */
|
||||
#define _UART_IFC_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
|
||||
#define _UART_IFC_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
|
||||
#define _UART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
|
||||
#define UART_IFC_TXOF_DEFAULT (_UART_IFC_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_IFC */
|
||||
#define UART_IFC_TXUF (0x1UL << 7) /**< Clear TX Underflow Interrupt Flag */
|
||||
#define _UART_IFC_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
|
||||
#define _UART_IFC_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
|
||||
#define _UART_IFC_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
|
||||
#define UART_IFC_TXUF_DEFAULT (_UART_IFC_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_IFC */
|
||||
#define UART_IFC_PERR (0x1UL << 8) /**< Clear Parity Error Interrupt Flag */
|
||||
#define _UART_IFC_PERR_SHIFT 8 /**< Shift value for USART_PERR */
|
||||
#define _UART_IFC_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
|
||||
#define _UART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
|
||||
#define UART_IFC_PERR_DEFAULT (_UART_IFC_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_IFC */
|
||||
#define UART_IFC_FERR (0x1UL << 9) /**< Clear Framing Error Interrupt Flag */
|
||||
#define _UART_IFC_FERR_SHIFT 9 /**< Shift value for USART_FERR */
|
||||
#define _UART_IFC_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
|
||||
#define _UART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
|
||||
#define UART_IFC_FERR_DEFAULT (_UART_IFC_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_IFC */
|
||||
#define UART_IFC_MPAF (0x1UL << 10) /**< Clear Multi-Processor Address Frame Interrupt Flag */
|
||||
#define _UART_IFC_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
|
||||
#define _UART_IFC_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
|
||||
#define _UART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
|
||||
#define UART_IFC_MPAF_DEFAULT (_UART_IFC_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_IFC */
|
||||
#define UART_IFC_SSM (0x1UL << 11) /**< Clear Slave-Select In Master Mode Interrupt Flag */
|
||||
#define _UART_IFC_SSM_SHIFT 11 /**< Shift value for USART_SSM */
|
||||
#define _UART_IFC_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
|
||||
#define _UART_IFC_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
|
||||
#define UART_IFC_SSM_DEFAULT (_UART_IFC_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_IFC */
|
||||
#define UART_IFC_CCF (0x1UL << 12) /**< Clear Collision Check Fail Interrupt Flag */
|
||||
#define _UART_IFC_CCF_SHIFT 12 /**< Shift value for USART_CCF */
|
||||
#define _UART_IFC_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
|
||||
#define _UART_IFC_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IFC */
|
||||
#define UART_IFC_CCF_DEFAULT (_UART_IFC_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_IFC */
|
||||
|
||||
/* Bit fields for UART IEN */
|
||||
#define _UART_IEN_RESETVALUE 0x00000000UL /**< Default value for UART_IEN */
|
||||
#define _UART_IEN_MASK 0x00001FFFUL /**< Mask for UART_IEN */
|
||||
#define UART_IEN_TXC (0x1UL << 0) /**< TX Complete Interrupt Enable */
|
||||
#define _UART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */
|
||||
#define _UART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
|
||||
#define _UART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
|
||||
#define UART_IEN_TXC_DEFAULT (_UART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_IEN */
|
||||
#define UART_IEN_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Enable */
|
||||
#define _UART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */
|
||||
#define _UART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */
|
||||
#define _UART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
|
||||
#define UART_IEN_TXBL_DEFAULT (_UART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_IEN */
|
||||
#define UART_IEN_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Enable */
|
||||
#define _UART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */
|
||||
#define _UART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */
|
||||
#define _UART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
|
||||
#define UART_IEN_RXDATAV_DEFAULT (_UART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_IEN */
|
||||
#define UART_IEN_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Enable */
|
||||
#define _UART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
|
||||
#define _UART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
|
||||
#define _UART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
|
||||
#define UART_IEN_RXFULL_DEFAULT (_UART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_IEN */
|
||||
#define UART_IEN_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Enable */
|
||||
#define _UART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
|
||||
#define _UART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
|
||||
#define _UART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
|
||||
#define UART_IEN_RXOF_DEFAULT (_UART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_IEN */
|
||||
#define UART_IEN_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Enable */
|
||||
#define _UART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
|
||||
#define _UART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
|
||||
#define _UART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
|
||||
#define UART_IEN_RXUF_DEFAULT (_UART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for UART_IEN */
|
||||
#define UART_IEN_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Enable */
|
||||
#define _UART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
|
||||
#define _UART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
|
||||
#define _UART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
|
||||
#define UART_IEN_TXOF_DEFAULT (_UART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for UART_IEN */
|
||||
#define UART_IEN_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Enable */
|
||||
#define _UART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
|
||||
#define _UART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
|
||||
#define _UART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
|
||||
#define UART_IEN_TXUF_DEFAULT (_UART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_IEN */
|
||||
#define UART_IEN_PERR (0x1UL << 8) /**< Parity Error Interrupt Enable */
|
||||
#define _UART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */
|
||||
#define _UART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
|
||||
#define _UART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
|
||||
#define UART_IEN_PERR_DEFAULT (_UART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_IEN */
|
||||
#define UART_IEN_FERR (0x1UL << 9) /**< Framing Error Interrupt Enable */
|
||||
#define _UART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */
|
||||
#define _UART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
|
||||
#define _UART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
|
||||
#define UART_IEN_FERR_DEFAULT (_UART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for UART_IEN */
|
||||
#define UART_IEN_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt Enable */
|
||||
#define _UART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
|
||||
#define _UART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
|
||||
#define _UART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
|
||||
#define UART_IEN_MPAF_DEFAULT (_UART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for UART_IEN */
|
||||
#define UART_IEN_SSM (0x1UL << 11) /**< Slave-Select In Master Mode Interrupt Enable */
|
||||
#define _UART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */
|
||||
#define _UART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
|
||||
#define _UART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
|
||||
#define UART_IEN_SSM_DEFAULT (_UART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for UART_IEN */
|
||||
#define UART_IEN_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Enable */
|
||||
#define _UART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */
|
||||
#define _UART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
|
||||
#define _UART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IEN */
|
||||
#define UART_IEN_CCF_DEFAULT (_UART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for UART_IEN */
|
||||
|
||||
/* Bit fields for UART IRCTRL */
|
||||
#define _UART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for UART_IRCTRL */
|
||||
#define _UART_IRCTRL_MASK 0x000000FFUL /**< Mask for UART_IRCTRL */
|
||||
#define UART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */
|
||||
#define _UART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */
|
||||
#define _UART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */
|
||||
#define _UART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */
|
||||
#define UART_IRCTRL_IREN_DEFAULT (_UART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_IRCTRL */
|
||||
#define _UART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */
|
||||
#define _UART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */
|
||||
#define _UART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */
|
||||
#define _UART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for UART_IRCTRL */
|
||||
#define _UART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for UART_IRCTRL */
|
||||
#define _UART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for UART_IRCTRL */
|
||||
#define _UART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for UART_IRCTRL */
|
||||
#define UART_IRCTRL_IRPW_DEFAULT (_UART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_IRCTRL */
|
||||
#define UART_IRCTRL_IRPW_ONE (_UART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for UART_IRCTRL */
|
||||
#define UART_IRCTRL_IRPW_TWO (_UART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for UART_IRCTRL */
|
||||
#define UART_IRCTRL_IRPW_THREE (_UART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for UART_IRCTRL */
|
||||
#define UART_IRCTRL_IRPW_FOUR (_UART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for UART_IRCTRL */
|
||||
#define UART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */
|
||||
#define _UART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */
|
||||
#define _UART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */
|
||||
#define _UART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */
|
||||
#define UART_IRCTRL_IRFILT_DEFAULT (_UART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_IRCTRL */
|
||||
#define _UART_IRCTRL_IRPRSSEL_SHIFT 4 /**< Shift value for USART_IRPRSSEL */
|
||||
#define _UART_IRCTRL_IRPRSSEL_MASK 0x70UL /**< Bit mask for USART_IRPRSSEL */
|
||||
#define _UART_IRCTRL_IRPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */
|
||||
#define _UART_IRCTRL_IRPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for UART_IRCTRL */
|
||||
#define _UART_IRCTRL_IRPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for UART_IRCTRL */
|
||||
#define _UART_IRCTRL_IRPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for UART_IRCTRL */
|
||||
#define _UART_IRCTRL_IRPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for UART_IRCTRL */
|
||||
#define _UART_IRCTRL_IRPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for UART_IRCTRL */
|
||||
#define _UART_IRCTRL_IRPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for UART_IRCTRL */
|
||||
#define _UART_IRCTRL_IRPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for UART_IRCTRL */
|
||||
#define _UART_IRCTRL_IRPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for UART_IRCTRL */
|
||||
#define UART_IRCTRL_IRPRSSEL_DEFAULT (_UART_IRCTRL_IRPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for UART_IRCTRL */
|
||||
#define UART_IRCTRL_IRPRSSEL_PRSCH0 (_UART_IRCTRL_IRPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for UART_IRCTRL */
|
||||
#define UART_IRCTRL_IRPRSSEL_PRSCH1 (_UART_IRCTRL_IRPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for UART_IRCTRL */
|
||||
#define UART_IRCTRL_IRPRSSEL_PRSCH2 (_UART_IRCTRL_IRPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for UART_IRCTRL */
|
||||
#define UART_IRCTRL_IRPRSSEL_PRSCH3 (_UART_IRCTRL_IRPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for UART_IRCTRL */
|
||||
#define UART_IRCTRL_IRPRSSEL_PRSCH4 (_UART_IRCTRL_IRPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for UART_IRCTRL */
|
||||
#define UART_IRCTRL_IRPRSSEL_PRSCH5 (_UART_IRCTRL_IRPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for UART_IRCTRL */
|
||||
#define UART_IRCTRL_IRPRSSEL_PRSCH6 (_UART_IRCTRL_IRPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for UART_IRCTRL */
|
||||
#define UART_IRCTRL_IRPRSSEL_PRSCH7 (_UART_IRCTRL_IRPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for UART_IRCTRL */
|
||||
#define UART_IRCTRL_IRPRSEN (0x1UL << 7) /**< IrDA PRS Channel Enable */
|
||||
#define _UART_IRCTRL_IRPRSEN_SHIFT 7 /**< Shift value for USART_IRPRSEN */
|
||||
#define _UART_IRCTRL_IRPRSEN_MASK 0x80UL /**< Bit mask for USART_IRPRSEN */
|
||||
#define _UART_IRCTRL_IRPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_IRCTRL */
|
||||
#define UART_IRCTRL_IRPRSEN_DEFAULT (_UART_IRCTRL_IRPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for UART_IRCTRL */
|
||||
|
||||
/* Bit fields for UART ROUTE */
|
||||
#define _UART_ROUTE_RESETVALUE 0x00000000UL /**< Default value for UART_ROUTE */
|
||||
#define _UART_ROUTE_MASK 0x0000030FUL /**< Mask for UART_ROUTE */
|
||||
#define UART_ROUTE_RXPEN (0x1UL << 0) /**< RX Pin Enable */
|
||||
#define _UART_ROUTE_RXPEN_SHIFT 0 /**< Shift value for USART_RXPEN */
|
||||
#define _UART_ROUTE_RXPEN_MASK 0x1UL /**< Bit mask for USART_RXPEN */
|
||||
#define _UART_ROUTE_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTE */
|
||||
#define UART_ROUTE_RXPEN_DEFAULT (_UART_ROUTE_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for UART_ROUTE */
|
||||
#define UART_ROUTE_TXPEN (0x1UL << 1) /**< TX Pin Enable */
|
||||
#define _UART_ROUTE_TXPEN_SHIFT 1 /**< Shift value for USART_TXPEN */
|
||||
#define _UART_ROUTE_TXPEN_MASK 0x2UL /**< Bit mask for USART_TXPEN */
|
||||
#define _UART_ROUTE_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTE */
|
||||
#define UART_ROUTE_TXPEN_DEFAULT (_UART_ROUTE_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for UART_ROUTE */
|
||||
#define UART_ROUTE_CSPEN (0x1UL << 2) /**< CS Pin Enable */
|
||||
#define _UART_ROUTE_CSPEN_SHIFT 2 /**< Shift value for USART_CSPEN */
|
||||
#define _UART_ROUTE_CSPEN_MASK 0x4UL /**< Bit mask for USART_CSPEN */
|
||||
#define _UART_ROUTE_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTE */
|
||||
#define UART_ROUTE_CSPEN_DEFAULT (_UART_ROUTE_CSPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for UART_ROUTE */
|
||||
#define UART_ROUTE_CLKPEN (0x1UL << 3) /**< CLK Pin Enable */
|
||||
#define _UART_ROUTE_CLKPEN_SHIFT 3 /**< Shift value for USART_CLKPEN */
|
||||
#define _UART_ROUTE_CLKPEN_MASK 0x8UL /**< Bit mask for USART_CLKPEN */
|
||||
#define _UART_ROUTE_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTE */
|
||||
#define UART_ROUTE_CLKPEN_DEFAULT (_UART_ROUTE_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for UART_ROUTE */
|
||||
#define _UART_ROUTE_LOCATION_SHIFT 8 /**< Shift value for USART_LOCATION */
|
||||
#define _UART_ROUTE_LOCATION_MASK 0x300UL /**< Bit mask for USART_LOCATION */
|
||||
#define _UART_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for UART_ROUTE */
|
||||
#define _UART_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for UART_ROUTE */
|
||||
#define _UART_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for UART_ROUTE */
|
||||
#define _UART_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for UART_ROUTE */
|
||||
#define _UART_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for UART_ROUTE */
|
||||
#define UART_ROUTE_LOCATION_DEFAULT (_UART_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for UART_ROUTE */
|
||||
#define UART_ROUTE_LOCATION_LOC0 (_UART_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for UART_ROUTE */
|
||||
#define UART_ROUTE_LOCATION_LOC1 (_UART_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for UART_ROUTE */
|
||||
#define UART_ROUTE_LOCATION_LOC2 (_UART_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for UART_ROUTE */
|
||||
#define UART_ROUTE_LOCATION_LOC3 (_UART_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for UART_ROUTE */
|
||||
|
||||
/** @} End of group EFM32G_UART */
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,197 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief efm32g_vcmp Register and Bit Field definitions
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_VCMP
|
||||
* @{
|
||||
* @brief EFM32G_VCMP Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__IO uint32_t INPUTSEL; /**< Input Selection Register */
|
||||
__I uint32_t STATUS; /**< Status Register */
|
||||
__IO uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__I uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IO uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IO uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
} VCMP_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_VCMP_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/* Bit fields for VCMP CTRL */
|
||||
#define _VCMP_CTRL_RESETVALUE 0x47000000UL /**< Default value for VCMP_CTRL */
|
||||
#define _VCMP_CTRL_MASK 0x4F030715UL /**< Mask for VCMP_CTRL */
|
||||
#define VCMP_CTRL_EN (0x1UL << 0) /**< Voltage Supply Comparator Enable */
|
||||
#define _VCMP_CTRL_EN_SHIFT 0 /**< Shift value for VCMP_EN */
|
||||
#define _VCMP_CTRL_EN_MASK 0x1UL /**< Bit mask for VCMP_EN */
|
||||
#define _VCMP_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */
|
||||
#define VCMP_CTRL_EN_DEFAULT (_VCMP_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_CTRL */
|
||||
#define VCMP_CTRL_INACTVAL (0x1UL << 2) /**< Inactive Value */
|
||||
#define _VCMP_CTRL_INACTVAL_SHIFT 2 /**< Shift value for VCMP_INACTVAL */
|
||||
#define _VCMP_CTRL_INACTVAL_MASK 0x4UL /**< Bit mask for VCMP_INACTVAL */
|
||||
#define _VCMP_CTRL_INACTVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */
|
||||
#define VCMP_CTRL_INACTVAL_DEFAULT (_VCMP_CTRL_INACTVAL_DEFAULT << 2) /**< Shifted mode DEFAULT for VCMP_CTRL */
|
||||
#define VCMP_CTRL_HYSTEN (0x1UL << 4) /**< Hysteresis Enable */
|
||||
#define _VCMP_CTRL_HYSTEN_SHIFT 4 /**< Shift value for VCMP_HYSTEN */
|
||||
#define _VCMP_CTRL_HYSTEN_MASK 0x10UL /**< Bit mask for VCMP_HYSTEN */
|
||||
#define _VCMP_CTRL_HYSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */
|
||||
#define VCMP_CTRL_HYSTEN_DEFAULT (_VCMP_CTRL_HYSTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for VCMP_CTRL */
|
||||
#define _VCMP_CTRL_WARMTIME_SHIFT 8 /**< Shift value for VCMP_WARMTIME */
|
||||
#define _VCMP_CTRL_WARMTIME_MASK 0x700UL /**< Bit mask for VCMP_WARMTIME */
|
||||
#define _VCMP_CTRL_WARMTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */
|
||||
#define _VCMP_CTRL_WARMTIME_4CYCLES 0x00000000UL /**< Mode 4CYCLES for VCMP_CTRL */
|
||||
#define _VCMP_CTRL_WARMTIME_8CYCLES 0x00000001UL /**< Mode 8CYCLES for VCMP_CTRL */
|
||||
#define _VCMP_CTRL_WARMTIME_16CYCLES 0x00000002UL /**< Mode 16CYCLES for VCMP_CTRL */
|
||||
#define _VCMP_CTRL_WARMTIME_32CYCLES 0x00000003UL /**< Mode 32CYCLES for VCMP_CTRL */
|
||||
#define _VCMP_CTRL_WARMTIME_64CYCLES 0x00000004UL /**< Mode 64CYCLES for VCMP_CTRL */
|
||||
#define _VCMP_CTRL_WARMTIME_128CYCLES 0x00000005UL /**< Mode 128CYCLES for VCMP_CTRL */
|
||||
#define _VCMP_CTRL_WARMTIME_256CYCLES 0x00000006UL /**< Mode 256CYCLES for VCMP_CTRL */
|
||||
#define _VCMP_CTRL_WARMTIME_512CYCLES 0x00000007UL /**< Mode 512CYCLES for VCMP_CTRL */
|
||||
#define VCMP_CTRL_WARMTIME_DEFAULT (_VCMP_CTRL_WARMTIME_DEFAULT << 8) /**< Shifted mode DEFAULT for VCMP_CTRL */
|
||||
#define VCMP_CTRL_WARMTIME_4CYCLES (_VCMP_CTRL_WARMTIME_4CYCLES << 8) /**< Shifted mode 4CYCLES for VCMP_CTRL */
|
||||
#define VCMP_CTRL_WARMTIME_8CYCLES (_VCMP_CTRL_WARMTIME_8CYCLES << 8) /**< Shifted mode 8CYCLES for VCMP_CTRL */
|
||||
#define VCMP_CTRL_WARMTIME_16CYCLES (_VCMP_CTRL_WARMTIME_16CYCLES << 8) /**< Shifted mode 16CYCLES for VCMP_CTRL */
|
||||
#define VCMP_CTRL_WARMTIME_32CYCLES (_VCMP_CTRL_WARMTIME_32CYCLES << 8) /**< Shifted mode 32CYCLES for VCMP_CTRL */
|
||||
#define VCMP_CTRL_WARMTIME_64CYCLES (_VCMP_CTRL_WARMTIME_64CYCLES << 8) /**< Shifted mode 64CYCLES for VCMP_CTRL */
|
||||
#define VCMP_CTRL_WARMTIME_128CYCLES (_VCMP_CTRL_WARMTIME_128CYCLES << 8) /**< Shifted mode 128CYCLES for VCMP_CTRL */
|
||||
#define VCMP_CTRL_WARMTIME_256CYCLES (_VCMP_CTRL_WARMTIME_256CYCLES << 8) /**< Shifted mode 256CYCLES for VCMP_CTRL */
|
||||
#define VCMP_CTRL_WARMTIME_512CYCLES (_VCMP_CTRL_WARMTIME_512CYCLES << 8) /**< Shifted mode 512CYCLES for VCMP_CTRL */
|
||||
#define VCMP_CTRL_IRISE (0x1UL << 16) /**< Rising Edge Interrupt Sense */
|
||||
#define _VCMP_CTRL_IRISE_SHIFT 16 /**< Shift value for VCMP_IRISE */
|
||||
#define _VCMP_CTRL_IRISE_MASK 0x10000UL /**< Bit mask for VCMP_IRISE */
|
||||
#define _VCMP_CTRL_IRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */
|
||||
#define VCMP_CTRL_IRISE_DEFAULT (_VCMP_CTRL_IRISE_DEFAULT << 16) /**< Shifted mode DEFAULT for VCMP_CTRL */
|
||||
#define VCMP_CTRL_IFALL (0x1UL << 17) /**< Falling Edge Interrupt Sense */
|
||||
#define _VCMP_CTRL_IFALL_SHIFT 17 /**< Shift value for VCMP_IFALL */
|
||||
#define _VCMP_CTRL_IFALL_MASK 0x20000UL /**< Bit mask for VCMP_IFALL */
|
||||
#define _VCMP_CTRL_IFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_CTRL */
|
||||
#define VCMP_CTRL_IFALL_DEFAULT (_VCMP_CTRL_IFALL_DEFAULT << 17) /**< Shifted mode DEFAULT for VCMP_CTRL */
|
||||
#define _VCMP_CTRL_BIASPROG_SHIFT 24 /**< Shift value for VCMP_BIASPROG */
|
||||
#define _VCMP_CTRL_BIASPROG_MASK 0xF000000UL /**< Bit mask for VCMP_BIASPROG */
|
||||
#define _VCMP_CTRL_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for VCMP_CTRL */
|
||||
#define VCMP_CTRL_BIASPROG_DEFAULT (_VCMP_CTRL_BIASPROG_DEFAULT << 24) /**< Shifted mode DEFAULT for VCMP_CTRL */
|
||||
#define VCMP_CTRL_HALFBIAS (0x1UL << 30) /**< Half Bias Current */
|
||||
#define _VCMP_CTRL_HALFBIAS_SHIFT 30 /**< Shift value for VCMP_HALFBIAS */
|
||||
#define _VCMP_CTRL_HALFBIAS_MASK 0x40000000UL /**< Bit mask for VCMP_HALFBIAS */
|
||||
#define _VCMP_CTRL_HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for VCMP_CTRL */
|
||||
#define VCMP_CTRL_HALFBIAS_DEFAULT (_VCMP_CTRL_HALFBIAS_DEFAULT << 30) /**< Shifted mode DEFAULT for VCMP_CTRL */
|
||||
|
||||
/* Bit fields for VCMP INPUTSEL */
|
||||
#define _VCMP_INPUTSEL_RESETVALUE 0x00000000UL /**< Default value for VCMP_INPUTSEL */
|
||||
#define _VCMP_INPUTSEL_MASK 0x0000013FUL /**< Mask for VCMP_INPUTSEL */
|
||||
#define _VCMP_INPUTSEL_TRIGLEVEL_SHIFT 0 /**< Shift value for VCMP_TRIGLEVEL */
|
||||
#define _VCMP_INPUTSEL_TRIGLEVEL_MASK 0x3FUL /**< Bit mask for VCMP_TRIGLEVEL */
|
||||
#define _VCMP_INPUTSEL_TRIGLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_INPUTSEL */
|
||||
#define VCMP_INPUTSEL_TRIGLEVEL_DEFAULT (_VCMP_INPUTSEL_TRIGLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_INPUTSEL */
|
||||
#define VCMP_INPUTSEL_LPREF (0x1UL << 8) /**< Low Power Reference */
|
||||
#define _VCMP_INPUTSEL_LPREF_SHIFT 8 /**< Shift value for VCMP_LPREF */
|
||||
#define _VCMP_INPUTSEL_LPREF_MASK 0x100UL /**< Bit mask for VCMP_LPREF */
|
||||
#define _VCMP_INPUTSEL_LPREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_INPUTSEL */
|
||||
#define VCMP_INPUTSEL_LPREF_DEFAULT (_VCMP_INPUTSEL_LPREF_DEFAULT << 8) /**< Shifted mode DEFAULT for VCMP_INPUTSEL */
|
||||
|
||||
/* Bit fields for VCMP STATUS */
|
||||
#define _VCMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for VCMP_STATUS */
|
||||
#define _VCMP_STATUS_MASK 0x00000003UL /**< Mask for VCMP_STATUS */
|
||||
#define VCMP_STATUS_VCMPACT (0x1UL << 0) /**< Voltage Supply Comparator Active */
|
||||
#define _VCMP_STATUS_VCMPACT_SHIFT 0 /**< Shift value for VCMP_VCMPACT */
|
||||
#define _VCMP_STATUS_VCMPACT_MASK 0x1UL /**< Bit mask for VCMP_VCMPACT */
|
||||
#define _VCMP_STATUS_VCMPACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_STATUS */
|
||||
#define VCMP_STATUS_VCMPACT_DEFAULT (_VCMP_STATUS_VCMPACT_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_STATUS */
|
||||
#define VCMP_STATUS_VCMPOUT (0x1UL << 1) /**< Voltage Supply Comparator Output */
|
||||
#define _VCMP_STATUS_VCMPOUT_SHIFT 1 /**< Shift value for VCMP_VCMPOUT */
|
||||
#define _VCMP_STATUS_VCMPOUT_MASK 0x2UL /**< Bit mask for VCMP_VCMPOUT */
|
||||
#define _VCMP_STATUS_VCMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_STATUS */
|
||||
#define VCMP_STATUS_VCMPOUT_DEFAULT (_VCMP_STATUS_VCMPOUT_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_STATUS */
|
||||
|
||||
/* Bit fields for VCMP IEN */
|
||||
#define _VCMP_IEN_RESETVALUE 0x00000000UL /**< Default value for VCMP_IEN */
|
||||
#define _VCMP_IEN_MASK 0x00000003UL /**< Mask for VCMP_IEN */
|
||||
#define VCMP_IEN_EDGE (0x1UL << 0) /**< Edge Trigger Interrupt Enable */
|
||||
#define _VCMP_IEN_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */
|
||||
#define _VCMP_IEN_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */
|
||||
#define _VCMP_IEN_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IEN */
|
||||
#define VCMP_IEN_EDGE_DEFAULT (_VCMP_IEN_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_IEN */
|
||||
#define VCMP_IEN_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Enable */
|
||||
#define _VCMP_IEN_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */
|
||||
#define _VCMP_IEN_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */
|
||||
#define _VCMP_IEN_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IEN */
|
||||
#define VCMP_IEN_WARMUP_DEFAULT (_VCMP_IEN_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IEN */
|
||||
|
||||
/* Bit fields for VCMP IF */
|
||||
#define _VCMP_IF_RESETVALUE 0x00000000UL /**< Default value for VCMP_IF */
|
||||
#define _VCMP_IF_MASK 0x00000003UL /**< Mask for VCMP_IF */
|
||||
#define VCMP_IF_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag */
|
||||
#define _VCMP_IF_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */
|
||||
#define _VCMP_IF_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */
|
||||
#define _VCMP_IF_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IF */
|
||||
#define VCMP_IF_EDGE_DEFAULT (_VCMP_IF_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_IF */
|
||||
#define VCMP_IF_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag */
|
||||
#define _VCMP_IF_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */
|
||||
#define _VCMP_IF_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */
|
||||
#define _VCMP_IF_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IF */
|
||||
#define VCMP_IF_WARMUP_DEFAULT (_VCMP_IF_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IF */
|
||||
|
||||
/* Bit fields for VCMP IFS */
|
||||
#define _VCMP_IFS_RESETVALUE 0x00000000UL /**< Default value for VCMP_IFS */
|
||||
#define _VCMP_IFS_MASK 0x00000003UL /**< Mask for VCMP_IFS */
|
||||
#define VCMP_IFS_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag Set */
|
||||
#define _VCMP_IFS_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */
|
||||
#define _VCMP_IFS_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */
|
||||
#define _VCMP_IFS_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFS */
|
||||
#define VCMP_IFS_EDGE_DEFAULT (_VCMP_IFS_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_IFS */
|
||||
#define VCMP_IFS_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag Set */
|
||||
#define _VCMP_IFS_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */
|
||||
#define _VCMP_IFS_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */
|
||||
#define _VCMP_IFS_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFS */
|
||||
#define VCMP_IFS_WARMUP_DEFAULT (_VCMP_IFS_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IFS */
|
||||
|
||||
/* Bit fields for VCMP IFC */
|
||||
#define _VCMP_IFC_RESETVALUE 0x00000000UL /**< Default value for VCMP_IFC */
|
||||
#define _VCMP_IFC_MASK 0x00000003UL /**< Mask for VCMP_IFC */
|
||||
#define VCMP_IFC_EDGE (0x1UL << 0) /**< Edge Triggered Interrupt Flag Clear */
|
||||
#define _VCMP_IFC_EDGE_SHIFT 0 /**< Shift value for VCMP_EDGE */
|
||||
#define _VCMP_IFC_EDGE_MASK 0x1UL /**< Bit mask for VCMP_EDGE */
|
||||
#define _VCMP_IFC_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFC */
|
||||
#define VCMP_IFC_EDGE_DEFAULT (_VCMP_IFC_EDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for VCMP_IFC */
|
||||
#define VCMP_IFC_WARMUP (0x1UL << 1) /**< Warm-up Interrupt Flag Clear */
|
||||
#define _VCMP_IFC_WARMUP_SHIFT 1 /**< Shift value for VCMP_WARMUP */
|
||||
#define _VCMP_IFC_WARMUP_MASK 0x2UL /**< Bit mask for VCMP_WARMUP */
|
||||
#define _VCMP_IFC_WARMUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VCMP_IFC */
|
||||
#define VCMP_IFC_WARMUP_DEFAULT (_VCMP_IFC_WARMUP_DEFAULT << 1) /**< Shifted mode DEFAULT for VCMP_IFC */
|
||||
|
||||
/** @} End of group EFM32G_VCMP */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,133 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief efm32g_wdog Register and Bit Field definitions
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_WDOG
|
||||
* @{
|
||||
* @brief EFM32G_WDOG Register Declaration
|
||||
*****************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /**< Control Register */
|
||||
__IO uint32_t CMD; /**< Command Register */
|
||||
|
||||
__I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
} WDOG_TypeDef; /** @} */
|
||||
|
||||
/**************************************************************************//**
|
||||
* @defgroup EFM32G_WDOG_BitFields
|
||||
* @{
|
||||
*****************************************************************************/
|
||||
|
||||
/* Bit fields for WDOG CTRL */
|
||||
#define _WDOG_CTRL_RESETVALUE 0x00000F00UL /**< Default value for WDOG_CTRL */
|
||||
#define _WDOG_CTRL_MASK 0x00003F7FUL /**< Mask for WDOG_CTRL */
|
||||
#define WDOG_CTRL_EN (0x1UL << 0) /**< Watchdog Timer Enable */
|
||||
#define _WDOG_CTRL_EN_SHIFT 0 /**< Shift value for WDOG_EN */
|
||||
#define _WDOG_CTRL_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */
|
||||
#define _WDOG_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
|
||||
#define WDOG_CTRL_EN_DEFAULT (_WDOG_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CTRL */
|
||||
#define WDOG_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */
|
||||
#define _WDOG_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for WDOG_DEBUGRUN */
|
||||
#define _WDOG_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for WDOG_DEBUGRUN */
|
||||
#define _WDOG_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
|
||||
#define WDOG_CTRL_DEBUGRUN_DEFAULT (_WDOG_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_CTRL */
|
||||
#define WDOG_CTRL_EM2RUN (0x1UL << 2) /**< Energy Mode 2 Run Enable */
|
||||
#define _WDOG_CTRL_EM2RUN_SHIFT 2 /**< Shift value for WDOG_EM2RUN */
|
||||
#define _WDOG_CTRL_EM2RUN_MASK 0x4UL /**< Bit mask for WDOG_EM2RUN */
|
||||
#define _WDOG_CTRL_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
|
||||
#define WDOG_CTRL_EM2RUN_DEFAULT (_WDOG_CTRL_EM2RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_CTRL */
|
||||
#define WDOG_CTRL_EM3RUN (0x1UL << 3) /**< Energy Mode 3 Run Enable */
|
||||
#define _WDOG_CTRL_EM3RUN_SHIFT 3 /**< Shift value for WDOG_EM3RUN */
|
||||
#define _WDOG_CTRL_EM3RUN_MASK 0x8UL /**< Bit mask for WDOG_EM3RUN */
|
||||
#define _WDOG_CTRL_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
|
||||
#define WDOG_CTRL_EM3RUN_DEFAULT (_WDOG_CTRL_EM3RUN_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CTRL */
|
||||
#define WDOG_CTRL_LOCK (0x1UL << 4) /**< Configuration lock */
|
||||
#define _WDOG_CTRL_LOCK_SHIFT 4 /**< Shift value for WDOG_LOCK */
|
||||
#define _WDOG_CTRL_LOCK_MASK 0x10UL /**< Bit mask for WDOG_LOCK */
|
||||
#define _WDOG_CTRL_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
|
||||
#define WDOG_CTRL_LOCK_DEFAULT (_WDOG_CTRL_LOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_CTRL */
|
||||
#define WDOG_CTRL_EM4BLOCK (0x1UL << 5) /**< Energy Mode 4 Block */
|
||||
#define _WDOG_CTRL_EM4BLOCK_SHIFT 5 /**< Shift value for WDOG_EM4BLOCK */
|
||||
#define _WDOG_CTRL_EM4BLOCK_MASK 0x20UL /**< Bit mask for WDOG_EM4BLOCK */
|
||||
#define _WDOG_CTRL_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
|
||||
#define WDOG_CTRL_EM4BLOCK_DEFAULT (_WDOG_CTRL_EM4BLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for WDOG_CTRL */
|
||||
#define WDOG_CTRL_SWOSCBLOCK (0x1UL << 6) /**< Software Oscillator Disable Block */
|
||||
#define _WDOG_CTRL_SWOSCBLOCK_SHIFT 6 /**< Shift value for WDOG_SWOSCBLOCK */
|
||||
#define _WDOG_CTRL_SWOSCBLOCK_MASK 0x40UL /**< Bit mask for WDOG_SWOSCBLOCK */
|
||||
#define _WDOG_CTRL_SWOSCBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
|
||||
#define WDOG_CTRL_SWOSCBLOCK_DEFAULT (_WDOG_CTRL_SWOSCBLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for WDOG_CTRL */
|
||||
#define _WDOG_CTRL_PERSEL_SHIFT 8 /**< Shift value for WDOG_PERSEL */
|
||||
#define _WDOG_CTRL_PERSEL_MASK 0xF00UL /**< Bit mask for WDOG_PERSEL */
|
||||
#define _WDOG_CTRL_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CTRL */
|
||||
#define WDOG_CTRL_PERSEL_DEFAULT (_WDOG_CTRL_PERSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_CTRL */
|
||||
#define _WDOG_CTRL_CLKSEL_SHIFT 12 /**< Shift value for WDOG_CLKSEL */
|
||||
#define _WDOG_CTRL_CLKSEL_MASK 0x3000UL /**< Bit mask for WDOG_CLKSEL */
|
||||
#define _WDOG_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CTRL */
|
||||
#define _WDOG_CTRL_CLKSEL_ULFRCO 0x00000000UL /**< Mode ULFRCO for WDOG_CTRL */
|
||||
#define _WDOG_CTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for WDOG_CTRL */
|
||||
#define _WDOG_CTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for WDOG_CTRL */
|
||||
#define WDOG_CTRL_CLKSEL_DEFAULT (_WDOG_CTRL_CLKSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for WDOG_CTRL */
|
||||
#define WDOG_CTRL_CLKSEL_ULFRCO (_WDOG_CTRL_CLKSEL_ULFRCO << 12) /**< Shifted mode ULFRCO for WDOG_CTRL */
|
||||
#define WDOG_CTRL_CLKSEL_LFRCO (_WDOG_CTRL_CLKSEL_LFRCO << 12) /**< Shifted mode LFRCO for WDOG_CTRL */
|
||||
#define WDOG_CTRL_CLKSEL_LFXO (_WDOG_CTRL_CLKSEL_LFXO << 12) /**< Shifted mode LFXO for WDOG_CTRL */
|
||||
|
||||
/* Bit fields for WDOG CMD */
|
||||
#define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */
|
||||
#define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */
|
||||
#define WDOG_CMD_CLEAR (0x1UL << 0) /**< Watchdog Timer Clear */
|
||||
#define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */
|
||||
#define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */
|
||||
#define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */
|
||||
#define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */
|
||||
#define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */
|
||||
#define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CMD */
|
||||
#define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */
|
||||
#define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /**< Shifted mode CLEARED for WDOG_CMD */
|
||||
|
||||
/* Bit fields for WDOG SYNCBUSY */
|
||||
#define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */
|
||||
#define _WDOG_SYNCBUSY_MASK 0x00000003UL /**< Mask for WDOG_SYNCBUSY */
|
||||
#define WDOG_SYNCBUSY_CTRL (0x1UL << 0) /**< WDOG_CTRL Register Busy */
|
||||
#define _WDOG_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for WDOG_CTRL */
|
||||
#define _WDOG_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for WDOG_CTRL */
|
||||
#define _WDOG_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */
|
||||
#define WDOG_SYNCBUSY_CTRL_DEFAULT (_WDOG_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
|
||||
#define WDOG_SYNCBUSY_CMD (0x1UL << 1) /**< WDOG_CMD Register Busy */
|
||||
#define _WDOG_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for WDOG_CMD */
|
||||
#define _WDOG_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for WDOG_CMD */
|
||||
#define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */
|
||||
#define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */
|
||||
|
||||
/** @} End of group EFM32G_WDOG */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,143 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief CMSIS Cortex-M Peripheral Access Layer for Energy Micro devices
|
||||
*
|
||||
* This is a convenience header file for defining the part number on the
|
||||
* build command line, instead of specifying the part specific header file.
|
||||
* @verbatim
|
||||
* Example: Add "-DEFM32G890F128" to your build options, to define part
|
||||
* Add "#include "em_device.h" to your source files
|
||||
* @endverbatim
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __EM_DEVICE_H
|
||||
#define __EM_DEVICE_H
|
||||
|
||||
|
||||
#if defined(EFM32G200F16)
|
||||
#include "efm32g200f16.h"
|
||||
|
||||
#elif defined(EFM32G200F32)
|
||||
#include "efm32g200f32.h"
|
||||
|
||||
#elif defined(EFM32G200F64)
|
||||
#include "efm32g200f64.h"
|
||||
|
||||
#elif defined(EFM32G210F128)
|
||||
#include "efm32g210f128.h"
|
||||
|
||||
#elif defined(EFM32G222F128)
|
||||
#include "efm32g222f128.h"
|
||||
|
||||
#elif defined(EFM32G222F32)
|
||||
#include "efm32g222f32.h"
|
||||
|
||||
#elif defined(EFM32G222F64)
|
||||
#include "efm32g222f64.h"
|
||||
|
||||
#elif defined(EFM32G230F128)
|
||||
#include "efm32g230f128.h"
|
||||
|
||||
#elif defined(EFM32G230F32)
|
||||
#include "efm32g230f32.h"
|
||||
|
||||
#elif defined(EFM32G230F64)
|
||||
#include "efm32g230f64.h"
|
||||
|
||||
#elif defined(EFM32G232F128)
|
||||
#include "efm32g232f128.h"
|
||||
|
||||
#elif defined(EFM32G232F32)
|
||||
#include "efm32g232f32.h"
|
||||
|
||||
#elif defined(EFM32G232F64)
|
||||
#include "efm32g232f64.h"
|
||||
|
||||
#elif defined(EFM32G280F128)
|
||||
#include "efm32g280f128.h"
|
||||
|
||||
#elif defined(EFM32G280F32)
|
||||
#include "efm32g280f32.h"
|
||||
|
||||
#elif defined(EFM32G280F64)
|
||||
#include "efm32g280f64.h"
|
||||
|
||||
#elif defined(EFM32G290F128)
|
||||
#include "efm32g290f128.h"
|
||||
|
||||
#elif defined(EFM32G290F32)
|
||||
#include "efm32g290f32.h"
|
||||
|
||||
#elif defined(EFM32G290F64)
|
||||
#include "efm32g290f64.h"
|
||||
|
||||
#elif defined(EFM32G840F128)
|
||||
#include "efm32g840f128.h"
|
||||
|
||||
#elif defined(EFM32G840F32)
|
||||
#include "efm32g840f32.h"
|
||||
|
||||
#elif defined(EFM32G840F64)
|
||||
#include "efm32g840f64.h"
|
||||
|
||||
#elif defined(EFM32G842F128)
|
||||
#include "efm32g842f128.h"
|
||||
|
||||
#elif defined(EFM32G842F32)
|
||||
#include "efm32g842f32.h"
|
||||
|
||||
#elif defined(EFM32G842F64)
|
||||
#include "efm32g842f64.h"
|
||||
|
||||
#elif defined(EFM32G880F128)
|
||||
#include "efm32g880f128.h"
|
||||
|
||||
#elif defined(EFM32G880F32)
|
||||
#include "efm32g880f32.h"
|
||||
|
||||
#elif defined(EFM32G880F64)
|
||||
#include "efm32g880f64.h"
|
||||
|
||||
#elif defined(EFM32G890F128)
|
||||
#include "efm32g890f128.h"
|
||||
|
||||
#elif defined(EFM32G890F32)
|
||||
#include "efm32g890f32.h"
|
||||
|
||||
#elif defined(EFM32G890F64)
|
||||
#include "efm32g890f64.h"
|
||||
|
||||
|
||||
#else
|
||||
#error "em_device.h: PART NUMBER undefined"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,131 @@
|
|||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief CMSIS Cortex-M3 System Layer for EFM32G devices.
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
*******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __SYSTEM_EFM32G_H
|
||||
#define __SYSTEM_EFM32G_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*******************************************************************************
|
||||
************************** GLOBAL VARIABLES *******************************
|
||||
******************************************************************************/
|
||||
|
||||
extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */
|
||||
|
||||
/*******************************************************************************
|
||||
***************************** PROTOTYPES **********************************
|
||||
******************************************************************************/
|
||||
|
||||
/* Interrupt routines - prototypes */
|
||||
#if defined(_EFM32_GECKO_FAMILY)
|
||||
void Reset_Handler(void);
|
||||
void NMI_Handler(void);
|
||||
void HardFault_Handler(void);
|
||||
void MemManage_Handler(void);
|
||||
void BusFault_Handler(void);
|
||||
void UsageFault_Handler(void);
|
||||
void SVC_Handler(void);
|
||||
void DebugMon_Handler(void);
|
||||
void PendSV_Handler(void);
|
||||
void SysTick_Handler(void);
|
||||
void DMA_IRQHandler(void);
|
||||
void GPIO_EVEN_IRQHandler(void);
|
||||
void TIMER0_IRQHandler(void);
|
||||
void USART0_RX_IRQHandler(void);
|
||||
void USART0_TX_IRQHandler(void);
|
||||
void ACMP0_IRQHandler(void);
|
||||
void ADC0_IRQHandler(void);
|
||||
void DAC0_IRQHandler(void);
|
||||
void I2C0_IRQHandler(void);
|
||||
void GPIO_ODD_IRQHandler(void);
|
||||
void TIMER1_IRQHandler(void);
|
||||
void TIMER2_IRQHandler(void);
|
||||
void USART1_RX_IRQHandler(void);
|
||||
void USART1_TX_IRQHandler(void);
|
||||
void USART2_RX_IRQHandler(void);
|
||||
void USART2_TX_IRQHandler(void);
|
||||
void UART0_RX_IRQHandler(void);
|
||||
void UART0_TX_IRQHandler(void);
|
||||
void LEUART0_IRQHandler(void);
|
||||
void LEUART1_IRQHandler(void);
|
||||
void LETIMER0_IRQHandler(void);
|
||||
void PCNT0_IRQHandler(void);
|
||||
void PCNT1_IRQHandler(void);
|
||||
void PCNT2_IRQHandler(void);
|
||||
void RTC_IRQHandler(void);
|
||||
void CMU_IRQHandler(void);
|
||||
void VCMP_IRQHandler(void);
|
||||
void LCD_IRQHandler(void);
|
||||
void MSC_IRQHandler(void);
|
||||
void AES_IRQHandler(void);
|
||||
#endif
|
||||
|
||||
uint32_t SystemCoreClockGet(void);
|
||||
|
||||
/**************************************************************************//**
|
||||
* @brief
|
||||
* Update CMSIS SystemCoreClock variable.
|
||||
*
|
||||
* @details
|
||||
* CMSIS defines a global variable SystemCoreClock that shall hold the
|
||||
* core frequency in Hz. If the core frequency is dynamically changed, the
|
||||
* variable must be kept updated in order to be CMSIS compliant.
|
||||
*
|
||||
* Notice that if only changing core clock frequency through the EFM32 CMU
|
||||
* API, this variable will be kept updated. This function is only provided
|
||||
* for CMSIS compliance and if a user modifies the the core clock outside
|
||||
* the CMU API.
|
||||
*****************************************************************************/
|
||||
static __INLINE void SystemCoreClockUpdate(void)
|
||||
{
|
||||
SystemCoreClockGet();
|
||||
}
|
||||
|
||||
void SystemInit(void);
|
||||
uint32_t SystemHFClockGet(void);
|
||||
uint32_t SystemHFXOClockGet(void);
|
||||
void SystemHFXOClockSet(uint32_t freq);
|
||||
uint32_t SystemLFRCOClockGet(void);
|
||||
uint32_t SystemULFRCOClockGet(void);
|
||||
uint32_t SystemLFXOClockGet(void);
|
||||
void SystemLFXOClockSet(uint32_t freq);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_EFM32G_H */
|
||||
|
|
@ -0,0 +1,271 @@
|
|||
;/**************************************************************************//**
|
||||
; * @file
|
||||
; * @brief CMSIS Core Device Startup File for
|
||||
; * Energy Micro EFM32G Device Series
|
||||
; * @version 3.20.0
|
||||
; * @date 03. February 2012
|
||||
; *
|
||||
; * @note
|
||||
; * Copyright (C) 2012 ARM Limited. All rights reserved.
|
||||
; *
|
||||
; * @par
|
||||
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
; * processor based microcontrollers. This file can be freely distributed
|
||||
; * within development tools that are supporting such ARM based processors.
|
||||
; *
|
||||
; * @par
|
||||
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
;/*
|
||||
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
;*/
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000C00
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY, ALIGN=8
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
|
||||
DCD DMA_IRQHandler ; 0: DMA Interrupt
|
||||
DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt
|
||||
DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt
|
||||
DCD USART0_RX_IRQHandler ; 3: USART0_RX Interrupt
|
||||
DCD USART0_TX_IRQHandler ; 4: USART0_TX Interrupt
|
||||
DCD ACMP0_IRQHandler ; 5: ACMP0 Interrupt
|
||||
DCD ADC0_IRQHandler ; 6: ADC0 Interrupt
|
||||
DCD DAC0_IRQHandler ; 7: DAC0 Interrupt
|
||||
DCD I2C0_IRQHandler ; 8: I2C0 Interrupt
|
||||
DCD GPIO_ODD_IRQHandler ; 9: GPIO_ODD Interrupt
|
||||
DCD TIMER1_IRQHandler ; 10: TIMER1 Interrupt
|
||||
DCD TIMER2_IRQHandler ; 11: TIMER2 Interrupt
|
||||
DCD USART1_RX_IRQHandler ; 12: USART1_RX Interrupt
|
||||
DCD USART1_TX_IRQHandler ; 13: USART1_TX Interrupt
|
||||
DCD USART2_RX_IRQHandler ; 14: USART2_RX Interrupt
|
||||
DCD USART2_TX_IRQHandler ; 15: USART2_TX Interrupt
|
||||
DCD UART0_RX_IRQHandler ; 16: UART0_RX Interrupt
|
||||
DCD UART0_TX_IRQHandler ; 17: UART0_TX Interrupt
|
||||
DCD LEUART0_IRQHandler ; 18: LEUART0 Interrupt
|
||||
DCD LEUART1_IRQHandler ; 19: LEUART1 Interrupt
|
||||
DCD LETIMER0_IRQHandler ; 20: LETIMER0 Interrupt
|
||||
DCD PCNT0_IRQHandler ; 21: PCNT0 Interrupt
|
||||
DCD PCNT1_IRQHandler ; 22: PCNT1 Interrupt
|
||||
DCD PCNT2_IRQHandler ; 23: PCNT2 Interrupt
|
||||
DCD RTC_IRQHandler ; 24: RTC Interrupt
|
||||
DCD CMU_IRQHandler ; 25: CMU Interrupt
|
||||
DCD VCMP_IRQHandler ; 26: VCMP Interrupt
|
||||
DCD LCD_IRQHandler ; 27: LCD Interrupt
|
||||
DCD MSC_IRQHandler ; 28: MSC Interrupt
|
||||
DCD AES_IRQHandler ; 29: AES Interrupt
|
||||
|
||||
__Vectors_End
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT DMA_IRQHandler [WEAK]
|
||||
EXPORT GPIO_EVEN_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_IRQHandler [WEAK]
|
||||
EXPORT USART0_RX_IRQHandler [WEAK]
|
||||
EXPORT USART0_TX_IRQHandler [WEAK]
|
||||
EXPORT ACMP0_IRQHandler [WEAK]
|
||||
EXPORT ADC0_IRQHandler [WEAK]
|
||||
EXPORT DAC0_IRQHandler [WEAK]
|
||||
EXPORT I2C0_IRQHandler [WEAK]
|
||||
EXPORT GPIO_ODD_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT USART1_RX_IRQHandler [WEAK]
|
||||
EXPORT USART1_TX_IRQHandler [WEAK]
|
||||
EXPORT USART2_RX_IRQHandler [WEAK]
|
||||
EXPORT USART2_TX_IRQHandler [WEAK]
|
||||
EXPORT UART0_RX_IRQHandler [WEAK]
|
||||
EXPORT UART0_TX_IRQHandler [WEAK]
|
||||
EXPORT LEUART0_IRQHandler [WEAK]
|
||||
EXPORT LEUART1_IRQHandler [WEAK]
|
||||
EXPORT LETIMER0_IRQHandler [WEAK]
|
||||
EXPORT PCNT0_IRQHandler [WEAK]
|
||||
EXPORT PCNT1_IRQHandler [WEAK]
|
||||
EXPORT PCNT2_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT CMU_IRQHandler [WEAK]
|
||||
EXPORT VCMP_IRQHandler [WEAK]
|
||||
EXPORT LCD_IRQHandler [WEAK]
|
||||
EXPORT MSC_IRQHandler [WEAK]
|
||||
EXPORT AES_IRQHandler [WEAK]
|
||||
|
||||
|
||||
DMA_IRQHandler
|
||||
GPIO_EVEN_IRQHandler
|
||||
TIMER0_IRQHandler
|
||||
USART0_RX_IRQHandler
|
||||
USART0_TX_IRQHandler
|
||||
ACMP0_IRQHandler
|
||||
ADC0_IRQHandler
|
||||
DAC0_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
GPIO_ODD_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
USART1_RX_IRQHandler
|
||||
USART1_TX_IRQHandler
|
||||
USART2_RX_IRQHandler
|
||||
USART2_TX_IRQHandler
|
||||
UART0_RX_IRQHandler
|
||||
UART0_TX_IRQHandler
|
||||
LEUART0_IRQHandler
|
||||
LEUART1_IRQHandler
|
||||
LETIMER0_IRQHandler
|
||||
PCNT0_IRQHandler
|
||||
PCNT1_IRQHandler
|
||||
PCNT2_IRQHandler
|
||||
RTC_IRQHandler
|
||||
CMU_IRQHandler
|
||||
VCMP_IRQHandler
|
||||
LCD_IRQHandler
|
||||
MSC_IRQHandler
|
||||
AES_IRQHandler
|
||||
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
|
@ -0,0 +1,260 @@
|
|||
/**************************************************************************//**
|
||||
* File : startup_efm32x.s
|
||||
*
|
||||
* Abstract : This file contains interrupt vector and startup code.
|
||||
*
|
||||
* Functions : Reset_Handler
|
||||
*
|
||||
* Target : Energy Micro EFM32 EFM32G microcontrollers
|
||||
*
|
||||
* Environment : Atollic TrueSTUDIO(R)
|
||||
*
|
||||
* Distribution: The file is distributed "as is," without any warranty
|
||||
* of any kind.
|
||||
*
|
||||
* (c)Copyright Atollic AB.
|
||||
* You may use this file as-is or modify it according to the needs of your
|
||||
* project. This file may only be built (assembled or compiled and linked)
|
||||
* using the Atollic TrueSTUDIO(R) product. The use of this file together
|
||||
* with other tools than Atollic TrueSTUDIO(R) is not permitted.
|
||||
*
|
||||
*******************************************************************************
|
||||
* Energy Micro release version
|
||||
* @version 3.20.0
|
||||
******************************************************************************/
|
||||
|
||||
.syntax unified
|
||||
.thumb
|
||||
|
||||
.global Reset_Handler
|
||||
.global InterruptVector
|
||||
.global Default_Handler
|
||||
|
||||
/* Linker script definitions */
|
||||
/* start address for the initialization values of the .data section */
|
||||
.word _sidata
|
||||
/* start address for the .data section */
|
||||
.word _sdata
|
||||
/* end address for the .data section */
|
||||
.word _edata
|
||||
/* start address for the .bss section */
|
||||
.word _sbss
|
||||
/* end address for the .bss section */
|
||||
.word _ebss
|
||||
|
||||
/**
|
||||
**===========================================================================
|
||||
** Program - Reset_Handler
|
||||
** Abstract: This code gets called after reset.
|
||||
**===========================================================================
|
||||
*/
|
||||
.section .text.Reset_Handler,"ax", %progbits
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
/* Set stack pointer */
|
||||
ldr sp,=_estack
|
||||
|
||||
/* Branch to SystemInit function */
|
||||
bl SystemInit
|
||||
|
||||
/* Copy data initialization values */
|
||||
ldr r1,=_sidata
|
||||
ldr r2,=_sdata
|
||||
ldr r3,=_edata
|
||||
b cmpdata
|
||||
CopyLoop:
|
||||
ldr r0, [r1], #4
|
||||
str r0, [r2], #4
|
||||
cmpdata:
|
||||
cmp r2, r3
|
||||
blt CopyLoop
|
||||
|
||||
/* Clear BSS section */
|
||||
movs r0, #0
|
||||
ldr r2,=_sbss
|
||||
ldr r3,=_ebss
|
||||
b cmpbss
|
||||
ClearLoop:
|
||||
str r0, [r2], #4
|
||||
cmpbss:
|
||||
cmp r2, r3
|
||||
blt ClearLoop
|
||||
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
|
||||
/* Branch to main */
|
||||
bl main
|
||||
|
||||
/* If main returns, branch to Default_Handler. */
|
||||
b Default_Handler
|
||||
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
**===========================================================================
|
||||
** Program - Default_Handler
|
||||
** Abstract: This code gets called when the processor receives an
|
||||
** unexpected interrupt.
|
||||
**===========================================================================
|
||||
*/
|
||||
.section .text.Default_Handler,"ax", %progbits
|
||||
Default_Handler:
|
||||
b Default_Handler
|
||||
|
||||
.size Default_Handler, .-Default_Handler
|
||||
|
||||
/**
|
||||
**===========================================================================
|
||||
** Interrupt vector table
|
||||
**===========================================================================
|
||||
*/
|
||||
.section .isr_vector,"a", %progbits
|
||||
InterruptVector:
|
||||
.word _estack /* 0 - Stack pointer */
|
||||
.word Reset_Handler /* 1 - Reset */
|
||||
.word NMI_Handler /* 2 - NMI */
|
||||
.word HardFault_Handler /* 3 - Hard fault */
|
||||
.word MemManage_Handler /* 4 - Memory management fault */
|
||||
.word BusFault_Handler /* 5 - Bus fault */
|
||||
.word UsageFault_Handler /* 6 - Usage fault */
|
||||
.word 0 /* 7 - Reserved */
|
||||
.word 0 /* 8 - Reserved */
|
||||
.word 0 /* 9 - Reserved */
|
||||
.word 0 /* 10 - Reserved */
|
||||
.word SVC_Handler /* 11 - SVCall */
|
||||
.word DebugMonitor_Handler /* 12 - Reservered for Debug */
|
||||
.word 0 /* 13 - Reserved */
|
||||
.word PendSV_Handler /* 14 - PendSV */
|
||||
.word SysTick_Handler /* 15 - Systick */
|
||||
|
||||
/* External Interrupts */
|
||||
.word DMA_IRQHandler
|
||||
.word GPIO_EVEN_IRQHandler
|
||||
.word TIMER0_IRQHandler
|
||||
.word USART0_RX_IRQHandler
|
||||
.word USART0_TX_IRQHandler
|
||||
.word ACMP0_IRQHandler
|
||||
.word ADC0_IRQHandler
|
||||
.word DAC0_IRQHandler
|
||||
.word I2C0_IRQHandler
|
||||
.word GPIO_ODD_IRQHandler
|
||||
.word TIMER1_IRQHandler
|
||||
.word TIMER2_IRQHandler
|
||||
.word USART1_RX_IRQHandler
|
||||
.word USART1_TX_IRQHandler
|
||||
.word USART2_RX_IRQHandler
|
||||
.word USART2_TX_IRQHandler
|
||||
.word UART0_RX_IRQHandler
|
||||
.word UART0_TX_IRQHandler
|
||||
.word LEUART0_IRQHandler
|
||||
.word LEUART1_IRQHandler
|
||||
.word LETIMER0_IRQHandler
|
||||
.word PCNT0_IRQHandler
|
||||
.word PCNT1_IRQHandler
|
||||
.word PCNT2_IRQHandler
|
||||
.word RTC_IRQHandler
|
||||
.word CMU_IRQHandler
|
||||
.word VCMP_IRQHandler
|
||||
.word LCD_IRQHandler
|
||||
.word MSC_IRQHandler
|
||||
.word AES_IRQHandler
|
||||
|
||||
|
||||
|
||||
/**
|
||||
**===========================================================================
|
||||
** Weak interrupt handlers redirected to Default_Handler. These can be
|
||||
** overridden in user code.
|
||||
**===========================================================================
|
||||
*/
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler, Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler, Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler, Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler, Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler, Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler, Default_Handler
|
||||
|
||||
.weak DebugMonitor_Handler
|
||||
.thumb_set DebugMonitor_Handler, Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler, Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler, Default_Handler
|
||||
|
||||
.weak DMA_IRQHandler
|
||||
.thumb_set DMA_IRQHandler, Default_Handler
|
||||
.weak GPIO_EVEN_IRQHandler
|
||||
.thumb_set GPIO_EVEN_IRQHandler, Default_Handler
|
||||
.weak TIMER0_IRQHandler
|
||||
.thumb_set TIMER0_IRQHandler, Default_Handler
|
||||
.weak USART0_RX_IRQHandler
|
||||
.thumb_set USART0_RX_IRQHandler, Default_Handler
|
||||
.weak USART0_TX_IRQHandler
|
||||
.thumb_set USART0_TX_IRQHandler, Default_Handler
|
||||
.weak ACMP0_IRQHandler
|
||||
.thumb_set ACMP0_IRQHandler, Default_Handler
|
||||
.weak ADC0_IRQHandler
|
||||
.thumb_set ADC0_IRQHandler, Default_Handler
|
||||
.weak DAC0_IRQHandler
|
||||
.thumb_set DAC0_IRQHandler, Default_Handler
|
||||
.weak I2C0_IRQHandler
|
||||
.thumb_set I2C0_IRQHandler, Default_Handler
|
||||
.weak GPIO_ODD_IRQHandler
|
||||
.thumb_set GPIO_ODD_IRQHandler, Default_Handler
|
||||
.weak TIMER1_IRQHandler
|
||||
.thumb_set TIMER1_IRQHandler, Default_Handler
|
||||
.weak TIMER2_IRQHandler
|
||||
.thumb_set TIMER2_IRQHandler, Default_Handler
|
||||
.weak USART1_RX_IRQHandler
|
||||
.thumb_set USART1_RX_IRQHandler, Default_Handler
|
||||
.weak USART1_TX_IRQHandler
|
||||
.thumb_set USART1_TX_IRQHandler, Default_Handler
|
||||
.weak USART2_RX_IRQHandler
|
||||
.thumb_set USART2_RX_IRQHandler, Default_Handler
|
||||
.weak USART2_TX_IRQHandler
|
||||
.thumb_set USART2_TX_IRQHandler, Default_Handler
|
||||
.weak UART0_RX_IRQHandler
|
||||
.thumb_set UART0_RX_IRQHandler, Default_Handler
|
||||
.weak UART0_TX_IRQHandler
|
||||
.thumb_set UART0_TX_IRQHandler, Default_Handler
|
||||
.weak LEUART0_IRQHandler
|
||||
.thumb_set LEUART0_IRQHandler, Default_Handler
|
||||
.weak LEUART1_IRQHandler
|
||||
.thumb_set LEUART1_IRQHandler, Default_Handler
|
||||
.weak LETIMER0_IRQHandler
|
||||
.thumb_set LETIMER0_IRQHandler, Default_Handler
|
||||
.weak PCNT0_IRQHandler
|
||||
.thumb_set PCNT0_IRQHandler, Default_Handler
|
||||
.weak PCNT1_IRQHandler
|
||||
.thumb_set PCNT1_IRQHandler, Default_Handler
|
||||
.weak PCNT2_IRQHandler
|
||||
.thumb_set PCNT2_IRQHandler, Default_Handler
|
||||
.weak RTC_IRQHandler
|
||||
.thumb_set RTC_IRQHandler, Default_Handler
|
||||
.weak CMU_IRQHandler
|
||||
.thumb_set CMU_IRQHandler, Default_Handler
|
||||
.weak VCMP_IRQHandler
|
||||
.thumb_set VCMP_IRQHandler, Default_Handler
|
||||
.weak LCD_IRQHandler
|
||||
.thumb_set LCD_IRQHandler, Default_Handler
|
||||
.weak MSC_IRQHandler
|
||||
.thumb_set MSC_IRQHandler, Default_Handler
|
||||
.weak AES_IRQHandler
|
||||
.thumb_set AES_IRQHandler, Default_Handler
|
||||
|
||||
|
||||
.end
|
||||
|
|
@ -0,0 +1,245 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief CMSIS Core Device Startup File for
|
||||
* Energy Micro EFM32G Device Series
|
||||
******************************************************************************
|
||||
*
|
||||
* Version: Sourcery G++ 4.4-180
|
||||
* Support: https://support.codesourcery.com/GNUToolchain/
|
||||
*
|
||||
* Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.
|
||||
*
|
||||
* The authors hereby grant permission to use, copy, modify, distribute,
|
||||
* and license this software and its documentation for any purpose, provided
|
||||
* that existing copyright notices are retained in all copies and that this
|
||||
* notice is included verbatim in any distributions. No written agreement,
|
||||
* license, or royalty fee is required for any of the authorized uses.
|
||||
* Modifications to this software may be copyrighted by their authors
|
||||
* and need not follow the licensing terms described here, provided that
|
||||
* the new terms are clearly indicated on the first page of each file where
|
||||
* they apply.
|
||||
*
|
||||
*******************************************************************************
|
||||
* Energy Micro release version
|
||||
* @version 3.20.0
|
||||
******************************************************************************/
|
||||
|
||||
/* Vector Table */
|
||||
|
||||
.section ".cs3.interrupt_vector"
|
||||
.globl __cs3_interrupt_vector_em
|
||||
.type __cs3_interrupt_vector_em, %object
|
||||
|
||||
__cs3_interrupt_vector_em:
|
||||
.long __cs3_stack /* Top of Stack */
|
||||
.long __cs3_reset /* Reset Handler */
|
||||
.long NMI_Handler /* NMI Handler */
|
||||
.long HardFault_Handler /* Hard Fault Handler */
|
||||
.long MemManage_Handler /* MPU Fault Handler */
|
||||
.long BusFault_Handler /* Bus Fault Handler */
|
||||
.long UsageFault_Handler /* Usage Fault Handler */
|
||||
.long Reserved7_Handler /* Reserved */
|
||||
.long Reserved8_Handler /* Reserved */
|
||||
.long Reserved9_Handler /* Reserved */
|
||||
.long Reserved10_Handler /* Reserved */
|
||||
.long SVC_Handler /* SVCall Handler */
|
||||
.long DebugMon_Handler /* Debug Monitor Handler */
|
||||
.long Reserved13_Handler /* Reserved */
|
||||
.long PendSV_Handler /* PendSV Handler */
|
||||
.long SysTick_Handler /* SysTick Handler */
|
||||
|
||||
/* External Interrupts */
|
||||
.long DMA_IRQHandler
|
||||
.long GPIO_EVEN_IRQHandler
|
||||
.long TIMER0_IRQHandler
|
||||
.long USART0_RX_IRQHandler
|
||||
.long USART0_TX_IRQHandler
|
||||
.long ACMP0_IRQHandler
|
||||
.long ADC0_IRQHandler
|
||||
.long DAC0_IRQHandler
|
||||
.long I2C0_IRQHandler
|
||||
.long GPIO_ODD_IRQHandler
|
||||
.long TIMER1_IRQHandler
|
||||
.long TIMER2_IRQHandler
|
||||
.long USART1_RX_IRQHandler
|
||||
.long USART1_TX_IRQHandler
|
||||
.long USART2_RX_IRQHandler
|
||||
.long USART2_TX_IRQHandler
|
||||
.long UART0_RX_IRQHandler
|
||||
.long UART0_TX_IRQHandler
|
||||
.long LEUART0_IRQHandler
|
||||
.long LEUART1_IRQHandler
|
||||
.long LETIMER0_IRQHandler
|
||||
.long PCNT0_IRQHandler
|
||||
.long PCNT1_IRQHandler
|
||||
.long PCNT2_IRQHandler
|
||||
.long RTC_IRQHandler
|
||||
.long CMU_IRQHandler
|
||||
.long VCMP_IRQHandler
|
||||
.long LCD_IRQHandler
|
||||
.long MSC_IRQHandler
|
||||
.long AES_IRQHandler
|
||||
|
||||
.size __cs3_interrupt_vector_em, . - __cs3_interrupt_vector_em
|
||||
|
||||
.thumb
|
||||
|
||||
|
||||
/* Reset Handler */
|
||||
|
||||
.section .cs3.reset,"x",%progbits
|
||||
.thumb_func
|
||||
.globl __cs3_reset_em
|
||||
.type __cs3_reset_em, %function
|
||||
__cs3_reset_em:
|
||||
/* jump to common start code */
|
||||
ldr r0, =SystemInit
|
||||
blx r0
|
||||
ldr r0,=__cs3_start_asm
|
||||
bx r0
|
||||
.pool
|
||||
.size __cs3_reset_em,.-__cs3_reset_em
|
||||
.thumb
|
||||
|
||||
.globl _IRQHandlerinterrupt
|
||||
.type _IRQHandlerinterrupt, %function
|
||||
_IRQHandlerinterrupt:
|
||||
b .
|
||||
.size _IRQHandlerinterrupt, . - _IRQHandlerinterrupt
|
||||
|
||||
.weak NMI_Handler
|
||||
.globl NMI_Handler
|
||||
.set NMI_Handler, _IRQHandlerinterrupt
|
||||
.weak HardFault_Handler
|
||||
.globl HardFault_Handler
|
||||
.set HardFault_Handler, _IRQHandlerinterrupt
|
||||
.weak MemManage_Handler
|
||||
.globl MemManage_Handler
|
||||
.set MemManage_Handler, _IRQHandlerinterrupt
|
||||
.weak BusFault_Handler
|
||||
.globl BusFault_Handler
|
||||
.set BusFault_Handler, _IRQHandlerinterrupt
|
||||
.weak UsageFault_Handler
|
||||
.globl UsageFault_Handler
|
||||
.set UsageFault_Handler, _IRQHandlerinterrupt
|
||||
.weak Reserved7_Handler
|
||||
.globl Reserved7_Handler
|
||||
.set Reserved7_Handler, _IRQHandlerinterrupt
|
||||
.weak Reserved8_Handler
|
||||
.globl Reserved8_Handler
|
||||
.set Reserved8_Handler, _IRQHandlerinterrupt
|
||||
.weak Reserved9_Handler
|
||||
.globl Reserved9_Handler
|
||||
.set Reserved9_Handler, _IRQHandlerinterrupt
|
||||
.weak Reserved10_Handler
|
||||
.globl Reserved10_Handler
|
||||
.set Reserved10_Handler, _IRQHandlerinterrupt
|
||||
.weak SVC_Handler
|
||||
.globl SVC_Handler
|
||||
.set SVC_Handler, _IRQHandlerinterrupt
|
||||
.weak DebugMon_Handler
|
||||
.globl DebugMon_Handler
|
||||
.set DebugMon_Handler, _IRQHandlerinterrupt
|
||||
.weak Reserved13_Handler
|
||||
.globl Reserved13_Handler
|
||||
.set Reserved13_Handler, _IRQHandlerinterrupt
|
||||
.weak PendSV_Handler
|
||||
.globl PendSV_Handler
|
||||
.set PendSV_Handler, _IRQHandlerinterrupt
|
||||
.weak SysTick_Handler
|
||||
.globl SysTick_Handler
|
||||
.set SysTick_Handler, _IRQHandlerinterrupt
|
||||
|
||||
.weak DMA_IRQHandler
|
||||
.globl DMA_IRQHandler
|
||||
.set DMA_IRQHandler, _IRQHandlerinterrupt
|
||||
.weak GPIO_EVEN_IRQHandler
|
||||
.globl GPIO_EVEN_IRQHandler
|
||||
.set GPIO_EVEN_IRQHandler, _IRQHandlerinterrupt
|
||||
.weak TIMER0_IRQHandler
|
||||
.globl TIMER0_IRQHandler
|
||||
.set TIMER0_IRQHandler, _IRQHandlerinterrupt
|
||||
.weak USART0_RX_IRQHandler
|
||||
.globl USART0_RX_IRQHandler
|
||||
.set USART0_RX_IRQHandler, _IRQHandlerinterrupt
|
||||
.weak USART0_TX_IRQHandler
|
||||
.globl USART0_TX_IRQHandler
|
||||
.set USART0_TX_IRQHandler, _IRQHandlerinterrupt
|
||||
.weak ACMP0_IRQHandler
|
||||
.globl ACMP0_IRQHandler
|
||||
.set ACMP0_IRQHandler, _IRQHandlerinterrupt
|
||||
.weak ADC0_IRQHandler
|
||||
.globl ADC0_IRQHandler
|
||||
.set ADC0_IRQHandler, _IRQHandlerinterrupt
|
||||
.weak DAC0_IRQHandler
|
||||
.globl DAC0_IRQHandler
|
||||
.set DAC0_IRQHandler, _IRQHandlerinterrupt
|
||||
.weak I2C0_IRQHandler
|
||||
.globl I2C0_IRQHandler
|
||||
.set I2C0_IRQHandler, _IRQHandlerinterrupt
|
||||
.weak GPIO_ODD_IRQHandler
|
||||
.globl GPIO_ODD_IRQHandler
|
||||
.set GPIO_ODD_IRQHandler, _IRQHandlerinterrupt
|
||||
.weak TIMER1_IRQHandler
|
||||
.globl TIMER1_IRQHandler
|
||||
.set TIMER1_IRQHandler, _IRQHandlerinterrupt
|
||||
.weak TIMER2_IRQHandler
|
||||
.globl TIMER2_IRQHandler
|
||||
.set TIMER2_IRQHandler, _IRQHandlerinterrupt
|
||||
.weak USART1_RX_IRQHandler
|
||||
.globl USART1_RX_IRQHandler
|
||||
.set USART1_RX_IRQHandler, _IRQHandlerinterrupt
|
||||
.weak USART1_TX_IRQHandler
|
||||
.globl USART1_TX_IRQHandler
|
||||
.set USART1_TX_IRQHandler, _IRQHandlerinterrupt
|
||||
.weak USART2_RX_IRQHandler
|
||||
.globl USART2_RX_IRQHandler
|
||||
.set USART2_RX_IRQHandler, _IRQHandlerinterrupt
|
||||
.weak USART2_TX_IRQHandler
|
||||
.globl USART2_TX_IRQHandler
|
||||
.set USART2_TX_IRQHandler, _IRQHandlerinterrupt
|
||||
.weak UART0_RX_IRQHandler
|
||||
.globl UART0_RX_IRQHandler
|
||||
.set UART0_RX_IRQHandler, _IRQHandlerinterrupt
|
||||
.weak UART0_TX_IRQHandler
|
||||
.globl UART0_TX_IRQHandler
|
||||
.set UART0_TX_IRQHandler, _IRQHandlerinterrupt
|
||||
.weak LEUART0_IRQHandler
|
||||
.globl LEUART0_IRQHandler
|
||||
.set LEUART0_IRQHandler, _IRQHandlerinterrupt
|
||||
.weak LEUART1_IRQHandler
|
||||
.globl LEUART1_IRQHandler
|
||||
.set LEUART1_IRQHandler, _IRQHandlerinterrupt
|
||||
.weak LETIMER0_IRQHandler
|
||||
.globl LETIMER0_IRQHandler
|
||||
.set LETIMER0_IRQHandler, _IRQHandlerinterrupt
|
||||
.weak PCNT0_IRQHandler
|
||||
.globl PCNT0_IRQHandler
|
||||
.set PCNT0_IRQHandler, _IRQHandlerinterrupt
|
||||
.weak PCNT1_IRQHandler
|
||||
.globl PCNT1_IRQHandler
|
||||
.set PCNT1_IRQHandler, _IRQHandlerinterrupt
|
||||
.weak PCNT2_IRQHandler
|
||||
.globl PCNT2_IRQHandler
|
||||
.set PCNT2_IRQHandler, _IRQHandlerinterrupt
|
||||
.weak RTC_IRQHandler
|
||||
.globl RTC_IRQHandler
|
||||
.set RTC_IRQHandler, _IRQHandlerinterrupt
|
||||
.weak CMU_IRQHandler
|
||||
.globl CMU_IRQHandler
|
||||
.set CMU_IRQHandler, _IRQHandlerinterrupt
|
||||
.weak VCMP_IRQHandler
|
||||
.globl VCMP_IRQHandler
|
||||
.set VCMP_IRQHandler, _IRQHandlerinterrupt
|
||||
.weak LCD_IRQHandler
|
||||
.globl LCD_IRQHandler
|
||||
.set LCD_IRQHandler, _IRQHandlerinterrupt
|
||||
.weak MSC_IRQHandler
|
||||
.globl MSC_IRQHandler
|
||||
.set MSC_IRQHandler, _IRQHandlerinterrupt
|
||||
.weak AES_IRQHandler
|
||||
.globl AES_IRQHandler
|
||||
.set AES_IRQHandler, _IRQHandlerinterrupt
|
||||
|
||||
|
||||
.end
|
||||
|
|
@ -0,0 +1,227 @@
|
|||
/* @file
|
||||
* @brief startup file for Energy Micro EFM32G devices.
|
||||
* For use with GCC for ARM Embedded Processors
|
||||
* @version 3.20.0
|
||||
* Date: 08 Feb 2012
|
||||
*
|
||||
* Copyright (c) 2012, ARM Limited
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
* Neither the name of the ARM Limited nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
.syntax unified
|
||||
.arch armv7-m
|
||||
|
||||
.section .stack
|
||||
.align 3
|
||||
#ifdef __STACK_SIZE
|
||||
.equ Stack_Size, __STACK_SIZE
|
||||
#else
|
||||
.equ Stack_Size, 0x400
|
||||
#endif
|
||||
.globl __StackTop
|
||||
.globl __StackLimit
|
||||
__StackLimit:
|
||||
.space Stack_Size
|
||||
.size __StackLimit, . - __StackLimit
|
||||
__StackTop:
|
||||
.size __StackTop, . - __StackTop
|
||||
|
||||
.section .heap
|
||||
.align 3
|
||||
#ifdef __HEAP_SIZE
|
||||
.equ Heap_Size, __HEAP_SIZE
|
||||
#else
|
||||
.equ Heap_Size, 0xC00
|
||||
#endif
|
||||
.globl __HeapBase
|
||||
.globl __HeapLimit
|
||||
__HeapBase:
|
||||
.if Heap_Size
|
||||
.space Heap_Size
|
||||
.endif
|
||||
.size __HeapBase, . - __HeapBase
|
||||
__HeapLimit:
|
||||
.size __HeapLimit, . - __HeapLimit
|
||||
|
||||
.section .isr_vector
|
||||
.align 8
|
||||
.globl __isr_vector
|
||||
__isr_vector:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler /* Reset Handler */
|
||||
.long NMI_Handler /* NMI Handler */
|
||||
.long HardFault_Handler /* Hard Fault Handler */
|
||||
.long MemManage_Handler /* MPU Fault Handler */
|
||||
.long BusFault_Handler /* Bus Fault Handler */
|
||||
.long UsageFault_Handler /* Usage Fault Handler */
|
||||
.long Default_Handler /* Reserved */
|
||||
.long Default_Handler /* Reserved */
|
||||
.long Default_Handler /* Reserved */
|
||||
.long Default_Handler /* Reserved */
|
||||
.long SVC_Handler /* SVCall Handler */
|
||||
.long DebugMon_Handler /* Debug Monitor Handler */
|
||||
.long Default_Handler /* Reserved */
|
||||
.long PendSV_Handler /* PendSV Handler */
|
||||
.long SysTick_Handler /* SysTick Handler */
|
||||
|
||||
/* External interrupts */
|
||||
.long DMA_IRQHandler /* 0 - DMA */
|
||||
.long GPIO_EVEN_IRQHandler /* 1 - GPIO_EVEN */
|
||||
.long TIMER0_IRQHandler /* 2 - TIMER0 */
|
||||
.long USART0_RX_IRQHandler /* 3 - USART0_RX */
|
||||
.long USART0_TX_IRQHandler /* 4 - USART0_TX */
|
||||
.long ACMP0_IRQHandler /* 5 - ACMP0 */
|
||||
.long ADC0_IRQHandler /* 6 - ADC0 */
|
||||
.long DAC0_IRQHandler /* 7 - DAC0 */
|
||||
.long I2C0_IRQHandler /* 8 - I2C0 */
|
||||
.long GPIO_ODD_IRQHandler /* 9 - GPIO_ODD */
|
||||
.long TIMER1_IRQHandler /* 10 - TIMER1 */
|
||||
.long TIMER2_IRQHandler /* 11 - TIMER2 */
|
||||
.long USART1_RX_IRQHandler /* 12 - USART1_RX */
|
||||
.long USART1_TX_IRQHandler /* 13 - USART1_TX */
|
||||
.long USART2_RX_IRQHandler /* 14 - USART2_RX */
|
||||
.long USART2_TX_IRQHandler /* 15 - USART2_TX */
|
||||
.long UART0_RX_IRQHandler /* 16 - UART0_RX */
|
||||
.long UART0_TX_IRQHandler /* 17 - UART0_TX */
|
||||
.long LEUART0_IRQHandler /* 18 - LEUART0 */
|
||||
.long LEUART1_IRQHandler /* 19 - LEUART1 */
|
||||
.long LETIMER0_IRQHandler /* 20 - LETIMER0 */
|
||||
.long PCNT0_IRQHandler /* 21 - PCNT0 */
|
||||
.long PCNT1_IRQHandler /* 22 - PCNT1 */
|
||||
.long PCNT2_IRQHandler /* 23 - PCNT2 */
|
||||
.long RTC_IRQHandler /* 24 - RTC */
|
||||
.long CMU_IRQHandler /* 25 - CMU */
|
||||
.long VCMP_IRQHandler /* 26 - VCMP */
|
||||
.long LCD_IRQHandler /* 27 - LCD */
|
||||
.long MSC_IRQHandler /* 28 - MSC */
|
||||
.long AES_IRQHandler /* 29 - AES */
|
||||
|
||||
|
||||
.size __isr_vector, . - __isr_vector
|
||||
|
||||
.text
|
||||
.thumb
|
||||
.thumb_func
|
||||
.align 2
|
||||
.globl Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
/* Loop to copy data from read only memory to RAM. The ranges
|
||||
* of copy from/to are specified by following symbols evaluated in
|
||||
* linker script.
|
||||
* __etext: End of code section, i.e., begin of data sections to copy from.
|
||||
* __data_start__/__data_end__: RAM address range that data should be
|
||||
* copied to. Both must be aligned to 4 bytes boundary. */
|
||||
#ifndef __NO_SYSTEM_INIT
|
||||
ldr r0, =SystemInit
|
||||
blx r0
|
||||
#endif
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__data_end__
|
||||
|
||||
#if 1
|
||||
/* Here are two copies of loop implemenations. First one favors code size
|
||||
* and the second one favors performance. Default uses the first one.
|
||||
* Change to "#if 0" to use the second one */
|
||||
.flash_to_ram_loop:
|
||||
cmp r2, r3
|
||||
ittt lt
|
||||
ldrlt r0, [r1], #4
|
||||
strlt r0, [r2], #4
|
||||
blt .flash_to_ram_loop
|
||||
#else
|
||||
subs r3, r2
|
||||
ble .flash_to_ram_loop_end
|
||||
.flash_to_ram_loop:
|
||||
subs r3, #4
|
||||
ldr r0, [r1, r3]
|
||||
str r0, [r2, r3]
|
||||
bgt .flash_to_ram_loop
|
||||
.flash_to_ram_loop_end:
|
||||
#endif
|
||||
|
||||
ldr r0, =_start
|
||||
bx r0
|
||||
.pool
|
||||
.size Reset_Handler, . - Reset_Handler
|
||||
|
||||
/* Macro to define default handlers. Default handler
|
||||
* will be weak symbol and just dead loops. They can be
|
||||
* overwritten by other handlers */
|
||||
.macro def_irq_handler handler_name
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak \handler_name
|
||||
.type \handler_name, %function
|
||||
\handler_name:
|
||||
b .
|
||||
.size \handler_name, . - \handler_name
|
||||
.endm
|
||||
|
||||
def_irq_handler Default_Handler
|
||||
|
||||
def_irq_handler NMI_Handler
|
||||
def_irq_handler HardFault_Handler
|
||||
def_irq_handler MemManage_Handler
|
||||
def_irq_handler BusFault_Handler
|
||||
def_irq_handler UsageFault_Handler
|
||||
def_irq_handler SVC_Handler
|
||||
def_irq_handler DebugMon_Handler
|
||||
def_irq_handler PendSV_Handler
|
||||
def_irq_handler SysTick_Handler
|
||||
|
||||
def_irq_handler DMA_IRQHandler
|
||||
def_irq_handler GPIO_EVEN_IRQHandler
|
||||
def_irq_handler TIMER0_IRQHandler
|
||||
def_irq_handler USART0_RX_IRQHandler
|
||||
def_irq_handler USART0_TX_IRQHandler
|
||||
def_irq_handler ACMP0_IRQHandler
|
||||
def_irq_handler ADC0_IRQHandler
|
||||
def_irq_handler DAC0_IRQHandler
|
||||
def_irq_handler I2C0_IRQHandler
|
||||
def_irq_handler GPIO_ODD_IRQHandler
|
||||
def_irq_handler TIMER1_IRQHandler
|
||||
def_irq_handler TIMER2_IRQHandler
|
||||
def_irq_handler USART1_RX_IRQHandler
|
||||
def_irq_handler USART1_TX_IRQHandler
|
||||
def_irq_handler USART2_RX_IRQHandler
|
||||
def_irq_handler USART2_TX_IRQHandler
|
||||
def_irq_handler UART0_RX_IRQHandler
|
||||
def_irq_handler UART0_TX_IRQHandler
|
||||
def_irq_handler LEUART0_IRQHandler
|
||||
def_irq_handler LEUART1_IRQHandler
|
||||
def_irq_handler LETIMER0_IRQHandler
|
||||
def_irq_handler PCNT0_IRQHandler
|
||||
def_irq_handler PCNT1_IRQHandler
|
||||
def_irq_handler PCNT2_IRQHandler
|
||||
def_irq_handler RTC_IRQHandler
|
||||
def_irq_handler CMU_IRQHandler
|
||||
def_irq_handler VCMP_IRQHandler
|
||||
def_irq_handler LCD_IRQHandler
|
||||
def_irq_handler MSC_IRQHandler
|
||||
def_irq_handler AES_IRQHandler
|
||||
|
||||
|
||||
.end
|
||||
|
|
@ -0,0 +1,299 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief CMSIS Compatible EFM32G startup file in C for IAR EWARM
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#include "em_device.h" /* The correct device header file. */
|
||||
|
||||
#pragma language=extended
|
||||
#pragma segment="CSTACK"
|
||||
|
||||
/* IAR start function */
|
||||
extern void __iar_program_start(void);
|
||||
/* CMSIS init function */
|
||||
extern void SystemInit(void);
|
||||
|
||||
/* Auto defined by linker */
|
||||
extern unsigned char CSTACK$$Limit;
|
||||
|
||||
__weak void Reset_Handler(void)
|
||||
{
|
||||
SystemInit();
|
||||
__iar_program_start();
|
||||
}
|
||||
|
||||
__weak void NMI_Handler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void HardFault_Handler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void MemManage_Handler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void BusFault_Handler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void UsageFault_Handler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void SVC_Handler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void DebugMon_Handler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void PendSV_Handler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void SysTick_Handler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void DMA_IRQHandler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void GPIO_EVEN_IRQHandler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void TIMER0_IRQHandler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void USART0_RX_IRQHandler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void USART0_TX_IRQHandler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void ACMP0_IRQHandler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void ADC0_IRQHandler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void DAC0_IRQHandler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void I2C0_IRQHandler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void GPIO_ODD_IRQHandler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void TIMER1_IRQHandler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void TIMER2_IRQHandler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void USART1_RX_IRQHandler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void USART1_TX_IRQHandler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void USART2_RX_IRQHandler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void USART2_TX_IRQHandler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void UART0_RX_IRQHandler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void UART0_TX_IRQHandler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void LEUART0_IRQHandler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void LEUART1_IRQHandler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void LETIMER0_IRQHandler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void PCNT0_IRQHandler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void PCNT1_IRQHandler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void PCNT2_IRQHandler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void RTC_IRQHandler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void CMU_IRQHandler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void VCMP_IRQHandler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void LCD_IRQHandler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void MSC_IRQHandler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
__weak void AES_IRQHandler(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
|
||||
/* With IAR, the CSTACK is defined via project options settings */
|
||||
#pragma data_alignment=256
|
||||
#pragma location = ".intvec"
|
||||
const void * const __vector_table[]= {
|
||||
&CSTACK$$Limit,
|
||||
(void *) Reset_Handler, /* 1 - Reset (start instruction) */
|
||||
(void *) NMI_Handler, /* 2 - NMI */
|
||||
(void *) HardFault_Handler, /* 3 - HardFault */
|
||||
(void *) MemManage_Handler,
|
||||
(void *) BusFault_Handler,
|
||||
(void *) UsageFault_Handler,
|
||||
(void *) 0,
|
||||
(void *) 0,
|
||||
(void *) 0,
|
||||
(void *) 0,
|
||||
(void *) SVC_Handler,
|
||||
(void *) DebugMon_Handler,
|
||||
(void *) 0,
|
||||
(void *) PendSV_Handler,
|
||||
(void *) SysTick_Handler,
|
||||
(void *) DMA_IRQHandler, /* 0 - DMA */
|
||||
(void *) GPIO_EVEN_IRQHandler, /* 1 - GPIO_EVEN */
|
||||
(void *) TIMER0_IRQHandler, /* 2 - TIMER0 */
|
||||
(void *) USART0_RX_IRQHandler, /* 3 - USART0_RX */
|
||||
(void *) USART0_TX_IRQHandler, /* 4 - USART0_TX */
|
||||
(void *) ACMP0_IRQHandler, /* 5 - ACMP0 */
|
||||
(void *) ADC0_IRQHandler, /* 6 - ADC0 */
|
||||
(void *) DAC0_IRQHandler, /* 7 - DAC0 */
|
||||
(void *) I2C0_IRQHandler, /* 8 - I2C0 */
|
||||
(void *) GPIO_ODD_IRQHandler, /* 9 - GPIO_ODD */
|
||||
(void *) TIMER1_IRQHandler, /* 10 - TIMER1 */
|
||||
(void *) TIMER2_IRQHandler, /* 11 - TIMER2 */
|
||||
(void *) USART1_RX_IRQHandler, /* 12 - USART1_RX */
|
||||
(void *) USART1_TX_IRQHandler, /* 13 - USART1_TX */
|
||||
(void *) USART2_RX_IRQHandler, /* 14 - USART2_RX */
|
||||
(void *) USART2_TX_IRQHandler, /* 15 - USART2_TX */
|
||||
(void *) UART0_RX_IRQHandler, /* 16 - UART0_RX */
|
||||
(void *) UART0_TX_IRQHandler, /* 17 - UART0_TX */
|
||||
(void *) LEUART0_IRQHandler, /* 18 - LEUART0 */
|
||||
(void *) LEUART1_IRQHandler, /* 19 - LEUART1 */
|
||||
(void *) LETIMER0_IRQHandler, /* 20 - LETIMER0 */
|
||||
(void *) PCNT0_IRQHandler, /* 21 - PCNT0 */
|
||||
(void *) PCNT1_IRQHandler, /* 22 - PCNT1 */
|
||||
(void *) PCNT2_IRQHandler, /* 23 - PCNT2 */
|
||||
(void *) RTC_IRQHandler, /* 24 - RTC */
|
||||
(void *) CMU_IRQHandler, /* 25 - CMU */
|
||||
(void *) VCMP_IRQHandler, /* 26 - VCMP */
|
||||
(void *) LCD_IRQHandler, /* 27 - LCD */
|
||||
(void *) MSC_IRQHandler, /* 28 - MSC */
|
||||
(void *) AES_IRQHandler, /* 29 - AES */
|
||||
|
||||
};
|
||||
|
|
@ -0,0 +1,330 @@
|
|||
;/**************************************************************************//**
|
||||
; * @file
|
||||
; * @brief CMSIS Core Device Startup File
|
||||
; * Energy Micro EFM32G Device Series
|
||||
; * @version 3.20.0
|
||||
; * @date 30. January 2012
|
||||
; *
|
||||
; * @note
|
||||
; * Copyright (C) 2012 ARM Limited. All rights reserved.
|
||||
; *
|
||||
; * @par
|
||||
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
; * processor based microcontrollers. This file can be freely distributed
|
||||
; * within development tools that are supporting such ARM based processors.
|
||||
; *
|
||||
; * @par
|
||||
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
;
|
||||
; When debugging in RAM, it can be located in RAM with at least a 128 byte
|
||||
; alignment, 256 byte alignment is requied if all interrupt vectors are in use.
|
||||
;
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(8)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
PUBLIC __vector_table_0x1c
|
||||
PUBLIC __Vectors
|
||||
PUBLIC __Vectors_End
|
||||
PUBLIC __Vectors_Size
|
||||
|
||||
DATA
|
||||
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler
|
||||
|
||||
DCD NMI_Handler
|
||||
DCD HardFault_Handler
|
||||
DCD MemManage_Handler
|
||||
DCD BusFault_Handler
|
||||
DCD UsageFault_Handler
|
||||
__vector_table_0x1c
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD SVC_Handler
|
||||
DCD DebugMon_Handler
|
||||
DCD 0
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD DMA_IRQHandler ; 0: DMA Interrupt
|
||||
DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt
|
||||
DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt
|
||||
DCD USART0_RX_IRQHandler ; 3: USART0_RX Interrupt
|
||||
DCD USART0_TX_IRQHandler ; 4: USART0_TX Interrupt
|
||||
DCD ACMP0_IRQHandler ; 5: ACMP0 Interrupt
|
||||
DCD ADC0_IRQHandler ; 6: ADC0 Interrupt
|
||||
DCD DAC0_IRQHandler ; 7: DAC0 Interrupt
|
||||
DCD I2C0_IRQHandler ; 8: I2C0 Interrupt
|
||||
DCD GPIO_ODD_IRQHandler ; 9: GPIO_ODD Interrupt
|
||||
DCD TIMER1_IRQHandler ; 10: TIMER1 Interrupt
|
||||
DCD TIMER2_IRQHandler ; 11: TIMER2 Interrupt
|
||||
DCD USART1_RX_IRQHandler ; 12: USART1_RX Interrupt
|
||||
DCD USART1_TX_IRQHandler ; 13: USART1_TX Interrupt
|
||||
DCD USART2_RX_IRQHandler ; 14: USART2_RX Interrupt
|
||||
DCD USART2_TX_IRQHandler ; 15: USART2_TX Interrupt
|
||||
DCD UART0_RX_IRQHandler ; 16: UART0_RX Interrupt
|
||||
DCD UART0_TX_IRQHandler ; 17: UART0_TX Interrupt
|
||||
DCD LEUART0_IRQHandler ; 18: LEUART0 Interrupt
|
||||
DCD LEUART1_IRQHandler ; 19: LEUART1 Interrupt
|
||||
DCD LETIMER0_IRQHandler ; 20: LETIMER0 Interrupt
|
||||
DCD PCNT0_IRQHandler ; 21: PCNT0 Interrupt
|
||||
DCD PCNT1_IRQHandler ; 22: PCNT1 Interrupt
|
||||
DCD PCNT2_IRQHandler ; 23: PCNT2 Interrupt
|
||||
DCD RTC_IRQHandler ; 24: RTC Interrupt
|
||||
DCD CMU_IRQHandler ; 25: CMU Interrupt
|
||||
DCD VCMP_IRQHandler ; 26: VCMP Interrupt
|
||||
DCD LCD_IRQHandler ; 27: LCD Interrupt
|
||||
DCD MSC_IRQHandler ; 28: MSC Interrupt
|
||||
DCD AES_IRQHandler ; 29: AES Interrupt
|
||||
|
||||
|
||||
__Vectors_End
|
||||
__Vectors EQU __vector_table
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
; Device specific interrupt handlers
|
||||
|
||||
PUBWEAK DMA_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA_IRQHandler
|
||||
B DMA_IRQHandler
|
||||
|
||||
PUBWEAK GPIO_EVEN_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
GPIO_EVEN_IRQHandler
|
||||
B GPIO_EVEN_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIMER0_IRQHandler
|
||||
B TIMER0_IRQHandler
|
||||
|
||||
PUBWEAK USART0_RX_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
USART0_RX_IRQHandler
|
||||
B USART0_RX_IRQHandler
|
||||
|
||||
PUBWEAK USART0_TX_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
USART0_TX_IRQHandler
|
||||
B USART0_TX_IRQHandler
|
||||
|
||||
PUBWEAK ACMP0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
ACMP0_IRQHandler
|
||||
B ACMP0_IRQHandler
|
||||
|
||||
PUBWEAK ADC0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
ADC0_IRQHandler
|
||||
B ADC0_IRQHandler
|
||||
|
||||
PUBWEAK DAC0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DAC0_IRQHandler
|
||||
B DAC0_IRQHandler
|
||||
|
||||
PUBWEAK I2C0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
I2C0_IRQHandler
|
||||
B I2C0_IRQHandler
|
||||
|
||||
PUBWEAK GPIO_ODD_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
GPIO_ODD_IRQHandler
|
||||
B GPIO_ODD_IRQHandler
|
||||
|
||||
PUBWEAK TIMER1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIMER1_IRQHandler
|
||||
B TIMER1_IRQHandler
|
||||
|
||||
PUBWEAK TIMER2_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIMER2_IRQHandler
|
||||
B TIMER2_IRQHandler
|
||||
|
||||
PUBWEAK USART1_RX_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
USART1_RX_IRQHandler
|
||||
B USART1_RX_IRQHandler
|
||||
|
||||
PUBWEAK USART1_TX_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
USART1_TX_IRQHandler
|
||||
B USART1_TX_IRQHandler
|
||||
|
||||
PUBWEAK USART2_RX_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
USART2_RX_IRQHandler
|
||||
B USART2_RX_IRQHandler
|
||||
|
||||
PUBWEAK USART2_TX_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
USART2_TX_IRQHandler
|
||||
B USART2_TX_IRQHandler
|
||||
|
||||
PUBWEAK UART0_RX_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
UART0_RX_IRQHandler
|
||||
B UART0_RX_IRQHandler
|
||||
|
||||
PUBWEAK UART0_TX_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
UART0_TX_IRQHandler
|
||||
B UART0_TX_IRQHandler
|
||||
|
||||
PUBWEAK LEUART0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
LEUART0_IRQHandler
|
||||
B LEUART0_IRQHandler
|
||||
|
||||
PUBWEAK LEUART1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
LEUART1_IRQHandler
|
||||
B LEUART1_IRQHandler
|
||||
|
||||
PUBWEAK LETIMER0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
LETIMER0_IRQHandler
|
||||
B LETIMER0_IRQHandler
|
||||
|
||||
PUBWEAK PCNT0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
PCNT0_IRQHandler
|
||||
B PCNT0_IRQHandler
|
||||
|
||||
PUBWEAK PCNT1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
PCNT1_IRQHandler
|
||||
B PCNT1_IRQHandler
|
||||
|
||||
PUBWEAK PCNT2_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
PCNT2_IRQHandler
|
||||
B PCNT2_IRQHandler
|
||||
|
||||
PUBWEAK RTC_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
RTC_IRQHandler
|
||||
B RTC_IRQHandler
|
||||
|
||||
PUBWEAK CMU_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
CMU_IRQHandler
|
||||
B CMU_IRQHandler
|
||||
|
||||
PUBWEAK VCMP_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
VCMP_IRQHandler
|
||||
B VCMP_IRQHandler
|
||||
|
||||
PUBWEAK LCD_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
LCD_IRQHandler
|
||||
B LCD_IRQHandler
|
||||
|
||||
PUBWEAK MSC_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
MSC_IRQHandler
|
||||
B MSC_IRQHandler
|
||||
|
||||
PUBWEAK AES_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
AES_IRQHandler
|
||||
B AES_IRQHandler
|
||||
|
||||
|
||||
END
|
||||
|
|
@ -0,0 +1,386 @@
|
|||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief CMSIS Cortex-M3 System Layer for EFM32G devices.
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
*******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "em_device.h"
|
||||
|
||||
/*******************************************************************************
|
||||
****************************** DEFINES ************************************
|
||||
******************************************************************************/
|
||||
|
||||
/** LFRCO frequency, tuned to below frequency during manufacturing. */
|
||||
#define EFM32_LFRCO_FREQ (32768UL)
|
||||
#define EFM32_ULFRCO_FREQ (1000UL)
|
||||
|
||||
/*******************************************************************************
|
||||
************************** LOCAL VARIABLES ********************************
|
||||
******************************************************************************/
|
||||
|
||||
/* System oscillator frequencies. These frequencies are normally constant */
|
||||
/* for a target, but they are made configurable in order to allow run-time */
|
||||
/* handling of different boards. The crystal oscillator clocks can be set */
|
||||
/* compile time to a non-default value by defining respective EFM32_nFXO_FREQ */
|
||||
/* values according to board design. By defining the EFM32_nFXO_FREQ to 0, */
|
||||
/* one indicates that the oscillator is not present, in order to save some */
|
||||
/* SW footprint. */
|
||||
|
||||
#ifndef EFM32_HFXO_FREQ
|
||||
#ifdef _EFM32_GIANT_FAMILY
|
||||
#define EFM32_HFXO_FREQ (48000000UL)
|
||||
#else
|
||||
#define EFM32_HFXO_FREQ (32000000UL)
|
||||
#endif
|
||||
#endif
|
||||
/* Do not define variable if HF crystal oscillator not present */
|
||||
#if (EFM32_HFXO_FREQ > 0)
|
||||
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
|
||||
/** System HFXO clock. */
|
||||
static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ;
|
||||
/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
|
||||
#endif
|
||||
|
||||
#ifndef EFM32_LFXO_FREQ
|
||||
#define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ)
|
||||
#endif
|
||||
/* Do not define variable if LF crystal oscillator not present */
|
||||
#if (EFM32_LFXO_FREQ > 0)
|
||||
/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
|
||||
/** System LFXO clock. */
|
||||
static uint32_t SystemLFXOClock = EFM32_LFXO_FREQ;
|
||||
/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
|
||||
#endif
|
||||
|
||||
/* Inline function to get the chip's Production Revision. */
|
||||
__STATIC_INLINE uint8_t GetProdRev(void)
|
||||
{
|
||||
return ((DEVINFO->PART & _DEVINFO_PART_PROD_REV_MASK)
|
||||
>> _DEVINFO_PART_PROD_REV_SHIFT);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
************************** GLOBAL VARIABLES *******************************
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief
|
||||
* System System Clock Frequency (Core Clock).
|
||||
*
|
||||
* @details
|
||||
* Required CMSIS global variable that must be kept up-to-date.
|
||||
*/
|
||||
uint32_t SystemCoreClock;
|
||||
|
||||
/*******************************************************************************
|
||||
************************** GLOBAL FUNCTIONS *******************************
|
||||
******************************************************************************/
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief
|
||||
* Get the current core clock frequency.
|
||||
*
|
||||
* @details
|
||||
* Calculate and get the current core clock frequency based on the current
|
||||
* configuration. Assuming that the SystemCoreClock global variable is
|
||||
* maintained, the core clock frequency is stored in that variable as well.
|
||||
* This function will however calculate the core clock based on actual HW
|
||||
* configuration. It will also update the SystemCoreClock global variable.
|
||||
*
|
||||
* @note
|
||||
* This is an EFM32 proprietary function, not part of the CMSIS definition.
|
||||
*
|
||||
* @return
|
||||
* The current core clock frequency in Hz.
|
||||
******************************************************************************/
|
||||
uint32_t SystemCoreClockGet(void)
|
||||
{
|
||||
uint32_t ret;
|
||||
|
||||
ret = SystemHFClockGet();
|
||||
#if defined (_EFM32_GIANT_FAMILY)
|
||||
/* Leopard/Giant Gecko has an additional divider */
|
||||
ret = ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)>>_CMU_CTRL_HFCLKDIV_SHIFT));
|
||||
#endif
|
||||
ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >>
|
||||
_CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT;
|
||||
|
||||
/* Keep CMSIS variable up-to-date just in case */
|
||||
SystemCoreClock = ret;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief
|
||||
* Get the current HFCLK frequency.
|
||||
*
|
||||
* @note
|
||||
* This is an EFM32 proprietary function, not part of the CMSIS definition.
|
||||
*
|
||||
* @return
|
||||
* The current HFCLK frequency in Hz.
|
||||
******************************************************************************/
|
||||
uint32_t SystemHFClockGet(void)
|
||||
{
|
||||
uint32_t ret;
|
||||
|
||||
switch (CMU->STATUS & (CMU_STATUS_HFRCOSEL | CMU_STATUS_HFXOSEL |
|
||||
CMU_STATUS_LFRCOSEL | CMU_STATUS_LFXOSEL))
|
||||
{
|
||||
case CMU_STATUS_LFXOSEL:
|
||||
#if (EFM32_LFXO_FREQ > 0)
|
||||
ret = SystemLFXOClock;
|
||||
#else
|
||||
/* We should not get here, since core should not be clocked. May */
|
||||
/* be caused by a misconfiguration though. */
|
||||
ret = 0;
|
||||
#endif
|
||||
break;
|
||||
|
||||
case CMU_STATUS_LFRCOSEL:
|
||||
ret = EFM32_LFRCO_FREQ;
|
||||
break;
|
||||
|
||||
case CMU_STATUS_HFXOSEL:
|
||||
#if (EFM32_HFXO_FREQ > 0)
|
||||
ret = SystemHFXOClock;
|
||||
#else
|
||||
/* We should not get here, since core should not be clocked. May */
|
||||
/* be caused by a misconfiguration though. */
|
||||
ret = 0;
|
||||
#endif
|
||||
break;
|
||||
|
||||
default: /* CMU_STATUS_HFRCOSEL */
|
||||
switch (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK)
|
||||
{
|
||||
case CMU_HFRCOCTRL_BAND_28MHZ:
|
||||
ret = 28000000;
|
||||
break;
|
||||
|
||||
case CMU_HFRCOCTRL_BAND_21MHZ:
|
||||
ret = 21000000;
|
||||
break;
|
||||
|
||||
case CMU_HFRCOCTRL_BAND_14MHZ:
|
||||
ret = 14000000;
|
||||
break;
|
||||
|
||||
case CMU_HFRCOCTRL_BAND_11MHZ:
|
||||
ret = 11000000;
|
||||
break;
|
||||
|
||||
case CMU_HFRCOCTRL_BAND_7MHZ:
|
||||
if ( GetProdRev() >= 19 )
|
||||
ret = 6600000;
|
||||
else
|
||||
ret = 7000000;
|
||||
break;
|
||||
|
||||
case CMU_HFRCOCTRL_BAND_1MHZ:
|
||||
if ( GetProdRev() >= 19 )
|
||||
ret = 1200000;
|
||||
else
|
||||
ret = 1000000;
|
||||
break;
|
||||
|
||||
default:
|
||||
ret = 0;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
/**************************************************************************//**
|
||||
* @brief
|
||||
* Get high frequency crystal oscillator clock frequency for target system.
|
||||
*
|
||||
* @note
|
||||
* This is an EFM32 proprietary function, not part of the CMSIS definition.
|
||||
*
|
||||
* @return
|
||||
* HFXO frequency in Hz.
|
||||
*****************************************************************************/
|
||||
uint32_t SystemHFXOClockGet(void)
|
||||
{
|
||||
/* External crystal oscillator present? */
|
||||
#if (EFM32_HFXO_FREQ > 0)
|
||||
return SystemHFXOClock;
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**************************************************************************//**
|
||||
* @brief
|
||||
* Set high frequency crystal oscillator clock frequency for target system.
|
||||
*
|
||||
* @note
|
||||
* This function is mainly provided for being able to handle target systems
|
||||
* with different HF crystal oscillator frequencies run-time. If used, it
|
||||
* should probably only be used once during system startup.
|
||||
*
|
||||
* @note
|
||||
* This is an EFM32 proprietary function, not part of the CMSIS definition.
|
||||
*
|
||||
* @param[in] freq
|
||||
* HFXO frequency in Hz used for target.
|
||||
*****************************************************************************/
|
||||
void SystemHFXOClockSet(uint32_t freq)
|
||||
{
|
||||
/* External crystal oscillator present? */
|
||||
#if (EFM32_HFXO_FREQ > 0)
|
||||
SystemHFXOClock = freq;
|
||||
|
||||
/* Update core clock frequency if HFXO is used to clock core */
|
||||
if (CMU->STATUS & CMU_STATUS_HFXOSEL)
|
||||
{
|
||||
/* The function will update the global variable */
|
||||
SystemCoreClockGet();
|
||||
}
|
||||
#else
|
||||
(void)freq; /* Unused parameter */
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**************************************************************************//**
|
||||
* @brief
|
||||
* Initialize the system.
|
||||
*
|
||||
* @details
|
||||
* Do required generic HW system init.
|
||||
*
|
||||
* @note
|
||||
* This function is invoked during system init, before the main() routine
|
||||
* and any data has been initialized. For this reason, it cannot do any
|
||||
* initialization of variables etc.
|
||||
*****************************************************************************/
|
||||
void SystemInit(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
/**************************************************************************//**
|
||||
* @brief
|
||||
* Get low frequency RC oscillator clock frequency for target system.
|
||||
*
|
||||
* @note
|
||||
* This is an EFM32 proprietary function, not part of the CMSIS definition.
|
||||
*
|
||||
* @return
|
||||
* LFRCO frequency in Hz.
|
||||
*****************************************************************************/
|
||||
uint32_t SystemLFRCOClockGet(void)
|
||||
{
|
||||
/* Currently we assume that this frequency is properly tuned during */
|
||||
/* manufacturing and is not changed after reset. If future requirements */
|
||||
/* for re-tuning by user, we can add support for that. */
|
||||
return EFM32_LFRCO_FREQ;
|
||||
}
|
||||
|
||||
|
||||
/**************************************************************************//**
|
||||
* @brief
|
||||
* Get ultra low frequency RC oscillator clock frequency for target system.
|
||||
*
|
||||
* @note
|
||||
* This is an EFM32 proprietary function, not part of the CMSIS definition.
|
||||
*
|
||||
* @return
|
||||
* ULFRCO frequency in Hz.
|
||||
*****************************************************************************/
|
||||
uint32_t SystemULFRCOClockGet(void)
|
||||
{
|
||||
/* The ULFRCO frequency is not tuned, and can be very inaccurate */
|
||||
return EFM32_ULFRCO_FREQ;
|
||||
}
|
||||
|
||||
|
||||
/**************************************************************************//**
|
||||
* @brief
|
||||
* Get low frequency crystal oscillator clock frequency for target system.
|
||||
*
|
||||
* @note
|
||||
* This is an EFM32 proprietary function, not part of the CMSIS definition.
|
||||
*
|
||||
* @return
|
||||
* LFXO frequency in Hz.
|
||||
*****************************************************************************/
|
||||
uint32_t SystemLFXOClockGet(void)
|
||||
{
|
||||
/* External crystal oscillator present? */
|
||||
#if (EFM32_LFXO_FREQ > 0)
|
||||
return SystemLFXOClock;
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**************************************************************************//**
|
||||
* @brief
|
||||
* Set low frequency crystal oscillator clock frequency for target system.
|
||||
*
|
||||
* @note
|
||||
* This function is mainly provided for being able to handle target systems
|
||||
* with different HF crystal oscillator frequencies run-time. If used, it
|
||||
* should probably only be used once during system startup.
|
||||
*
|
||||
* @note
|
||||
* This is an EFM32 proprietary function, not part of the CMSIS definition.
|
||||
*
|
||||
* @param[in] freq
|
||||
* LFXO frequency in Hz used for target.
|
||||
*****************************************************************************/
|
||||
void SystemLFXOClockSet(uint32_t freq)
|
||||
{
|
||||
/* External crystal oscillator present? */
|
||||
#if (EFM32_LFXO_FREQ > 0)
|
||||
SystemLFXOClock = freq;
|
||||
|
||||
/* Update core clock frequency if LFXO is used to clock core */
|
||||
if (CMU->STATUS & CMU_STATUS_LFXOSEL)
|
||||
{
|
||||
/* The function will update the global variable */
|
||||
SystemCoreClockGet();
|
||||
}
|
||||
#else
|
||||
(void)freq; /* Unused parameter */
|
||||
#endif
|
||||
}
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/**************************************************************************//**
|
||||
* @file
|
||||
* @brief CMSIS Cortex Peripheral Access Layer for EFM32 device series
|
||||
*
|
||||
* This is a convenience header file for defining the EFM32 part number on the
|
||||
* build command line, instead of specifying the part specific header file.
|
||||
* @verbatim
|
||||
* Example: Add "-DEFM32G890F128" to your build options, to define part
|
||||
* Add "#include "efm32.h" to your source files
|
||||
* @endverbatim
|
||||
* @author Energy Micro AS
|
||||
* @version 3.20.0
|
||||
******************************************************************************
|
||||
* @section License
|
||||
* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
|
||||
******************************************************************************
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
|
||||
* obligation to support this Software. Energy Micro AS is providing the
|
||||
* Software "AS IS", with no express or implied warranties of any kind,
|
||||
* including, but not limited to, any implied warranties of merchantability
|
||||
* or fitness for any particular purpose or warranties against infringement
|
||||
* of any proprietary rights of a third party.
|
||||
*
|
||||
* Energy Micro AS will not be liable for any consequential, incidental, or
|
||||
* special damages, or any other relief, or for any claim by any third party,
|
||||
* arising from your use of this Software.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __EFM32_H
|
||||
#define __EFM32_H
|
||||
|
||||
/* This file is kept for backwards compability. */
|
||||
|
||||
#include "em_device.h"
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue